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STSLVDSP27

STSLVDSP27

  • 厂商:

    STMICROELECTRONICS(意法半导体)

  • 封装:

  • 描述:

    STSLVDSP27 - 8-bit low voltage serializer with 1.8V high speed dual differential line drivers and em...

  • 数据手册
  • 价格&库存
STSLVDSP27 数据手册
STSLVDSP27 8-bit low voltage serializer with 1.8V high speed dual differential line drivers and embedded DPLL Features ■ ■ ■ Sub-low voltage differential signaling: VOD = 150mV with RT = 100Ω, CL = 10pF Clock range: 4 to 27 MHz in parallel mode, BYP = Gnd Operative frequency serial mode, BYP = VDD; DIN0 to DOUT, CLKIN to CLKOUT, fOPR = 1 to 208 MHz max Embedded DPLL requires no external components Output voltage rise and fall times trVOD = tfVOD = 610ps typ at fOPR = 208MHz High speed propagation delay times tpLH~tpHL= 2.1ns typ at VDD = 3.0V; VIO = 1.8V Operating voltage range: VDD (OPR) = 2.5V to 3.6V VIO (OPR) = 1.65V to 1.95V High impedance on driver outputs IOZ = 1µA max; EN = Gnd; VO = Gnd or VIO Low voltage CMOS input threshold (DIN0-DIN7, CLKIN, EN, BYP, DVO, DV1) VIL = 0.3 x VDD max; VIH = 0.7 x VDD min 3.6V tolerant on all inputs (DIN0-DIN7, CLKIN, EN, BYP, DV0, DV1) Lead-free Flip-Chip package SMIA CCP1 (MIPI CSI-1) compatible PHY Flip-Chip20 ■ ■ ■ ■ ■ ■ ■ ■ ■ Description The STSLVDSP27 is an 8:1 bit serializer with embedded DPLL. The dual differential line drivers implement the electrical characteristics of sub-low voltage differential signaling (subLVDS), bringing out the serialized data and related synchronous clock signal. The STSLVDSP27 serializer IC is provided with two power supply rails, VDD and VIO. The first supply is related to the logic levels of the input data (DIN0-DIN7, CLKIN) and Enables (EN, BYP, DV0, DV1) pins. VIO provides the power supply to the output current drivers in the device. VIO is always expected to be a nominal 1.8V. VDD depends on the application, but will always be equal to or higher than VIO. In order to minimize static current consumption, it is possible to shut down the transmitters when the interface is not used by setting a power-down (EN) pin. This operation reduces the maximum current consumption to 20µA, making this device ideal for portable applications like mobile phones and portable battery equipment. Simplified functionality can be reached using the BYP select pin, which disables the internal DPLL circuitry. When this pin is High the device can work with serialized signals from DIN0 input only. A synchronous CLKIN signal must be provided and it will be put-out using subLVDS level by CLKOUT port; the sub-LVDS data will be put-out by DOUT port at a maximum frequency of 208Mhz. This innovative device provides an optimized high-speed link solution from different CMOS sensor devices (parallel or serial outputs) to more advanced graphic controllers in mobile phone applications. All inputs and outputs are equipped with protection circuits against static discharge, providing ESD immunity from transient excess voltage. The STSLVDSP27 is designed for operation over the commercial temperature range -40°C to 85°C. Order code Part number STSLVDSP27BJR June 2007 Temperature range -40 to 85 °C Rev. 1 Package Flip-Chip20 (Tape & Reel) Packaging 3000 parts per reel 1/23 www.st.com 23 STSLVDSP27 Contents 1 2 3 4 5 6 7 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Test circuits and timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 2/23 STSLVDSP27 Block diagram 1 Figure 1. Block diagram Simplified block diagram typical application 3/23 Pin configuration STSLVDSP27 2 Figure 2. Pin configuration Pin configuration and logic diagram (Top view - Bumps are on the other side) Table 1. Pin description PlN N° B1 Symbol DIN0 DIN1-DIN7 DOUT+, DOUTCLKIN CLKOUT+, CLKOUTDV0, DV1 GND VDD VIO EN BYP Name and function CMOS parallel/serial data inputs CMOS parallel data inputs SubLVDS driver data outputs CMOS parallel/serial clock input SubLVDS driver clock outputs CMOS data valid inputs Ground Main power supply voltage SubLVDS bus output supply voltage CMOS main chip enable input CMOS by-pass select input A1, A2, A3, A4, B4, C4, D4 D1, C1 B3 D3, C3 C2, D2 B2 E1 E2 E3 E4 4/23 STSLVDSP27 Pin configuration Table 2. Controls EN L H H H H Truth table (bypass functionality: DIN0 => DOUT, CLKIN => CLKOUT; main chip Enable(1) functionality) Input DV0 X X X X X DV1 X X X X X DIN0 X L L H H DIN1-7 CLKIN X X X X X X L H L H DOUT+ Z L L H H Differential outputs DOUTZ H H L L CLKOUT+ Z L H L H CLKOUTZ H L H L BYP X H H H H 1. All differential outputs are put in high impedance vs gnd only; the internal DPLL circuit is put in shutdown mode to obtain minimum power consumption. Note: Table 3. Controls EN H H n:0..1; Z = High Impedance, X = Don’t care Truth table (data valid functionality) Input DV0(1) L X DV1(1) X L DIN0 X X DIN1-7 CLKIN X X X X DOUT+ H H Differential outputs DOUTL L CLKOUT+ H H CLKOUTL L BYP L L 1. An AND gate is designed on Data Valid Inputs (DV0, DV1) to enable the standard functionality; only when the DV0=DV1="H" the device will work according to description in main page Note: n:0..1; Z = High Impedance, X = Don’t care 5/23 Maximum ratings STSLVDSP27 3 Table 4. Symbol VDD VIO VI VO ESD TSTG Maximum ratings Absolute maximum ratings Parameter Supply voltage SubLVDS bus supply voltage DC input voltage (DIN0-DIN7, BYP, CLKIN, EN, DV0, DV1) DC output voltage (DOUT+,DOUT-,CLKOUT+,CLKOUT-) Electrostatic discharge protection IEC61000-4-2 Contact R = 330Ω C = 150pF (All Pins vs GND) , Storage temperature range Value -0.5 to 4.6 -0.5 to 4.6 -0.5 to 4.6 -0.5 to (VIO + 0.5) ±2 -65 to +150 Unit V V V V KV °C Note: Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these condition is not implied. Recommended operating conditions Parameter Main supply voltage (1) (2) SubLVDS bus supply voltage (2) Table 5. Symbol VDD VIO Min. 2.5 1.65 Typ. 3.0 1.80 Max. 3.6 1.95 100 Unit V V mV Ω pF VDD_NOISE Peak-to-peak permitted main supply voltage noise RT CL TA TJ tR, tF Termination resistance (per pair differential output line) Termination capacitance (per line vs GND Pin) Operating ambient temperature range Operating junction temperature range Rise and fall time (DIN0-DIN7, BYP, CLKIN, EN, DV0, DV1; 10% to 90%; 90% to 10%) 80 100 10 120 -40 -40 85 125 10 °C °C ns 1. VDD Main supply voltage in serial mode (BYP = VDD) can be reduced down to 1.65V for typical 1.8V input signals 2. VDD Main supply voltage in parallel mode (BYP = GND) can reach 2.5V when VDD_NOISE = 100mV and VDD = 2.55V 6/23 STSLVDSP27 Electrical characteristics 4 Table 6. Symbol VCM Electrical characteristics Electrical characteristics (over recommended operating conditions unless otherwise noted. All typical values are at TA = 25°C, and VDD = 3.0V, VIO = 1.8V) Parameter Common mode output voltage (Figure 3.) Test conditions RT = 100Ω ± 1% Min. VIO/20.1 Typ. VIO/2 Max. VIO/2+ 0.1 Unit V Common mode output voltage change between VCM(SS) logic state ("L" and "H") (Figure 5.) Common mode peak-topeak output voltage change VCM(PP) between logic state ("L" and "H") (Figure 5.) |VOD| ΔVOD Differential output voltage (Figure 3.) Differential output voltage change between logic state ("L" and "H") RT = 100Ω ± 1% -20 20 mV RT = 100Ω ± 1% -40 40 mV RT = 100Ω ± 1% RT = 100Ω ± 1% 100 150 200 mV -20 20 mV Clock duty cycle@208MHz differential output voltage DCVOD CLKOUT+, CLKOUT-, DOUT+, DOUTIIO Driver output current CLKOUT+, CLKOUT-, DOUT+, DOUTDriver output impedance (Single ended) CLKOUT+, CLKOUT-, DOUT+, DOUT- (Figure 8.) Driver output impedance mismatch between RODOUT, ROCLKOUT RT = 100Ω ± 1% BYP=VDD; EN=VDD fCLKIN = 208MHz, fDIN0 = 208MHz 45 50 55 % RT = 100Ω ± 1% 1 1.5 2 mA RO VCM = VIO/2 + 100mV and VIO/2 -100mV 40 100 140 Ω DRO 10 % 7/23 Electrical characteristics Table 6. Symbol STSLVDSP27 Electrical characteristics (over recommended operating conditions unless otherwise noted. All typical values are at TA = 25°C, and VDD = 3.0V, VIO = 1.8V) Parameter Test conditions EN=VDD, BYP=VDD or GND, DIN0-DIN7=VDD or GND ) No load (RT = ∞ EN=VDD, BYP=VDD or GND, DIN0-DIN7=VDD or GND RT = 100Ω ± 1% Min. Typ. Max. 15 Unit 15 IS Supply current (IIO + IDD) EN=VDD, BYP=VDD(DPLL="OFF") RT = 100Ω ± 1%, CL = 10pF per line, DV0=DV1=VDD, fDIN0 and CLKIN = 208 MHz (VIL and VIH levels) EN=VDD, BYP=Gnd(DPLL="ON") RT = 100Ω ± 1%, CL = 10pF per line, DV0 = DV1= VDD, fCLKOUT = 160MHz fDIN0-DIN7,CLKIN = 22 MHz (VIL and VIH levels) mA 12 20 ISOFF Shutdown supply current (IIO + IDD) High level input voltage (DIN0-DIN7, BYP, CLKIN, EN, DV0, DV1) Low level input voltage (DIN0-DIN7, BYP, CLKIN, EN, DV0, DV1) High level input current (DIN0-DIN7, BYP, CLKIN, EN, DV0, DV1) Low level input current (DIN0-DIN7, BYP, CLKIN, EN, DV0, DV1) EN = GND, VDD = 2.7V to 3.6V VIO = 1.65V to 1.95V DIN0-DIN7, CLKIN, BYP = GND or VDD VDD = 2.7V to 3.6V, VIO = 1.65V to 1.95V VDD = 2.7V to 3.6V, VIO = 1.65V to 1.95V 0.7xVDD 20 µA VIH 3.6 V VIL 0 0.3xVDD V IIH VIH = 0.7 x VDD ±1 µA IIL VIL = 0.3 x VDD ±1 µA IOZ High impedance output current CLKOUT+,CLKOUT-, VO = 0 or VCC DOUT+, DOUT- ±1 µA 8/23 STSLVDSP27 Electrical characteristics Table 7. Serial switching characteristics (DPLL = "OFF", RT = 100Ω ±1%, CL = 10pF, over recommended operating conditions unless otherwise noted. Typical values are referred to TA = 25°C and VDD = 3.0V, VIO = 1.8V) Parameter Rise time differential output voltage (20% to 80%) (Figure 4.) Fall time differential output voltage (80% to 20%) (Figure 4.) Differential propagation delay time (DIN to DOUT) (Low to High) (Note: 1) (Figure 4.) Differential propagation delay time (DIN to DOUT) (Low to High) (Note: 1) (Figure 4.) Enable delay time (EN to DOUT: tPLZ, tPHZ) (Figure 7.) Disable delay time (EN to DOUT: tPLZ, tPHZ) (Figure 7.) Test Conditions trDIN = 4.9ns (10% to 90%); fDIN = 10MHz, PulseWidthDIN = 50ns trDIN = 4.2ns (90% to 10%); fDIN = 10MHz, PulseWidthDIN = 50ns trDIN = 4.9ns (10% to 90%); tfDIN = 4.2ns (90% to 10%); fDIN = 10MHz, PulseWidthDIN = 50ns Min. 400 Typ. 610 Max. 1000 Unit ps Symbol trVOD tfVOD 400 610 1000 ps tPLHD 1.0 2.1 2.8 ns tPHLD tfDIN = 4.2ns (10% to 90%); fDIN = 10MHz, PulseWidthDIN = 50ns 1.0 2.1 2.8 ns tEN trEN = 2.0ns (10% to 90%); tfEN = 2.0ns (90% to 10%) trEN = 2.0ns (10% to 90%); tfEN = 2.0ns (90% to 10%) 20 µs tDIS 1000 ns fOPR BYP = VDD trDIN0,CLKIN=1ns (10% to 90%); Operating frequency serial tfDIN0,CLKIN=1ns (90% to 10%) mode without DPLL fDIN0,CLKIN = 208MHz PulseWidthDIN0,CLKIN = 2.4ns 1 208 MHz Differential skew between trDIN = 4.9ns (10% to 90%); tSKEW1 signals on each differential tfDIN = 4.2ns (90% to 10%); pair (tPLHD - tPHLD) fDIN = 10MHz, PulseWidthDIN = 50ns Channel to channel skew between any two signals tSKEW2 on each different differential pair (Figure 6.) trDIN = 4.9ns (10% to 90%); tfDIN = 4.2ns (90% to 10%); fDIN = 10MHz, PulseWidthDIN = 50ns 150 ps 200 ps Note: 1 50% VDIN to 50% VDOUT 9/23 Electrical characteristics STSLVDSP27 Table 8. Parallel switching characteristics (DPLL = "ON", RT = 100Ω ±1%, CL = 10pF, over recommended operating conditions unless otherwise noted. Typical values are referred to TA = 25°C and VDD = 3.0V, VIO = 1.8V) Parameter Rise time differential output voltage (20% to 80%) (Figure 4.) Fall time differential output voltage (80% to 20%) (Figure 4.) Test Conditions trDIN = 4.9ns (10% to 90%); fDIN = 10MHz, PulseWidthDIN = 50ns trDIN = 4.2ns (90% to 10%); fDIN = 10MHz, PulseWidthDIN = 50ns trDIN0-DIN7,CLKIN=4.9ns (10% to 90%); tfDIN0-DIN7,CLKIN= 4.2ns (90% to 10%); fDIN0-DIN7,CLKIN=22MHz, PulseWidthDIN = 50ns trDIN0-DIN7,CLKIN=4.2ns (90% to 10%); tfDIN0-DIN7,CLKIN= 4.2ns (90% to 10%); fDIN0-DIN7,CLKIN=22MHz, PulseWidthDIN = 50ns trDIN0-DIN7,CLKIN=4.9ns (10% to 90%); tfDIN0-DIN7,CLKIN= 4.2ns (90% to 10%); fDIN0-DIN7,CLKIN=22MHz, PulseWidthDIN = 50ns trDIN0-DIN7,CLKIN=4.2ns (90% to 10%); tfDIN0-DIN7,CLKIN= 4.2ns (90% to 10%); fDIN0-DIN7,CLKIN=10MHz, PulseWidthDIN = 50ns trDIN0-DIN7,CLKIN=4.9ns (10% to 90%); tfDIN0-DIN7,CLKIN= 4.2ns (90% to 10%); fDIN0-DIN7,CLKIN=10MHz, PulseWidthDIN = 50ns trDIN0-DIN7,CLKIN=4.9ns (10% to 90%); tfDIN0-DIN7,CLKIN= 4.2ns (90% to 10%); fDIN0-DIN7,CLKIN=4 to 22MHz, PulseWidthDIN = 50ns trDIN0-DIN7,CLKIN=4.9ns (10% to 90%); tfDIN0-DIN7,CLKIN=4.2ns (90% to 10%); fDIN0-DIN7,CLKIN=4 to 22MHz, PulseWidthDIN = 50ns trEN = 2.0ns (10% to 90%); tfEN = 2.0ns (90% to 10%) trEN = 2.0ns (10% to 90%); tfEN = 2.0ns (90% to 10%) BYP = GND, fDIN0-DIN7,CLKIN=4 to 27MHz PulseWidthDIN0,CLKIN = 50% trDIN0,CLKIN=3ns (10% to 90%); tfDIN0,CLKIN=3ns (90% to 10%) Min. 400 Typ. 610 Max. 1000 Unit ps Symbol trVOD tfVOD 400 610 1000 ps Differential propagation delay time DIN0 (CLKIN to tPLHDIN0 DOUT) (Low to High) (Note 2) (Figure 10.) Differential propagation delay time DIN0 (CLKIN to tPHLDIN0 DOUT) (High to Low) (Note 2) (Figure 10.) Differential propagation delay time DIN7 (CLKIN to tPLHDIN7 DOUT) (Low to High) (Note 2) (Figure 10.) Differential propagation delay time DIN7 (CLKIN to tPHLDIN7 DOUT) (High to Low) (Note 2) (Figure 10.) Differential propagation delay time (CLKIN to DOUT first positive edge) (Low to High) (Figure 10.) 8 ns 8 ns 53 ns 53 ns tOCD 11 ns Set-up time (DIN0-DIN7, DV to CLKIN) (LH or HL to tSU_CLK positive CLKIN edge) (Figure 11.) Hold time (CLKIN to DIN0DIN7, DV) (positive CLKIN edge to LH or HL DIN,DV transition) (Figure 11.) Enable delay time (EN to DOUT: tPLZ, tPHZ) (Figure 7.) Disable delay time (EN to DOUT: tPLZ, tPHZ) (Figure 7.) Operating frequency parallel mode with DPLL 12 ns tH_CLK 10 ns tEN 20 µs tDIS 1000 ns fOPR 4 27 MHz 10/23 STSLVDSP27 Table 8. Electrical characteristics Parallel switching characteristics (DPLL = "ON", RT = 100Ω ±1%, CL = 10pF, over recommended operating conditions unless otherwise noted. Typical values are referred to TA = 25°C and VDD = 3.0V, VIO = 1.8V) Parameter Test Conditions BYP = GND, fDIN0-DIN7,CLKIN=4 to 27MHz PulseWidthDIN0,CLKIN = 50% trDIN0,CLKIN=3ns (10% to 90%); tfDIN0,CLKIN=3ns (90% to 10%) Min. Typ. Max. Unit Symbol CLKOUT frequency fCLKOUT parallel mode with DPLL 32 216 MHz Differential skew between trDIN = 4.9ns (10% to 90%); tSKEW1 signals on each differential tfDIN = 4.2ns (90% to 10%); fDIN = 10MHz, PulseWidthDIN = 50ns pair (tPLHD - tPHLD) Channel to channel skew between any two signals tSKEW2 on each different differential pair (Figure 6.) trDIN = 4.9ns (10% to 90%); tfDIN = 4.2ns (90% to 10%); fDIN = 10MHz, PulseWidthDIN = 50ns 150 ps 200 ps tDV BYP = GND, fDIN0-DIN7,CLKIN=4 to Data valid before CLKOUT 27MHz PulseWidthDIN0,CLKIN = 50% time (Figure 12.) trDIN0,CLKIN=3ns (10% to 90%); tfDIN0,CLKIN=3ns (90% to 10%) Data valid hold after CLKOUT time (Figure 12.) BYP = GND, fDIN0-DIN7,CLKIN=4 to 27MHz PulseWidthDIN0,CLKIN = 50% trDIN0,CLKIN=3ns (10% to 90%); tfDIN0,CLKIN=3ns (90% to 10%) trEN =2.0ns (10% to 90%) tfEN =2.0ns (90% to 10%) DV0=DV1=VDD; BYP= Gnd; DIN1DIN7=VDD or Gnd; fCLKIN =4 to 27MHz trCLKIN = 4.9ns (10% to 90%); tfCLKIN = 4.2ns (90% to 10%); fCLKIN = 4 to 27MHz, PulseWidthCLKIN =50% trCLKIN = 4.9ns (10% to 90%); tfCLKIN = 4.2ns (90% to 10%); fCLKIN = 4 to 27MHz, PulseWidthCLKIN =50% 1 ns tDH 2 ns tPLLS DPLL settling time (EN to CLKOUT) 50% LH EN to 50% CLKOUT (first negative edge) (Figure 9.) RMS cycle-to-cycle jitter between CLKIN and CLKOUT signals 70 µs 100 ps 600 JCY-CY Peak cycle-to-cycle jitter between CLKIN and CLKOUT signals Note: 1 2 3 50% VDIN to 50% VDOUT 50% CLKIN (positive edge) to 50% VDOUT (DIN0 will be referred to CLKOUT first positive edge; DIN7 will be referred to CLKOUT eighth positive edge) Power down can be guaranteed when VIO =1.8V, EN = GND, if low impedance < 1MΩ vs GND is guaranteed on VDD pin 11/23 Electrical characteristics STSLVDSP27 Table 9. Capacitive characteristics Test condition Value TA = 25°C Min. VIO = 1.65V to 1.95V, VI = GND or VDD Typ. 4 Max. pF Unit Symbol Parameter VDD (V) 2.7 to 3.6 CIN Input capacitance (DIN0-DIN7, CLKIN, EN, BYP, DV0, DV1) 12/23 STSLVDSP27 Test circuits and timing diagram 5 Figure 3. Test circuits and timing diagram Voltage and input current definition VCM = (VD+ + VD-)/2 Note: RT = 100 Ω ±1% Figure 4. Test circuit, timing and voltage definitions for differential output signal Note: RT = 100 Ω ±1%; CL = 10pF; trDIN = 4.9ns; tfDIN = 4.2ns; fDIN = 10MHz; PulseWidthDIN = 50ns. 13/23 Test circuits and timing diagram STSLVDSP27 Figure 5. Test circuit and definitions for the driver common mode output voltage Note: RT = 100 Ω ±1%; CL = 10pF; trDIN = 4.9ns; tfDIN = 4.2ns; fDIN = 10MHz; PulseWidthDIN = 50ns. Figure 6. tSKEW2 Note: RT = 100 Ω ±1%; CL = 10pF; trDIN = 4.9ns; tfDIN = 4.2ns; fDIN = 10MHz; PulseWidthDIN = 50ns 14/23 STSLVDSP27 Test circuits and timing diagram Figure 7. tEN (tPZL, tPZH); tDIS (tPHZ, tPLZ) Note: RT = 100 Ω ±1%; CL = 10pF; trDIN = 2.0ns; tfDIN = 2.0ns; fEN = 1MHz; PulseWidthDIN = 500ns RO: Driver output impedance Figure 8. Note: RT = 100 Ω ±1%; CL = 10pF ΔVX+ = VD+(VCM=1.0V) - VD+(VCM=0.8V); ΔVX- = VD-(VCM=1.0V) - VD-(VCM=0.8V); R0+ = (RT/2 x ΔVX+)/(200mV - ΔVX+); R0- = (RT/2 x ΔVX-)/(200mV - ΔVX-) 15/23 Test circuits and timing diagram STSLVDSP27 Figure 9. tPLLS Note: During tPLLS test DV0=DV1=VDD 16/23 STSLVDSP27 Tclkin Tocd CLKIN DIN[0..7] P1 P2 PN-1 PN PN+1 PN+1 data does not appear in the output stream Figure 10. General timing diagram (parallel mode) DV[0..1] CLKOUT DOUT P1: D0 P 1: D1 P1: D2 P1: D3 P 1: D4 P1: D5 P1: D6 P1: D7 P2: D0 P2: D1 P2: D2 P2: D3 PN-1: D4 PN-1: D5 PN-1: D6 PN-1: D7 PN: D0 PN: D1 PN: D2 PN: D3 PN: D4 PN: D5 PN: D6 PN: D7 0 < Tocd < Tclkin Test circuits and timing diagram 17/23 Test circuits and timing diagram STSLVDSP27 Figure 11. tCLKIN Note: tCLKIN Figure 12. tCLKOUT Note: tCLKOUT 18/23 STSLVDSP27 Package mechanical data 6 Package mechanical data In order to meet environmental requirements, ST offers these devices in ECOPACK® packages. These packages have a Lead-free second level interconnect. The category of second Level Interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com. 19/23 Package mechanical data STSLVDSP27 Flip-Chip20 Mechanical Data mm. Dim. Min. A A1 A2 b D D1 E E1 e SE 1.93 0.25 2.41 0.81 0.15 Typ. 0.89 0.24 0.65 0.30 2.46 2.00 1.98 1.5 0.50 0.25 2.03 76.0 0.35 2.51 9 .8 94.9 Max. 1.00 0.35 Min. 31.9 5.9 Typ. 35.0 9.4 25.6 11.8 96.9 78.7 78.0 59.1 19.7 9.8 79.9 13.8 98.8 Max. 39.4 13.8 mils. 7487339-D 20/23 STSLVDSP27 Package mechanical data Tape & Reel Flip-Chip20 Mechanical Data mm. Dim. Min. A C D N T Ao Bo Ko Po P 2.13 2.62 1.05 3.9 3.9 2.23 2.72 1.15 12.8 20.2 60 14.4 2.33 2.82 1.25 4.1 4.1 0.084 0.103 0.041 0.153 0.153 0.088 0.107 0.045 Typ. Max. 180 13.2 0.504 0.795 2.362 0.567 0.092 0.111 0.049 0.161 0.161 Min. Typ. Max. 7.086 0.519 inch. 21/23 Revision history STSLVDSP27 7 Table 10. Date Revision history Revision history Revision 1 Initial release. Changes 01-Jun-2007 22/23 STSLVDSP27 Please Read Carefully: Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale. Purchasers are solely responsible for the choice, selection and use of the ST products and services described herein, and ST assumes no liability whatsoever relating to the choice, selection or use of the ST products and services described herein. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. If any part of this document refers to any third party products or services it shall not be deemed a license grant by ST for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoever of such third party products or services or any intellectual property contained therein. UNLESS OTHERWISE SET FORTH IN ST’S TERMS AND CONDITIONS OF SALE ST DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY WITH RESPECT TO THE USE AND/OR SALE OF ST PRODUCTS INCLUDING WITHOUT LIMITATION IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE (AND THEIR EQUIVALENTS UNDER THE LAWS OF ANY JURISDICTION), OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. UNLESS EXPRESSLY APPROVED IN WRITING BY AN AUTHORIZED ST REPRESENTATIVE, ST PRODUCTS ARE NOT RECOMMENDED, AUTHORIZED OR WARRANTED FOR USE IN MILITARY, AIR CRAFT, SPACE, LIFE SAVING, OR LIFE SUSTAINING APPLICATIONS, NOR IN PRODUCTS OR SYSTEMS WHERE FAILURE OR MALFUNCTION MAY RESULT IN PERSONAL INJURY, DEATH, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE. ST PRODUCTS WHICH ARE NOT SPECIFIED AS "AUTOMOTIVE GRADE" MAY ONLY BE USED IN AUTOMOTIVE APPLICATIONS AT USER’S OWN RISK. Resale of ST products with provisions different from the statements and/or technical features set forth in this document shall immediately void any warranty granted by ST for the ST product or service described herein and shall not create or extend in any manner whatsoever, any liability of ST. ST and the ST logo are trademarks or registered trademarks of ST in various countries. Information in this document supersedes and replaces all information previously supplied. The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners. © 2007 STMicroelectronics - All rights reserved STMicroelectronics group of companies Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America www.st.com 23/23
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