STSPIN32F0601TR

STSPIN32F0601, STSPIN32F0602 Datasheet Advanced 600 V three-phase BLDC controller with embedded STM32 MCU Features • • • • • • Product status link STSPIN32F0601 STSPIN32F0601Q STSPIN32F0602 STSPIN32F0602Q • • • • • • • • • • Product label Three-phase gate drivers – High voltage rail up to 600 V – dV/dt transient immunity ±50 V/ns – Gate driving voltage range from 9V to 20V Driver current capability: – STSPIN32F0601/Q: 200/350 mA source/sink current – STSPIN32F0602/Q: 1/0.85 A source/sink current 32-bit ARM® Cortex®-M0 core: – Up to 48 MHz clock frequency – 4-kByte SRAM with HW parity – 32-kByte Flash memory with option bytes – used for write/readout protection 21 general-purpose I/O ports (GPIO) 6 general-purpose timers 12-bit ADC converter (up to 10 channels) I2C, USART and SPI interfaces Matched propagation delay for all channels Integrated bootstrap diodes Comparator for fast over current protection UVLO, Interlocking and deadtime functions Smart shutdown (smartSD) function Standby mode for low power consumption On-chip debug support via SWD Extended temperature range: -40 to +125 °C Package: – TQFP 10x10 64L pitch 0.5 Creepage 1.2 mm – QFN 10x10 72L pitch 0.5 Creepage 1.8 mm Applications • • • • • • Home and Industrial refrigerators compressors Industrial drives, pumps, fans Air conditioning compressors & fans Corded power tools, garden tools Home appliances Industrial automation Description The STSPIN32F060x system-in-package is an extremely integrated solution for driving three-phase applications, helping designers to reduce PCB area and overall bill-of-material. DS12981 - Rev 5 - February 2021 For further information contact your local STMicroelectronics sales office. www.st.com STSPIN32F0601, STSPIN32F0602 It embeds an STM32F031x6x7 featuring an ARM® 32-bit Cortex®-M0 CPU and a 600 V triple half-bridge gate driver, able to drive N-channel power MOSFETs or IGBTs. A comparator featuring advanced smartSD function is integrated, ensuring fast and effective protection against overload and overcurrent. The high-voltage bootstrap diodes are also integrated, as well as anti crossconduction, deadtime and UVLO protection on both the lower and upper driving sections, which prevents the power switches from operating in low efficiency or dangerous conditions. Matched delays between low and high-side sections guarantee no cycle distortion. The integrated MCU allows performing FOC, 6-step sensorless and other advanced driving algorithms including the speed control loop. DS12981 - Rev 5 page 2/32 STSPIN32F0601, STSPIN32F0602 Block diagram 1 Block diagram Figure 1. STSPIN32F060x SiP block diagram VCC PA12 PA13 VSS PA14 PA15 PB3 PB4 PB5 PB6 PB7 BOOT0 PB8 VDD VCC UVLO DETECTION UVLO VCC EN D1 BOOT3 HVG3 OUT3 UV & Level Shifter Floating structure +5V VCC D2 BOOT2 HVG2 HIN3 UV & Level Shifter +5V HIN2 PC13 PC14 PC15 PF0 PF1 NRST VSSA BYPASSREG1 VDDA PA0 PA1 PA2 PA3 STM32F031 VDD VSS BYPASSREG2 VSSA2 PB11 PB10 PB2 NPOR VDD PB1 PB0 PA7 PA6 PA5 PA4 VDDA PA0 PA1 PA2 PA3 PA14 PA15 PB3 PB4 PB5 PB6 PB7 BOOT0 PB8 PB9 VSS VDD18 VDD VBAT reserved PC13 PC14 PC15 PF0 PF1 NRST VSSA VCC HlN1 PF7 PF6 PA13 PA12 PA11 PA10 PA9 PA8 PB15 PB14 PB13 PB12 VDD18 OUT2 Floating structure +5V D3 BOOT1 HVG1 UV & Level Shifter +5V LOGIC SHOOT THROUGH PREVENTION LIN3 Floating structure VCC OUT1 LVG3 +5V DEADTIME VCC LIN2 +5V LVG2 LlN1 VCC LVG1 FAULT IOD SMART SD OD PGND +5V CIN + + VREF SGND CIN OD VSS VDD PB1 PB0 PA7 PA6 PA5 PA4 DS12981 - Rev 5 UVLO page 3/32 STSPIN32F0601, STSPIN32F0602 Pin description and connection diagram 2 Pin description and connection diagram Figure 2. STSPIN32F060x pin connection (TQFP top view) 49 64 NC RES5 VCC RES1 RES2 RES3 PA12 PA13 PA14 PA15 PB3 PB4 PB5 PB6 PB7 PB8 BOOT0 1 VSS HVG3 VDD OUT3 PC13 NC PC14 NC NC PC15 BOOT2 PF0 HVG2 PF1 EPAD NRST OUT2 VSSA NC VDDA NC PA0 NC BOOT1 PA3 HVG1 PA4 OUT1 33 NC LVG3 LVG2 LVG1 CIN GND OD VSS VDD PB1 PB0 PA7 PA6 PA5 17 RES4 NC PA2 PGND PA1 16 48 BOOT3 32 Figure 3. STSPIN32F060x pin connection (QFN top view) RES5 VCC RES1 RES2 RES3 PA12 PA13 PA14 PA15 PB3 PB4 PB5 PB6 PB7 BOOT0 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 RES6 1 PB8 2 53 BOOT3 VSS 3 52 HVG3 VDD 4 51 OUT3 PC13 5 PC14 6 PC15 7 PF0 8 PF1 9 47 BOOT2 EPAD NRST10 VSSA11 46 HVG2 45 OUT2 44 N.C. VDDA12 PA0 13 PA1 14 PA2 15 40 BOOT1 PA3 16 39 HVG1 PA4 17 38 OUT1 RES7 18 LVG3 RES4 LVG2 LVG1 GND OD CIN VSS PB1 VDD PA7 PB0 PA6 PA5 DS12981 - Rev 5 PGND 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 page 4/32 STSPIN32F0601, STSPIN32F0602 Pin description and connection diagram Table 1. Legend/abbreviations used in the pin description table Name Abbreviation Unless otherwise specified in brackets below the pin name, the pin function during and after reset is the same as the actual pin name Pin name AO Pin type I/O structure P Gate Driver Supply\GND pin S Supply pin I Input-only pin I/O Input / output pin FT 5 V-tolerant I/O FTf 5 V-tolerant I/O, FM+ capable TTa 3.3 V-tolerant I/O directly connected to ADC TC Standard 3.3V I/O B RST Notes Gate Driver Analog Output Dedicated BOOT0 pin Bidirectional reset pin with embedded weak pull-up resistor Unless otherwise specified by a note, all I/Os are set as floating inputs during and after reset Pin functions Alternate Functions Functions selected through GPIOx_AFR registers Additional functions Functions directly selected/enabled through peripheral registers Table 2. STSPIN32F060x MCU-Driver internal connections MCU pad Note: DS12981 - Rev 5 Type controller pad Function PB12 I/O - FT FAULT Gate Driver Fault output PB13 I/O - FT LIN1 Gate Driver Low Side input driver 1 PB14 I/O - FT LIN2 Gate Driver Low Side input driver 2 PB15 I/O - FT LIN3 Gate Driver Low Side input driver 3 PA8 I/O - FT HIN1 Gate Driver High Side input driver 1 PA9 I/O - FTf HIN2 Gate Driver High Side input driver 2 PA10 I/O - FTf HIN3 Gate Driver High Side input driver 3 PA11 I/O - FT EN Gate Driver shut down input Each unused GPIO inside the SiP should be configured in OUTPUT mode low level after startup by software page 5/32 STSPIN32F0601, STSPIN32F0602 Pin description table 3 Pin description table Table 3. Pin description TQFP N. DS12981 - Rev 5 QFN N. Name Type Function - 1 RES6 Reserved Pin must be left floating 1 2 PB8 I/O - FTf MCU PB8 2 3 VSS Supply MCU digital ground 3 4 VDD Supply MCU digital power supply 4 5 PC13 I/O - TC MCU PC13 5 6 PC14 I/O - TC MCU PC14 6 7 PC15 I/O - TC MCU PC15 7 8 PF0 I/O - FT MCU PF0 8 9 PF1 I/O - FT MCU PF1 9 10 NRST I/O - RST MCU Reset pin 10 11 VSSA Supply MCU analog ground 11 12 VDDA Supply MCU analog power supply 12 13 PA0 I/O - TTa MCU PA0 13 14 PA1 I/O - TTa MCU PA1 14 15 PA2 I/O - TTa MCU PA2 15 16 PA3 I/O - TTa MCU PA3 16 17 PA4 I/O - TTa MCU PA4 - 18 RES7 Reserved Pin must be left floating 17 19 PA5 I/O - TTa MCU PA5 18 20 PA6 I/O - TTa MCU PA6 19 21 PA7 I/O - TTa MCU PA7 20 22 PB0 I/O - TTa MCU PB0 21 23 PB1 I/O - TTa MCU PB1 22 24 VDD Supply MCU digital power supply 23 25 VSS Supply MCU digital ground 24 26 OD Analog OD Output Open Drain comparator output 25 27 CIN Analog Input Comparator positive input 26 28 SGND Power Driver signal ground 27 29 PGND Power Driver power ground 28 30 LVG1(1) Analog Out Phase 1 low-side driver output 29 31 LVG2(1) Analog Out Phase 2 low-side driver output 30 32 LVG3(1) Analog Out Phase 3 low-side driver output 31 33 RES4 Reserved Pin must be left floating 33 38 OUT1 Power Phase 1 high-side (floating) common voltage 34 39 HVG1(1) Analog Out Phase 1 high-side driver output 35 40 BOOT1 Power Phase 1 bootstrap supply voltage page 6/32 STSPIN32F0601, STSPIN32F0602 Pin description table TQFP N. QFN N. Name Type Function 40 45 OUT2 Power Phase 2 high-side (floating) common voltage 41 46 HVG2(1) Analog Out Phase 2 high-side driver output 42 47 BOOT2 Power Phase 2 bootstrap supply voltage 46 51 OUT3 Power Phase 3 high-side (floating) common voltage 47 52 HVG3(1) Analog Out Phase 3 high-side driver output 48 53 BOOT3 Power Phase 3 bootstrap supply voltage 50 58 RES5 Reserved Pin must be left floating 51 59 VCC Power Driver low side and logic supply voltage 52 60 RES1 Reserved Pin must be left floating 53 61 RES2 Reserved Pin must be left floating 54 62 RES3 Reserved Pin must be left floating 55 63 PA12 I/O - FT MCU PA12 56 64 PA13 I/O - FT MCU PA13/SWDIO (System debug data) 57 65 PA14 I/O - FT MCU PA14/SWDCLK (System debug clock) 58 66 PA15 I/O - FT MCU PA15 59 67 PB3 I/O - FT MCU PB3 60 68 PB4 I/O - FT MCU PB4 61 69 PB5 I/O - FT MCU PB5 62 70 PB6 I/O - FTf MCU PB6 63 71 PB7 I/O - FTf MCU PB7 64 72 BOOT0 I-B Boot memory selection 32, 36, 37, 38, 39, 43, 44, 45, 49 44 NC - - EPAD Not Connected Power Exposed pad, internally connected to SGND 1. The circuit guarantees less than 1 V on the LVG and HVG pins (at Isink = 10 mA), with VCC > 3 V. This allows omitting the “bleeder” resistor connected between the gate and the source of the external MOSFETs normally used to hold the pin low. When the EN is set low, gate driver outputs are forced low and assure low impedance. DS12981 - Rev 5 page 7/32 STSPIN32F0601, STSPIN32F0602 Electrical data 4 Electrical data 4.1 Absolute maximum ratings (Each voltage referred to SGND unless otherwise specified) Table 4. Absolute maximum ratings Symbol Parameter Test Condition Min Max Unit VCC Power supply voltage -0.3 21 V VPGND Low-side driver ground VCC – 21 VCC + 0.3 V (1) Low-side driver ground -21 21 V VOUT Output voltage VBOOT – 21 VBOOT + 0.3 V VBOOT Bootstrap voltage -0.3 620 V VHVG High side gate output voltage VOUT – 0.3 VBOOT + 0.3 V VLVG Low side gate output voltage VPGND – 0.3 VCC + 0.3 V VCIN Comparator input voltage -0.3 20 V VOD Open-drain voltage (OD, FAULT) -0.3 21 V dVOUT/dt Common mode transient Immunity 50 V/ns VPS VIO MCU logic input voltage TTa type(2) type(2) -0.3 4 V (3) Logic input voltage FT, FTf -0.3 VDD + 4 IIO MCU I/O output current (2) -25 25 mA ΣIIO MCU I/O total output current (2) -80 80 mA VDD MCU digital supply voltage (2) -0.3 4 V VDDA MCU analog supply voltage (2) -0.3 4 V Tstg Storage temperature -50 150 °C TJ Junction temperature -40 150 °C PTOT Total power dissipation 4.5 W ESD Human Body Model TQFP 10x10 64L package 2(4) QFN 10x10 72L package 2 V kV 1. VPS = VPGND - VSGND 2. For details see Table 15 and 16 in the STM32F031x6x7 datasheet www.st.com 3. Valid only if the internal pull-up/pull-down resistors are disabled. If the internal pull-up or pull-down resistor is enabled, the maximum limit is 4 V. 4. Pins 33 to 48 have HBM ESD rating 1C conforming to ANSI/ESDA/JEDEC JS-001-2014. DS12981 - Rev 5 page 8/32 STSPIN32F0601, STSPIN32F0602 Thermal data 4.2 Thermal data Table 5. Thermal data Symbol Rth(JA) Parameter Value Thermal resistance junction to ambient(1) TQFP 10x10 64L package 27.6 Thermal resistance junction to ambient (1) QFN 10x10 72L package 22.4 Unit °C/W 1. JEDEC 2s2p PCB in still air. 4.3 Recommended operating conditions Table 6. Recommended operating conditions Symbol Parameter Test Condition Min Typ Max Unit Power supply voltage (VCCthON)MAX 20 V Low-side driver supply voltage 4 20 V VPS (2) Low-side driver ground -5 5 V VBO (3) Floating supply voltage (VBOthON)MAX 20 V VCIN Comparator input voltage 0 15 V VOUT DC Output voltage -10(4) 580 V 800 kHz 3.6 V VDD 3.6 V VDD 3.6 V -40 125 °C VCC (1) VLS FSW VDD VDDA TJ Maximum switching frequency (5) Standard MCU operating voltage MCU analog operating voltage (ADC not used) MCU analog operating voltage (ADC used) 3.0 Must have a potential equal to or higher than VDD Operating junction temperature 3.3 1. VLS = VCC - VPGND 2. VPS = VPGND - VSGND 3. VBO = VBOOT - VOUT 4. LVG off. VCC = 9 V. Logic is operational if VBOOT > 5 V 5. Actual maximum FSW depends on power dissipation. DS12981 - Rev 5 page 9/32 STSPIN32F0601, STSPIN32F0602 Electrical characteristics 5 Electrical characteristics (VCC=15 V; VDD=3.3 V; PGND = SGND; TJ = +25 °C, unless otherwise specified) Table 7. Electrical characteristics Symbol Parameter Test condition Min Typ Max Unit 430 744 µA 950 1450 µA Power supply and standby mode IQCCU VCC under-voltage quiescent supply current IQCC VCC quiescent supply current VCC = 7 V; EN = 5 V; CIN = SGND EN = 5 V; CIN = SGND LVG & HVG: OFF VCCthON VCC UVLO turn-on threshold 8 8.5 9 V VCCthOFF VCC UVLO turn-off threshold 7.5 8 8.5 V VCChys VCC UVLO threshold hysteresis 0.4 0.5 0.6 V VDD = 3.6 V VDD current consumption IDD(1) (Supply current in Run mode, code executing from Flash memory) HSE bypass, PLL off 0.8 fHCLK = 1 MHz mA VDD = 3.6 V HSI clock, PLL on 18.9 fHCLK = 48 MHz VDD = 3.6 V HSE bypass, PLL off IDDA(1) VDDA current consumption 2.0 fHCLK = 1 MHz µA VDD = 3.6 V HSI clock, PLL on 220 fHCLK = 48 MHz VPOR VDD Power on reset Rising edge threshold VPDR VDD Power down reset threshold VPDRhyst VDD PDR hysteresis Falling edge 1.84(2) 1.92 2.00 V 1.80 1.88 1.96(2) V 40 mV High-side floating section supply(3) IQBOU VBO under-voltage quiescent supply current IQBO VBO quiescent supply current VCC = VBO = 6.5 V; EN = 5 V; CIN = SGND 25 62 µA 84 150 µA 8 8.5 V VBO = 15 V EN = 5 V; CIN = SGND LVG OFF; HVG = ON VBOthON DS12981 - Rev 5 VBO UVLO turn on threshold 7.5 page 10/32 STSPIN32F0601, STSPIN32F0602 Electrical characteristics Symbol Parameter Test condition Min Typ Max Unit VBOthOff VBO UVLO turn-off threshold 7 7.5 8 V VBOhys VBO UVLO threshold hysteresis 0.4 0.5 0.6 V ILK High voltage leakage current 15 µA RDboot Bootstrap diode on resistance BOOT = HVG = OUT = 620 V TJ = 25 °C LVG ON 215 240 LVG OFF 215 250 200 300 mA 350 mA 1.33 A 1.48 A 430 mA 500 mA 1.02 A 1.15 A 46 Ω 56 Ω 7.6 Ω 10.3 Ω 21 Ω 27 Ω 8 Ω 11.2 Ω Ω Output driving buffers Source peak current ISO STSPIN32F0601/Q STSPIN32F0602/Q TJ = 25 °C 160 Full temperature range(3) 130 TJ = 25 °C 0.88 Full temperature range(3) 0.72 TJ = 25 °C 230 Full temperature range(3) 200 TJ = 25 °C 0.71 1.0 Sink peak current ISI STSPIN32F0601/Q STSPIN32F0602/Q Source RDSon RDSonON STSPIN32F0601/Q STSPIN32F0602/Q Sink RDSon RDSonOFF STSPIN32F0601/Q STSPIN32F0602/Q Full temperature range(3) 350 0.85 0.51 I = 10mA TJ = 25 °C Full temperature 24 range(3) TJ = 25 °C 20 5 Full temperature range(3) 35 6.4 4.2 I = 10mA TJ = 25 °C 11 Full temperature range(3) 8 TJ = 25 °C Full temperature 5.5 range(3) 4.5 16 6.7 Logic Inputs Vil Low level logic threshold voltage 0.3·VDD+ TTa type (4) 0.07 0.475 ·VDD –0.2 FT, FTf type (4) TTa type (4) Vih High level logic threshold voltage FT, FTf type (4) Vhyst DS12981 - Rev 5 Schmitt trigger hysteresis 0.45 ·VDDIOx + 0.398 0.5 ·VDDIOx +0.2 V V V V TTa type (4) 200 mV FT, FTf type (4) 100 mV page 11/32 STSPIN32F0601, STSPIN32F0602 Electrical characteristics Symbol Parameter Test condition Min Typ TC, FT and FTf I/O TTa in digital mode Max Unit ± 0.1 VSS ≤ VIN ≤ VDDIOx TTa in digital mode Ilkg Input leakage current 1 VDDIOx ≤ VIN ≤ VDDA µA TTa in analog mode ± 0.1 VSS ≤ VIN ≤ VDDA FT and FTf I/O 10 VDDIOx ≤ VIN ≤ 5 V VSSDh SmartSD restart threshold VSSDl SmartSD unlatch threshold 3.5 4 4.3 V 0.56 0.75 V 510 mV Sense Comparator and FAULT VREF Internal voltage reference 410 460 CINhyst Comparator input hysteresis 40 70 CINPD Comparator input pull-down current 7 10 13 µA IOD OD internal current source 2.5 5 7.5 µA RON_OD OD On resistance IOD = 16 mA 19 25 36 W ISAT_OD OD saturation current VOD = 5 V VFLOAT_OD OD floating voltage level OD connected only to an external capacitance 4.4 4.8 5.2 V IOL_OD OD low level sink current VOD = 400 mV 11 16 21 mA RON_F FAULT On resistance IFAULT = 8 mA 50 100 Ω IOL_F FAULT low level sink VFAULT = 400mV current 8 12 mA tOD Comparator propagation delay 350 500 ns 50% CIN to 90% FAULT 350 500 ns 0 to 3.3 V voltage step on CIN 50% CIN to 90% LVG/HVG 360 510 ns 200 300 400 ns 4 7.7 10.3 V/µs VCIN = 1 V mV 95 4 mA Rpu = 100 kΩ to 5 V; 0 to 3.3 V voltage step on CIN 50% CIN to 90% OD tCIN-F Comparator triggering to FAULT tCINoff Comparator triggering to high/low side driver propagation delay tFCIN Comparator input filter time SR Slew rate 0 to 3.3 V voltage step on CIN; CL = 1 nF; Rpu = 1 kΩ to 5 V; DS12981 - Rev 5 90% to 10% OD page 12/32 STSPIN32F0601, STSPIN32F0602 Electrical characteristics Symbol Parameter Test condition Min Typ Max Unit Driver dynamic characteristics ton High/Low-side driver turn-on propagation delay OUT = 0 V 45 85 120 ns toff High/Low-side driver BOOT = VCC turn-off propagation CL = 1 nF delay 45 85 120 ns Enable to high/low side driver propagation delay Vin = 0 to 3.3 Vsee Figure 4 tEN 245 345 520 ns Rise time CL= 1 nF tr STSPIN32F0601/Q 120 STSPIN32F0602/Q 19 Fall time tf MT ns CL= 1 nF STSPIN32F0601/Q 50 STSPIN32F0602/Q 17 Delay matching high/low side turn-on/off ns 0 30 ns 300 400 ns 0 50 ns (6) DT Deadtime MDT (7) Matching deadtime CL= 1 nF CL= 1 nF 200 1. The current consumption depends on the firmware loaded in the microcontroller. See STM32F031x6x7 datasheet.www.st.com 2. Data based on characterization results, not tested in production. 3. Values provided by characterization, not tested 4. Data based on design simulation only. Not tested in production. 5. Comparator is disabled when VCC is in UVLO condition. 6. MT = max. (|ton(LVG) - toff(LVG)|, |ton(HVG) - toff(HVG)|, |toff(LVG) - ton(HVG)|, |toff(HVG) - ton(LVG)|) 7. MDT = | DTLH - DTHL |, refer to Figure 4. DS12981 - Rev 5 page 13/32 STSPIN32F0601, STSPIN32F0602 Electrical characteristics Figure 4. Propagation delay timing definition LIN 50% 50% 50% t > DT t > DT HIN 50% 50% tr tf 90% LVG 90% 10% 10% t on tr t off tf 90% HVG 90% 10% 10% t on t off EN 50% 50% 90% LVG/HVG 10% t EN t EN t EN Figure 5. Deadtime timing definitions t > DT LIN 50% HIN 50% 50% 50% tr tf 90% HVG 90% 10% 10% t off tf 90% LVG 10% t off DS12981 - Rev 5 DTLH 10% DTHL page 14/32 STSPIN32F0601, STSPIN32F0602 Electrical characteristics Figure 6. Deadtime and interlocking waveforms definition LIN INTERLOCKING CONTROL SIGNAL EDGES OVERLAPPED FOR MORE THAN DEAD TIME: INTERLOCKING INTERLOCKING HIN LVG DTHL DTLH HVG gate driver outputs OFF (HALF-BRIDGE TRI-STATE) gate driver outputs OFF (HALF-BRIDGE TRI-STATE) OCK ING LVG INT ERL ERL OCK HIN INT CONTROL SIGNAL EDGES OVERLAPPED: INTERLOCKING + DEAD TIME ING LIN DTHL DTLH HVG gate driver outputs OFF (HALF-BRIDGE TRI-STATE) gate driver outputs OFF (HALF-BRIDGE TRI-STATE) LIN CONTROL SIGNALS EDGES SYNCHRONOUS (*): DEAD TIME HIN LVG DTLH DTHL HVG gate driver outputs OFF (HALF-BRIDGE TRI-STATE) gate driver outputs OFF (HALF-BRIDGE TRI-STATE) LIN CONTROL SIGNALS EDGES NOT OVERLAPPED, BUT INSIDE THE DEAD TIME: DEAD TIME HIN LVG DTLH DTHL HVG gate driver outputs OFF (HALF-BRIDGE TRI-STATE) gate driver outputs OFF (HALF-BRIDGE TRI-STATE) LIN CONTROL SIGNALS EDGES NOT OVERLAPPED, OUTSIDE THE DEAD TIME: DIRECT DRIVING HIN LVG DTLH DTHL HVG gate driver outputs OFF (HALF-BRIDGE TRI-STATE) DS12981 - Rev 5 gate driver outputs OFF (HALF-BRIDGE TRI-STATE) page 15/32 STSPIN32F0601, STSPIN32F0602 Device description 6 Device description The STSPIN32F060x is a system-in-package providing an integrated solution suitable for driving high-voltage 3-phase applications. 6.1 Gate driver The STSPIN32F060x integrates a triple half-bridge gate driver able to drive N-channel power MOSFETs or IGBTs. The high-side section is supplied by a bootstrapped voltage technique with integrated bootstrap diode. All the inputs lines are connected to a pull-down resistor with typical value of 60 kΩ. The high- and low-side outputs of same half-bridge cannot be simultaneously driven high thanks to an integrated interlocking function. 6.1.1 Inputs and outputs The device is controlled through the following logic inputs: • EN: enable input, active high; • LIN: low-side driver inputs, active low; • HIN: high-side driver inputs, active low. Table 8. Inputs truth table (applicable when device is not in UVLO or SmartSD protection) Input pins Interlocking Note: Output pins EN LIN HIN LVG HVG L X X Low Low H H H Low Low H L H HIGH Low H H L Low HIGH H L L Low Low X : Don’t care The FAULT and OD pins are open-drain outputs. The FAULT signal is set low in case VCC UVLO is detected, or in case the SmartShutDown comparator triggers an event. It is only used to signal a UVLO or SmartSD activation to external circuits, and its state does not affect the behavior of other functions or circuits inside the driver. The OD behavior is explained in Section 6.1.5 . 6.1.2 Deadtime The deadtime feature, in companion with the interlocking feature, guarantees that driver outputs of the same channel are not high simultaneously and at least a DT time passes between the turn-off of one driver's output and the turn-on of the companion output of the same channel. If a deadtime longer than the internal DT is applied to LIN and HIN inputs by the external controller, the internal DT is ignored and the outputs follow the deadtime determined by the inputs. Refer to Figure 4 for the deadtime and interlocking waveforms. 6.1.3 VCC UVLO protection Undervoltage protection is available on VCC and BOOT supply pins. In order to avoid intermittent operation, a hysteresis sets the turn-off threshold with respect to the turn-on threshold. When VCC voltage goes below the VCCthOFF threshold all the outputs are switched off, both LVG and HVG. When VCC voltage reaches the VCCthON threshold the driver returns to normal operation and sets the LVG outputs according to actual input pins status; HVG is also set according to input pin status if the corresponding VBO section is not in UVLO condition. The FAULT output is kept low when VCC is in UVLO condition. The following figures show some examples of typical operation conditions. DS12981 - Rev 5 page 16/32 STSPIN32F0601, STSPIN32F0602 Gate driver Figure 7. VCC power ON and UVLO, LVG timing VCCthON VCCthOFF VCC 0V FAULT 0V UVLO VCC LIN 0V LVG 0V Figure 8. VCC power ON and UVLO, HVG timing VCCthON VCCthOFF VCC 0V FAULT UVLO VCC HIN 0V 0V VBOthON VBOthOFF VBO 0V HVG-OUT 6.1.4 VBO UVLO protection Dedicated undervoltage protection is available on each bootstrap section between BOOTx and OUTx supply pins. In order to avoid intermittent operation, a hysteresis sets the turn-off threshold with respect to the turn-on threshold. When VBO voltage goes below the VBOthOFF threshold, the HVG output of the corresponding bootstrap section is switched off. When VBO voltage reaches the VBOthON threshold the device returns to normal operation and the output remains off up to the next input pins transition that requests HVG to turn on. DS12981 - Rev 5 page 17/32 STSPIN32F0601, STSPIN32F0602 Gate driver Figure 9. VBO Power-ON and UVLO timing VCCthON VCCthOFF VCC 0V FAULT 0V HIN 0V VBOthON VBOthOFF VBO HVG-OUT 6.1.5 0V 0V Comparator and Smart shutdown The STSPIN32F060x integrates a comparator committed to the fault protection function, thanks to the SmartShutDown (SmartSD) circuit. The SmartSD architecture allows immediate turn-off of the gate driver outputs in the case of overload or overcurrent condition, by minimizing the propagation delay between the fault detection event and the actual output switch-off. In fact, the time delay between the fault detection and the output turn-off is not dependent on the value of the external components connected to the OD pin, which are only used to set the duration of disable time after the fault. This provides the possibility to increase the duration of the output disable time after the fault event up to very large values without increasing the delay time of the protection. The duration of the disable time is determined by the values of the external capacitor COD and of the optional pull-up resistor connected to the OD pin. The comparator has an internal voltage reference VREF connected to the inverting input, while the non-inverting input is available on the CIN pin. The comparator's CIN input can be connected to an external shunt resistor in order to implement a fast and simple overcurrent protection function. The output signal of the comparator is filtered from glitches shorter than tFCIN and then fed to the SmartSD logic. If the impulse on the CIN pin is higher than VREF and wider than tFCIN, the SmartSD logic is triggered and immediately sets all of the driver outputs to low-level (OFF). At the same time, FAULT is forced low to signal the event (for example to a MCU input) and OD starts to discharge the external COD capacitor used to set the duration of the output disable time of the fault event. The FAULT pin is released and driver outputs restart following the input pins as soon as the output disable time expires. The overall disable time is composed of two phases: • The OD unlatch time (t1 in Figure 10), which is the time required to discharge the COD capacitor down to the VSSDl threshold. The discharge starts as soon as the SSD comparator is triggered. • DS12981 - Rev 5 The OD Restart time (t2 in Figure 10), which is the time required to recharge the COD capacitor up to the VSSDh threshold. The recharge of COD starts when the OD internal MOSFET is turned-off, which happens when the fault condition has been removed (CIN < VREF - CINhyst) and the voltage on OD reaches the VSSDl threshold. This time normally covers most of the overall output disable time. page 18/32 STSPIN32F0601, STSPIN32F0602 Gate driver If no external pull-up is connected to OD, the external COD capacitor is discharged with a time constant defined by COD and the internal MOSFET's characteristic (Equation 1), and the Restart time is determined by the internal current source IOD and by COD (Equation 2 ). Equation 1 (1) V t1 ≅ RON_OD  ∙ COD ∙ ln V OD   SSDl Equation 2 (2) C ∙  V V V t2 ≅ OD I SSDh ∙ ln V SSDl − VOD OD SSDh − OD Where VOD = VFLOAT_OD In case the OD pin is connected to VCC by an external pull-up resistor ROD_ext, the OD discharge time is determined by the external network ROD_ext COD and by the internal MOSFET's RON_OD (Equation 3), while the Restart time is determined by current in ROD_ext (Equation 4) Equation 3 (3) V V  t1 ≅ COD ∙ ROD_ext / /RON_OD  ∙ ln V OD −− Von SSDl on Equation 4 (4) V V t2 ≅ COD ∙  ROD_ext  ∙ ln V SSDl − VOD   SSDh − OD where RON_OD   Von = R ∙ Vcc ; OD_ext + RON_OD  VOD = Vcc Figure 10. Smart shutdown timing waveforms VREF CIN t FCIN t FCIN Fast shut down t CINoff the driver outputs are switched off immediately after the comparator triggering LVG/HVG VOD OD VSSDh VSSDl 1 OD gate (internal) 2 t1 t2 disable time FAULT SMART SHUTDOWN CIRCUIT external pull-up VCC 5V 5V ROD_ext IOD OD OD SMART SD LOGIC COD RON_OD DS12981 - Rev 5 IOD SMART SD LOGIC COD RON_OD page 19/32 STSPIN32F0601, STSPIN32F0602 Microcontroller unit 6.2 Microcontroller unit The integrated MCU is the STM32F031x6 with the following main characteristics: • • • • • • • Core: ARM® 32-bit Cortex® -M0 CPU, frequency up to 48 MHz Memories: 4kB of SRAM, 32 kB of Flash Memory CRC calculation unit Up to 21 fast I/Os Advanced-control timer dedicated for PWM generation Up to 6 general purpose timers 12-bit ADC (up to 10 channels) • • • Communication interfaces: I2C, USART, SPI Serial Wire Debug (SWD) Extended temperature range: -40 to 125°C Note: For more details refer to the STM32F031x6 datasheet on www.st.com 6.2.1 Memories and boot mode The device has the following features: • 4 Kbytes of embedded SRAM accessed (read/write) at CPU clock speed with 0 wait states and featuring embedded parity checking with exception generation for fail-critical applications. • The non-volatile memory is divided into two arrays: – 32 Kbytes of embedded Flash memory for programs and data – Option bytes The option bytes are used to write-protect the memory (with 4 KB granularity) and/or readout-protect the whole memory with the following options: • Level 0: no readout protection • Level 1: memory readout protection, the Flash memory cannot be read from or written to if either debug features are connected or boot in RAM is selected • Level 2: chip readout protection, debug features (Cortex®-M0 serial wire) and boot in RAM selection disabled. At startup, the boot pin and boot selector option bit are used to select one of the three boot options: • boot from User Flash memory • boot from System Memory • boot from embedded SRAM The boot loader is located in System Memory, programmed by ST during production. It is used to reprogram the Flash memory by using USART on pins PA14/PA15. 6.2.2 Power management The VDD pin is the power supply for I/Os and the internal regulator. The VDDA pin is power supply for ADC, Reset blocks, RCs and PLL. The VDDA voltage is provided externally through VDDA pin Note: DS12981 - Rev 5 The VDDA voltage level must be always greater or equal to the VDD voltage level and must be established first. The MCU has integrated power-on reset (POR) and power-down reset (PDR) circuits. They are always active, and ensure proper operation above a threshold of 2 V. The device remains in reset mode when the monitored supply voltage is below a specified threshold, VPOR/PDR, without the need for an external reset circuit. • The POR monitors only the VDD supply voltage. During the startup phase it is required that VDDA should arrive first and be greater than or equal to VDD. • The PDR monitors both the VDD and VDDA supply voltages, however the VDDA power supply supervisor can be disabled (by programming a dedicated Option bit) to reduce the power consumption if the application design ensures that VDDA is higher than or equal to VDD. page 20/32 STSPIN32F0601, STSPIN32F0602 Microcontroller unit The device features an embedded programmable voltage detector (PVD) that monitors the VDD power supply and compares it to the VPVD threshold. An interrupt can be generated when VDD drops below the VPVD threshold and/or when VDD is higher than the VPVD threshold. The interrupt service routine can then generate a warning message and/or put the MCU into a safe state. The PVD is enabled by software. The MCU supports three low-power modes to achieve the best compromise between low power consumption, short startup time and available wakeup sources: • Sleep mode • In Sleep mode, only the CPU is stopped. All peripherals continue to operate and can wake up the CPU when an interrupt/event occurs. Stop mode • Stop mode achieves very low power consumption while retaining the content of SRAM and registers. All clocks in the 1.8 V domain are stopped, the PLL, the HSI RC and the HSE crystal oscillators are disabled. The voltage regulator can also be put either in normal or in low power mode. The device can be woken up from Stop mode by any of the EXTI lines (one of the 16 external lines, the PVD output, RTC, I2C1 or USART1). Standby mode The Standby mode is used to achieve the lowest power consumption. The internal voltage regulator is switched off so that the entire 1.8 V domain is powered off. The PLL, the HIS RC and the HSE crystal oscillators are also switched off. After entering Standby mode, SRAM and register contents are lost except for registers in the RTC domain and Standby circuitry. The device exits Standby mode when an external reset (NRST pin), an IWDG reset, a rising edge on the WKUP pins, or an RTC event occurs. 6.2.3 High-speed external clock source The high-speed external (HSE) clock can be generated from external clock signal or supplied with a 4 to 32 MHz crystal/ceramic resonator oscillator (see Figure 11). In the application, the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and startup stabilization time. Figure 11. Typical application with 8 MHz crystal 1. 2. The REXT value depends on the crystal characteristics (refer to the crystal resonator manufacturer for more details on them). The external clock signal has to respect the I/O characteristics and follows recommended clock input waveform (refer to Figure 12). Figure 12. HSE clock source timing diagram DS12981 - Rev 5 page 21/32 STSPIN32F0601, STSPIN32F0602 Advanced-control timer (TIM1) 6.3 Advanced-control timer (TIM1) The advanced-control timer (TIM1) can be seen as a three-phase PWM multiplexed on six channels. It has complementary PWM outputs with programmable inserted deadtimes. This timer is used to generate the PWM signal for the three half-bridge gate drivers as shown in Table 9. Table 9. TIM1 channel configuration DS12981 - Rev 5 MCU I/O ASIC input TIM1 channel PB13 LIN1 TIM1_CH1N PB14 LIN2 TIM1_CH2N PB15 LIN3 TIM1_CH3N PA8 HIN1 TIM1_CH1 PA9 HIN2 TIM1_CH2 PA10 HIN3 TIM1_CH3 page 22/32 STSPIN32F0601, STSPIN32F0602 Package information 7 Package information In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com. ECOPACK is an ST trademark. 7.1 TQFP 10x10 64L package information Figure 13. TQFP mechanical data BOTTOM VIEW DS12981 - Rev 5 EXPOSED PAD page 23/32 STSPIN32F0601, STSPIN32F0602 TQFP 10x10 64L package information Table 10. TQFP package dimensions Symbol Max A - - 1.2 STAND OFF A1 0.05 - 0.15 MOLD THICKNESS A2 0.95 - 1.05 LEAD WIDTH(PLATING) b 0.17 0.22 0.27 LEAD WIDTH b1 0.17 0.2 0.23 L/F THICKNESS(PLATING) c 0.09 - 0.2 L/F THICKNESS c1 0.09 - 0.16 X D - 12 - Y E - 12 - X D1 - 10 - Y E1 - 10 - e - 0.5 - L 0.45 0.6 0.75 θ 0° 3.5° 7° θ1 0° - - θ2 11° 12° 13° θ3 11° 12° 13° R1 0.08 - - R2 0.08 - 0.2 S 0.2 - - X M 5.85 5.95 6.05 Y N 5.85 5.95 6.05 LEAD PITCH EP SIZE DS12981 - Rev 5 Nom TOTAL THICKNESS BODY SIZE Note: Min PACKAGE LEAD TOLERANCE aaa 0.2 LEAD EDGE TOLERANCE bbb 0.2 COPLANARITY ccc 0.08 LEAD OFFSET ddd 0.08 MOLD FLATNESS eee 0.05 All dimensions are mm unless otherwise specified page 24/32 STSPIN32F0601, STSPIN32F0602 TQFP 10x10 64L package information Figure 14. QFN mechanical data TOP VIEW BOTTOM VIEW EXPOSED PAD SIDE VIEW Table 11. QFN package dimensions Symbol Min Non Max TOTAL THICKNESS A 0.90 0.95 1.00 STAND OFF A1 0 L/F THICKNESS A3 0.20 Ref. LEAD WIDTH b 0.15 0.20 0.25 BODY LENGTH X D 9.90 10.00 10.10 EP LENGTH X D2 5.40 5.50 5.60 LEAD PITCH e BODY WIDTH Y E 9.90 10.00 10.10 EP WIDTH Y E2 5.40 5.50 5.60 L 0.30 0.40 0.50 LEAD LENGTH DS12981 - Rev 5 0.05 0.50 BSC page 25/32 STSPIN32F0601, STSPIN32F0602 Suggested land pattern Symbol Min Non K Note: All dimensions are mm unless otherwise specified 7.2 Suggested land pattern Max 1.85 Ref. Figure 15. TQFP 10x10 64L suggested land pattern 11.45 1.25 .50 11.45 6.00 6.00 Note: .25 All dimensions are mm unless otherwise specified Figure 16. QFN 10x10 72L suggested land pattern DS12981 - Rev 5 page 26/32 STSPIN32F0601, STSPIN32F0602 Ordering information 8 Ordering information Table 12. Order codes Order code DS12981 - Rev 5 Package Package marking Packaging STSPIN32F0601 TQFP 10x10 64L STSPIN32F0 601 Tray STSPIN32F0601TR TQFP 10x10 64L STSPIN32F0 601 Tape and Reel STSPIN32F0602 TQFP 10x10 64L STSPIN32F0 602 Tray STSPIN32F0602TR TQFP 10x10 64L STSPIN32F0 602 Tape and Reel STSPIN32F0601Q QFN 10 x 10 72L SPINF601Q Tray STSPIN32F0601QTR QFN 10 x 10 72L SPINF601Q Tape and Reel STSPIN32F0602Q QFN 10 x 10 72L SPINF602Q Tray STSPIN32F0602QTR QFN 10 x 10 72L SPINF602Q Tape and Reel page 27/32 STSPIN32F0601, STSPIN32F0602 Revision history Table 13. Document revision history DS12981 - Rev 5 Date Version Changes 12-Jun-2019 1 Initial release. 29-Aug-2019 2 Minor text changes 04-Sept-2019 3 Minor change to Table 10 28-Oct-2020 4 Added QFN package version 20-Feb-2021 5 Updated Table 5, Table 7. Updated Figure 6, 7, 8, 9, and 10. page 28/32 STSPIN32F0601, STSPIN32F0602 Contents Contents 1 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 2 Pin description and connection diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 3 Pin description table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 4 Electrical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 4.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 4.2 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 4.3 Recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 5 Electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 6 Device description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 6.1 6.2 6.3 7 8 Gate driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 6.1.1 Inputs and outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 6.1.2 Deadtime . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 6.1.3 VCC UVLO protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 6.1.4 VBO UVLO protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 6.1.5 Comparator and Smart shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Microcontroller unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 6.2.1 Memories and boot mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 6.2.2 Power management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 6.2.3 High-speed external clock source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Advanced-control timer (TIM1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Package information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 7.1 [Package name] package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 7.2 Suggested land pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 List of tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 List of figures. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 DS12981 - Rev 5 page 29/32 STSPIN32F0601, STSPIN32F0602 List of tables List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Legend/abbreviations used in the pin description table . . . . . . . . . . . . . . . . . . . STSPIN32F060x MCU-Driver internal connections . . . . . . . . . . . . . . . . . . . . . . Pin description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Recommended operating conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Inputs truth table (applicable when device is not in UVLO or SmartSD protection) TIM1 channel configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TQFP package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . QFN package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Order codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DS12981 - Rev 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 . 5 . 6 . 8 . 9 . 9 10 16 22 24 25 27 28 page 30/32 STSPIN32F0601, STSPIN32F0602 List of figures List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. DS12981 - Rev 5 STSPIN32F060x SiP block diagram . . . . . . . . . . STSPIN32F060x pin connection (TQFP top view) . STSPIN32F060x pin connection (QFN top view) . . Propagation delay timing definition . . . . . . . . . . . Deadtime timing definitions . . . . . . . . . . . . . . . . Deadtime and interlocking waveforms definition . . VCC power ON and UVLO, LVG timing . . . . . . . . VCC power ON and UVLO, HVG timing . . . . . . . . VBO Power-ON and UVLO timing . . . . . . . . . . . . Smart shutdown timing waveforms . . . . . . . . . . . Typical application with 8 MHz crystal . . . . . . . . . HSE clock source timing diagram . . . . . . . . . . . . TQFP mechanical data . . . . . . . . . . . . . . . . . . . QFN mechanical data . . . . . . . . . . . . . . . . . . . . TQFP 10x10 64L suggested land pattern . . . . . . . QFN 10x10 72L suggested land pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 . 4 . 4 14 14 15 17 17 18 19 21 21 23 25 26 26 page 31/32 STSPIN32F0601, STSPIN32F0602 IMPORTANT NOTICE – PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement. Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers’ products. No license, express or implied, to any intellectual property right is granted by ST herein. Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. ST and the ST logo are trademarks of ST. For additional information about ST trademarks, please refer to www.st.com/trademarks. All other product or service names are the property of their respective owners. Information in this document supersedes and replaces information previously supplied in any prior versions of this document. © 2021 STMicroelectronics – All rights reserved DS12981 - Rev 5 page 32/32