STSPIN32F0ATR

STSPIN32F0A Advanced BLDC controller with embedded STM32 MCU Datasheet - production data • • • • • • • • • • Features • • • Extended operating voltage from 6.7 to 45 V Three-phase gate drivers − 600 mA sink/source − Integrated bootstrap diodes − Cross-conduction prevention 32-bit ARM® Cortex®-M0 core: − Up to 48 MHz clock frequency − 4-kByte SRAM with HW parity − 32-kByte Flash memory with option bytes used for write/readout protection − Availability FW bootloader September 2017 • • 3.3. V DC/DC buck converter regulator with overcurrent, short-circuit, and thermal protection 12 V LDO linear regulator with thermal protection 16 general-purpose I/O ports (GPIO) 5 general-purpose timers 12-bit ADC converter (up to 9 channels) I2C, USART and SPI interfaces 3 rail-to-rail operation amplifiers for signal conditioning Comparator for overcurrent protection with programmable threshold Standby mode for low power consumption UVLO protection on each power supply: − VM, VDD, VREG and VBOOTx On-chip debug support via SWD Extended temperature range: -40 to +125 °C Applications • • • • Smart manufacturing equipment Power tools, FANs and pumps Home appliances: vacuum cleaners, hand/hair dryers, air purifiers and coffee machines High-tech applications such as: drones, gimbals, educational/home robots DocID030766 Rev 2.0 This is information on a product in full production. 1/41 www.st.com Contents STSPIN32F0A Contents 1 Description....................................................................................... 5 2 Block diagrams................................................................................ 6 3 Electrical data .................................................................................. 8 3.1 Absolute maximum ratings ................................................................ 8 3.2 ESD protections ................................................................................ 9 3.3 Recommended operating conditions ................................................. 9 3.4 Thermal data ................................................................................... 10 4 Electrical characteristics .............................................................. 11 5 Pin description .............................................................................. 15 6 Device description......................................................................... 21 6.1 6.2 UVLO and thermal protections ........................................................ 21 6.1.1 UVLO on supply voltages ................................................................. 22 6.1.2 Thermal protection............................................................................ 22 DC/DC buck regulator ..................................................................... 22 6.2.1 External optional 3.3 V supply voltage ............................................. 23 6.3 Linear regulator ............................................................................... 24 6.4 Standby mode ................................................................................. 25 6.5 Gate drivers..................................................................................... 26 6.6 Microcontroller unit .......................................................................... 27 6.6.1 Memories and boot mode ................................................................. 27 6.6.2 Power management ......................................................................... 27 6.6.3 High-speed external clock source .................................................... 28 6.6.4 Advanced-control timer (TIM1) ......................................................... 29 6.7 Test mode ....................................................................................... 30 6.8 Operational amplifiers ..................................................................... 30 6.9 Comparator ..................................................................................... 30 6.10 ESD protection strategy .................................................................. 33 7 Application example...................................................................... 34 8 Package information ..................................................................... 36 8.1 VFQFPN48 7 x 7 package information ............................................ 37 9 Ordering information..................................................................... 39 10 Revision history ............................................................................ 40 2/41 DocID030766 Rev 2.0 STSPIN32F0A List of tables List of tables Table 1: Absolute maximum ratings ........................................................................................................... 8 Table 2: ESD protection ratings .................................................................................................................. 9 Table 3: Recommended operating conditions ............................................................................................ 9 Table 4: Thermal data ............................................................................................................................... 10 Table 5: Electrical characteristics ............................................................................................................. 11 Table 6: STSPIN32F0A SiP pin description ............................................................................................. 15 Table 7: STSPIN32F0A MCU pad mapping ............................................................................................. 17 Table 8: STSPIN32F0A analog IC pad description .................................................................................. 18 Table 9: UVLO and OT protection management ...................................................................................... 21 Table 10: TIM1 channel configuration ...................................................................................................... 29 Table 11: OC protection selection ............................................................................................................ 31 Table 12: OC threshold values ................................................................................................................. 31 Table 13: VFQFPN48 7 x 7 x 1.0 - 48L, pitch 0.5 - package mechanical data ........................................ 38 Table 14: Order codes .............................................................................................................................. 39 Table 15: Document revision history ........................................................................................................ 40 DocID030766 Rev 2.0 3/41 List of figures STSPIN32F0A List of figures Figure 1: STSPIN32F0A System-In-Package block diagram ..................................................................... 6 Figure 2: Analog IC block diagram ............................................................................................................. 7 Figure 3: Gate drivers timing .................................................................................................................... 14 Figure 4: STSPIN32F0A SiP pin connection (top view) ........................................................................... 15 Figure 5: Gate drivers' outputs characteristics in UVLO conditions ......................................................... 21 Figure 6: Power-up and power-down sequence ....................................................................................... 22 Figure 7: DC/DC buck regulator topology ................................................................................................. 23 Figure 8: Soft-start timing ......................................................................................................................... 23 Figure 9: Linear regulator block diagram .................................................................................................. 24 Figure 10: Linear regulator output characteristics .................................................................................... 25 Figure 11: “Standby to normal” operation timing (CREG = 1 µF) ............................................................. 26 Figure 12: HSE clock source timing diagram ........................................................................................... 29 Figure 13: Typical application with 8 MHz crystal ..................................................................................... 29 Figure 14: Operational amplifiers .............................................................................................................. 30 Figure 15: Comparator .............................................................................................................................. 31 Figure 16: Driver logic overcurrent management signals ......................................................................... 32 Figure 17: ESD protection strategy........................................................................................................... 33 Figure 18: Application example ................................................................................................................ 35 Figure 19: VFQFPN48 7 x 7 x 1.0 - 48L, pitch 0.5 package outline ......................................................... 37 Figure 20: VFQFPN48 7 x 7 x 1.0 - 48L, pitch 0.5 - suggested footprint ................................................. 38 4/41 DocID030766 Rev 2.0 STSPIN32F0A 1 Description Description The STSPIN32F0A is a System-In-Package providing an integrated solution suitable for driving three-phase BLDC motors using different driving modes. It embeds a triple half-bridge gate driver able to drive power MOSFETs with a current capability of 600 mA (sink and source). The high- and low-side switches of same halfbridge cannot be simultaneously driven high thanks to an integrated interlocking function. An internal DC/DC buck converter provides the 3.3 V voltage suitable to supply both the MCU and external components. An internal LDO linear regulator provides the supply voltage for gate drivers. The integrated operational amplifiers are available for the signal conditioning, e.g. the current sensing across the shunt resistors. A comparator with a programmable threshold is integrated to perform the overcurrent protection. The integrated MCU (STM32F031C6 with extended temperature range, suffix 7 version) allows performing field-oriented control, the 6-step sensorless and other advanced driving algorithms. It has the write-protection and read-protection feature for the embedded Flash memory to protect against unwanted writing and/or reading. It is possible to download the firmware on-the-field through the serial interface thanks to the embedded bootloader. The STSPIN32F0A device also features overtemperature and undervoltage lockout protections and can be put in the standby mode to reduce the power consumption. The device provides 16 general-purpose I/O ports (GPIO) with the 5 V tolerant capability, one 12-bit analog-to-digital converter with up to 9 channels performing conversions in a singleshot or scan modes, 5 synchronizable general-purpose timers and supports an easy to use debugging serial interface (SWD). DocID030766 Rev 2.0 5/41 6/41 CDDA STM32F031 VDD VBAT PA3 VDDA PA0 PA1 PA2 PA3 VDD PA2 BOOT0 PA1 PB6 PA0 PB7 PA14 PA15 PB3 PB4 PB5 PB6 PB7 BOOT0 PB8 PB9 VSS NRST PA15 PF7 PF6 PA13 PA12 PA11 PA10 PA9 PA8 PB15 PB14 PB13 PB12 RESERVED 3.3 V 2 to VDDA VDDA PC13 PC14 PC15 PF0 PF1 NRST VSSA PA14_SWD_CLK control CVM 6 OC_SEL OC compthreshold select DC/DCbuck conv. VM + PB1 PB0 PA7 PA6 PA5 PA4 DocID030766 Rev 2.0 OPAMP PA13_SWD_IO Connected to EPAD OP2P OP2O OP2N OPAMP OP3N OP3P OP3O TESTMODE GND PB11 PB10 PB2 VDD VSS PB1 PA7 PA6 PA5 PA4 RP1 RN1 CLP HS LS HS LS Current sensing feedback VREG12 VREG12 LS VREG12 VREG12 RLP HS VREG12 VREG12 VREG12 Current sensing feedback OC_COMP to MCU OP1P OP1N OP1O RN2 OPAMP VDD COMP ADJ REF RP2 Control logic gate driver 3x OpAmp net 12 V VREG VM CREG CVDD VREG12V OPP OPN OPO SW VDD CRST PF0 3.3 V CDD VM VDD LSW OUTW HSW VBOOTW LSV OUTV HSV VBOOTV LSU OUTU HSU VBOOTU LS HS to OpAmps OC_COMP RGL RGH CBOOT VM 3x power half-bridge LS OUT HS VBOOT M THREE-PHASE MOTOR 2 PF1 CDD VDD L1 Block diagrams STSPIN32F0A Block diagrams Figure 1: STSPIN32F0A System-In-Package block diagram STSPIN32F0A Block diagrams VREG12V SW VM VDD_3V3 PA13_SWD_IO Figure 2: Analog IC block diagram VM 3.3V VM 12 V VREG VREG12 VREG12 VBOOTU HS Control SWDIO_INT HSU OUTU VREG12 DC/DCbuckconv. OC_TH_STBY1 OC_TH_STBY2 OC_COMP_INT2 OC_SEL HS3 HS2 HS1 LS3 LS2 LS1 2 OCcompthresholdselect LS LSU VREG12 6 OC_COMP_INT1 Control logic gate driver OC_SEL VBOOTV HS HSV OUTV VREG12 LS LSV VREG12 VBOOTW HS 3.3 V VDD HSW OUTW VREG12 DocID030766 Rev 2.0 LS LSW OCComp ADJ REFCOMP OPAMP OP1P OP1O OP1N OPAMP OP2P OP2N OP2O OP3N OP3O GND OP3P OPAMP TESTMODE 7/41 Electrical data STSPIN32F0A 3 Electrical data 3.1 Absolute maximum ratings Stresses above the absolute maximum ratings listed in Table 1: "Absolute maximum ratings" may cause permanent damage to the device. Exposure to maximum rating conditions for extended periods may affect device reliability. Table 1: Absolute maximum ratings Symbol VM Parameter Test condition Value Unit - -0.3 to 48 V VREG12 shorted to VM 15 V Power supply voltage VREG12 Linear regulator output and gate driver supply voltage VOPP Op amp positive input voltage - -0.2 to VDD + 0.2 V VOPN Op amp negative input voltage - -0.2 to VDD + 0.2 V VCP Comparator input voltage - -2 to 2 V VHS High-side gate output voltage - VOUT - 0.3 to VBOOT + 0.3 V VLS Low-side gate output voltage - -0.3 to VREG12 + 0.3 V VBOOT Bootstrap voltage - Max. (VOUT - 0.3 or -0.3) to min. ('VOUT + VREG12 + 0.3' or 60) V VOUT Output voltage (OUTU, OUTV, OUTW) - -2 to VM + 2 V Output slew rate - ± 10 V/ns dVOUT/dt TTa type MCU logic input voltage(1) VIO IIO MCU I/O output current (1) (1) FT, FTf type -0.3 to 4 -0.3 to VDD + 4 (2) V BOOT0 0 to 9.0 (1) -25 to 25 mA (1), (3) -80 to 80 mA ΣIIO MCU I/O total output current VDD MCU digital supply voltage (1) -0.3 to 4 V VDDA MCU analog supply voltage (1) -0.3 to 4 V Tstg Storage temperature - -55 to 150 °C Operating junction temperature - -40 to 150 °C Tj Notes: (1)See Table 15 Voltage characteristics in the STM32F031C6 datasheet (suffix 7 version). (2)Valid only if the internal pull-up/pull-down resistors are disabled. If internal the pull-up or pull-down resistor is enabled, the maximum limit is 4 V. (3)If the MCU supply voltage is provided by an integrated DC/DC regulator, the application current consumption is limited at IDDA,max value (see Table 5: "Electrical characteristics"). 8/41 DocID030766 Rev 2.0 STSPIN32F0A 3.2 Electrical data ESD protections Table 2: ESD protection ratings Symbol 3.3 Parameter Test condition Class Value Unit HBM Human body model Conforming to ANSI/ESDA/JEDEC JS-001-2014 H2 2 kV CDM Charge device model Conforming to ANSI/ESDA/JEDEC JS-002-2014 C2 750 V Typ. Max. Unit (1) - 45 V VM = 45 V - - 0.75 V/µs Recommended operating conditions Table 3: Recommended operating conditions Symbol VM Parameter Test condition Power supply voltage dVM/dt Power supply voltage slope Min. 6.7 - VDDA DC/DC regulator output voltage - - 3.3 - V LSW Output inductance - - 22 - µH CDDA Output capacitance - 47 - - µF Output capacitor ESR - - - 200 mΩ 13 < VM < 45 V - 12 - - 15 ESRDDA Linear regulator output and gate driver supply voltage VREG12 CREG Shorted to VM 6.7 (1) V Load capacitance - 1 10 - µF ESR load capacitance - - - 1.2 Ω VBO Floating supply voltage (2) - - VREG12 1 15 V VCP Comparator input voltage - 0 - 1 V -40 - 125 °C -40 - 125 °C ESRREG Analog IC Tj Operating junction temperature MCU (3) Notes: (1)UVLO threshold VMOn_max. (2) VBO = VBOOT - VOUT. (3) See the STM32F031C6 datasheet (suffix 7 version). DocID030766 Rev 2.0 9/41 Electrical data 3.4 STSPIN32F0A Thermal data Thermal values are calculated by simulation with the following boundary conditions: 2s2p board as per the std. JEDEC (JESD51-7) in natural convection, board dimensions: 114.3 x 76.2 x 1.6 mm, ambient temperature: 25 °C. Table 4: Thermal data 10/41 Symbol Parameter Value Unit Rth (JA) Thermal resistance junction to ambient 45.6 °C/W DocID030766 Rev 2.0 STSPIN32F0A 4 Electrical characteristics Electrical characteristics Testing conditions: VM = 15 V; VDD = 3.3 V, unless otherwise specified. Typical values are tested at Tj = 25 °C, minimum and maximum values are guaranteed by thermal characterization in the temperature range of -40 to 125 °C, unless otherwise specified. Table 5: Electrical characteristics Symbol Parameter Test condition Min. Typ. Max. Unit VM = 45 V; VDD = 3.5 V externally supplied - 2 2.6 mA Standby PF7 = '0' PF6 = '0 VM = 45 V; VDD = 3.5 V externally supplied - 880 1100 µA Power supply and standby mode IM VM current consumption VMOn VM UVLO turn-on threshold VM rising from 0 V 6.0 6.3 6.6 V VMOff VM UVLO turn-off threshold VM falling from 8 V 5.8 7.1 6.4 V VMHys VM UVLO threshold hysteresis - - 0.2 - V VDD = 3.5 V externally supplied (1) - 2.5 5 Standby PF7 = '0' PF6 = '0' VDD = 3.5 V externally supplied(1) - 2.5 5 VDD = 3.5 V externally supplied(1) - 400 550 Standby PF7 = '0' PF6 = '0' VDD = 3.5 V externally supplied(1) - 80 125 IDD IDDA VDD current consumption VDDA current consumption mA µA VDDOn VDD UVLO turn-on threshold VDD rising from 0 V 2.5 2.65 2.8 V VDDOff VDD UVLO turn-off threshold VDD falling from 3.3 V 2.2 2.35 2.5 V VDDHys VDD UVLO threshold hysteresis - - 0.3 - V VREG = 13 V externally supplied, VM = 45 V; no commutation - 800 1200 Standby PF7 = '0' PF6 = '0' VREG = 13 V externally supplied - 800 1200 IREG12 VREG current consumption µA VREG12On VREG12 UVLO turn-on threshold VREG12 rising from 0 V 6.0 6.3 6.6 V VREG12Off VREG12 UVLO turn-off threshold VREG12 falling from 8 V 5.8 6.1 6.4 V VREG12Hys VREG12 UVLO threshold hysteresis - - 0.25 - V IBOOT VBO current consumption HS on VBO = 13 V - 200 290 µA VBOOn VBO UVLO turn-on threshold VBO rising from 0 V 5.5 5.8 6.1 V VBOOff VBOUVLO turn-off threshold VBO falling from 8 V 5.3 5.6 5.9 V DocID030766 Rev 2.0 11/41 Electrical characteristics Symbol STSPIN32F0A Parameter Test condition Min. Typ. Max. Unit VBO UVLO threshold hysteresis - - 0.15 - V Standby set time - - - 1 µs Power good voltage - 5.6 6 6.4 V VDDA Average output voltage (2) 3.09 3.3 3.5 V IDDA Output current DC; MCU current consumption included - - 70 mA fSW Maximum SW switching frequency Open loop, VDDA floating ISW = 100 mA - 200 330 kHz Switch ON resistance ISW = 200 mA - 1.4 - Ω - 80 - % VBOHys tsleep DC/DC switching regulator VPWR_OK RSWDS(ON) η IDDA,max(2) Efficiency VM = 8 V; IDDA = Peak current threshold - - 320 - mA IOVC Latched overcurrent threshold - - 1 - A tSS Soft-start time - 2.5 5 7.5 ms Linear regulator output and gate driver supply voltage VM = 13 ÷ 45 V (3) IO = 10 mA 11.4 12 12.6 V Drop voltage VM = 8 ÷ 11 V, IO = 10 mA - 200 400 mV Linear regulator current limit VM = 13 V 20 - 40 mA Maximum sink/source current capabilities TJ = 25 °C 400 600 - mA Full temperature range 350 - - mA Input lines pull-down resistor - 30 60 95 kΩ ton toff Input-to-output propagation delay (4) - - 20 40 ns MT Delay matching, HS and LS turn-on/off (5) - - 10 20 ns Bootstrap diode ON resistance - - 120 240 Ω - -0.1 - VDD + 0.1 V Vout = 1.65; Tj = 25 °C - 1 6 mV Vout = 1.65; full temp. range - - 7 mV ISW,peak Linear regulator VREG12 VREG12,drop IREG12,lim Gate drivers ISI ISO RPDin RDS_diode Operational amplifiers Vicm Input common mode voltage range VOPio Input offset voltage IOPio Input offset current Vout = 1.65 (6) - - 100 pA IOPib Input bias current (6) - - 100 pA Common mode rejection ratio 0 to 3.3 V; Vout = 1.65 V 70 90 - dB CMRR 12/41 DocID030766 Rev 2.0 STSPIN32F0A Symbol Electrical characteristics Parameter Test condition Min. Typ. Max. Unit Open loop gain RL = 10 kΩ; Vout = 1.65 - 90 - dB VDD - VOH High level output voltage RL = 10 kΩ - 15 40 mV VOL Low level output voltage RL = 10 kΩ(7) - 15 40 mV Vout = 3.3 V; Tj = 25 °C 18 - - mA Vout = 3.3 V; full temp. range 16 - - Vout = 0 V; Tj = 25 °C 18 - - Vout = 0 V; full temp. range 16 - - AOL (7) Sink output current IOUT mA Source output current GBP Gain bandwidth product RL = 2 kΩ; CL = 100 pF Vout = 1.65 10 18 - MHz Gain Minimum gain for stability Phase margin = 45° 0.2 V < Vout < VDD - 0.2 - 4 - V/V Slew rate RL = 2 kΩ; CL = 100 pF Vin 1 to 2 V step - 10 - V/µs PF6 = '0' PF7 = '1' 90 - 120 mV PF6 = '1' PF7 =' 0' 235 255 275 mV PF6 = '1' PF7 = '1' 465 505 545 mV - 80 120 ns SR OC comparator OCth Overcurrent threshold Comparator propagation delay OCth = 0.5 V; OC_Comp: voltage step from 0 to 1 V tOCdeglitch Comparator input deglitch filter time (8) 35 50 - ns tOCrelease Minimum overcurrent latch release pulse width (8) - - 20 ns tCPD Thermal protection TSD Thermal shut-down temperature - 130 140 150 °C Thys Thermal shut-down hysteresis - 20 30 40 °C Notes: (1)The current consumption depends on the firmware loaded in the microcontroller. (2)Using the 47 μF capacitor (APXG250ARA470MF61G), 22 μH inductor (MLF1608C220KTA00), and diode 1N4448TR. (3)With 11 < VM < 13 V the linear output voltage can be VREG12 or 'VM-VREG12,drop' depending on the linear regulator is already turned-on or not. (4)Figure (5) 3: "Gate drivers timing". MT = max. (|ton(LVG) - toff(LVG)|, |ton(HVG) - toff(HVG)|, |toff(LVG) - ton(HVG)|, |toff(HVG) - ton(LVG)|). (6)Guaranteed by design. (7)Guaranteed by IOUT test. (8) See Figure 16: "Driver logic overcurrent management signals". DocID030766 Rev 2.0 13/41 Electrical characteristics STSPIN32F0A Figure 3: Gate drivers timing LS1 (2) (3) HS1 (2) (3) 50% 50% 90% LSU(V)(W) HSU(V)(W) 10% toff ton 14/41 DocID030766 Rev 2.0 STSPIN32F0A Pin description VDD OP3O OP3N OP3P GND RESERVED BOOT0 PB7 PB6 PA15 PA14_SWD_CLK PA13_SWD_IO Figure 4: STSPIN32F0A SiP pin connection (top view) 48 47 46 45 44 43 42 41 40 39 38 37 OP2P 1 36 LSU OP2N 2 35 VBOOTU OP2O 3 34 OUTU PF0 4 33 HSU PF1 5 32 LSV VREG12 6 31 VBOOTV NRST 7 30 OUTV VM 8 29 HSV SW 9 28 LSW VDDA 10 27 VBOOTW PA0 11 26 OUTW PA1 12 25 HSW 16 17 18 19 20 21 22 PA5 PA6 PA7 PB1 TESTMODE OP1O OP1N 23 24 OC_Comp 15 OP1P 14 PA4 13 PA3 EPAD PA2 5 Pin description Table 6: STSPIN32F0A SiP pin description No. Name Type Function 1 OP2P Analog in Op amp 2 non-inverting input 2 OP2N Analog in Op amp 2 inverting input 3 OP2O Analog out 4 PF0 GPIO MCU PF0 5 PF1 GPIO MCU PF1 6 VREG12 Power 12 V linear regulator output 7 NRST GPIO MCU reset pin 8 VM Power Power supply voltage (bus voltage) 9 SW Analog out Op amp 2 output 3.3 V DC/DC buck regulator switching node DocID030766 Rev 2.0 15/41 Pin description 16/41 STSPIN32F0A No. Name Type Function 10 VDDA Power MCU analog power supply voltage 11 PA0 GPIO MCU PA0 12 PA1 GPIO MCU PA1 13 PA2 GPIO MCU PA2 14 PA3 GPIO MCU PA3 15 PA4 GPIO MCU PA4 16 PA5 GPIO MCU PA5 17 PA6 GPIO MCU PA6 18 PA7 GPIO MCU PA7 19 PB1 GPIO MCU PB1 20 TESTMODE Digital In Test mode input 21 OP1O Analog out Op amp 1 output 22 OP1N Analog in Op amp 1 inverting input 23 OP1P Analog in Op amp 1 non-inverting input 24 OC_COMP Analog in Overcurrent comparator input 25 HSW Analog out 26 OUTW Power W phase high-side (floating) common voltage 27 VBOOTW Power W phase bootstrap supply voltage 28 LSW Analog out W phase low-side driver output 29 HSV Analog out V phase high-side driver output 30 OUTV Power V phase high-side (floating) common voltage 31 VBOOTV Power V phase bootstrap supply voltage 32 LSV Analog out V phase low-side driver output 33 HSU Analog out U phase high-side driver output 34 OUTU Power U phase high-side (floating) common voltage 35 VBOOTU Power U phase bootstrap supply voltage 36 LSU Analog out 37 PA13_SWD_IO GPIO MCU PA13/SWDIO (system debug data via analog IC) 38 PA14_SWD_CLK GPIO MCU PA14/SWDCLK (system debug clock) 39 PA15 GPIO MCU PA15 40 PB6 GPIO MCU PB6 41 PB7 GPIO MCU PB7 42 BOOT0 Digital in 43 RESERVED - 44 GND Power 45 OP3P Analog in Op amp 3 non-inverting input 46 OP3N Analog in Op amp 3 inverting input W phase high-side driver output U phase low-side driver output MCU BOOT0 Reserved for test mode (can be left floating in application) Ground DocID030766 Rev 2.0 STSPIN32F0A Pin description No. Name Type Function 47 OP3O Analog out 48 VDD Power MCU digital power supply EPAD Power Internally connected to ground Op amp 3 output Table 7: STSPIN32F0A MCU pad mapping Alternate and additional functions MCU pad Type Analog IC pad PF0 I/O - FT - OSC_IN PF1 I/O - FT - OSC_OUT NRST I/O - RST - Device reset input / internal reset output (active low) VDDA S VDD_3V3 PA0 I/O - TTa - TIM2_CH1_ETR, USART1_CTS ADC_IN0, RTC_TAMP2, WKUP1 PA1 I/O - TTa - TIM2_CH2, EVENTOUT, USART1_RTS ADC_IN1 PA2 I/O - TTa - TIM2_CH3, USART1_TX ADC_IN2 PA3 I/O - TTa - TIM2_CH4, USART1_RX ADC_IN3 PA4 I/O - TTa - SPI1_NSS, I2S1_WS, TIM14_CH1, USART1_CK ADC_IN4 PA5 I/O - TTa - SPI1_SCK, I2S1_CK, TIM2_CH1_ETR ADC_IN5 Analog power supply voltage PA6 I/O - TTa - SPI1_MISO, I2S1_MCK, TIM3_CH1, TIM1_BKIN, TIM16_CH1, EVENTOUT ADC_IN6 PB1 I/O - TTa - TIM3_CH4, TIM14_CH1, TIM1_CH3N ADC_IN9 SPI1_MOSI, I2S1_SD, TIM3_CH2, TIM14_CH1, TIM1_CH1N, TIM17_CH1, EVENTOUT ADC_IN7 PA7 I/O - TTa - PB12 I/O - FT OC_COMP_INT TIM1_BKIN (1) PB13 I/O - FT LS1 TIM1_CH1N(1) PB14 I/O - FT LS2 TIM1_CH2N(1) PB15 I/O - FT LS3 TIM1_CH3N(1) PA8 I/O - FT HS1 TIM1_CH1(1) DocID030766 Rev 2.0 17/41 Pin description STSPIN32F0A Alternate and additional functions MCU pad Type Analog IC pad PA9 I/O - FTf HS2 TIM1_CH2(1) PA10 I/O - FTf HS3 TIM1_CH3 PA11 I/O - FT OC_SEL PA12 I/O - FT OC_COMP_INT2 PA13_SWD_IO I/O - FT SWDIO_INT IR_OUT, SWDIO PF6 I/O - FTf OC_TH_STBY2 Push-pull output(1) PF7 I/O - FTf OC_TH_STBY1 Push-pull output(1) PA14_SWD_CLK I/O - FT - USART1_TX, SWCLK PA15 I/O - FT - SPI1_NSS, I2S1_WS, TIM2_CH_ETR, EVENTOUT, USART1_RX PB6 I/O - FTf - I2C1_SCL, USART1_TX, TIM16_CH1N PB7 I/O - FTf - I2C1_SDA, USART1_RX, TIM17_CH1N VBAT, VDD S VDD VSS, VSSA S - Ground BOOT0 I - Boot memory selection PC13, PC14, PC15, PB0, PB2, PB10, PB11, PA15, PB3, PB4, PB5, PB8, PB9 - - Not connected Push-pull output(1) TIM1_ETR(1) Backup and digital power supply Notes: (1)The analog IC is designed to support these GPIOs configuration only. Different configuration could cause device malfunctioning. The GPIO input configuration without pull-up or pull-down is always allowed. Each unused GPIO inside the SiP should be configured in the OUTPUT mode low level after the startup by software. Table 8: STSPIN32F0A analog IC pad description 18/41 Pinout name Pad name Type Function PA13_SWD_IO SYS_SWDIO Digital I/O System debug data (connected to the output through the analog IC) VDDA VDD_3V3 Power 3.3 V DC/DC buck regulator voltage output VM VM Power Power supply voltage (bus voltage) SW SW Analog out 3.3 V DC/DC buck regulator switching node VREG12 VREG12 Power 12 V linear regulator output VBOOTU VBOOTU Power U phase bootstrap supply voltage DocID030766 Rev 2.0 STSPIN32F0A Pin description Pinout name Pad name Type Function HSU HSU Analog out U phase high-side driver output OUTU OUTU Power U phase high-side (floating) common voltage LSU LSU Analog out U phase low-side driver output VBOOTV VBOOTV Power V phase bootstrap supply voltage HSV HSV Analog out V phase high-side driver output OUTV OUTV Power V phase high-side (floating) common voltage LSV LSV Analog out V phase low-side driver output VBOOTW VBOOTW Power W phase bootstrap supply voltage HSW HSW Analog out W phase high-side driver output OUTW OUTW Power W phase high-side (floating) common voltage LSW LSW Analog out W phase low-side driver output OC_Comp OC_COMP Analog in OP1P OP1P Analog out OP1N OP1N Analog in Op amp 1 inverting input OP1O OP1O Analog in Op amp 1 non-inverting input OP2P OP2P Analog out OP2N OP2N Analog in Op amp 2 inverting input OP2O OP2O Analog in Op amp 2 non-inverting input OP3P OP3P Analog out OP3N OP3N Analog in Op amp 3 inverting input OP3O OP3O Analog in Op amp 3 non-inverting input RESERVED RESERVED Analog in Reserved for test mode GND GND Power TESTMODE TESTMODE Digital in - VDD Power MCU digital power supply - OC_COMP_INT Digital out OC comparator output - HS1 Digital in High-side input driver U - HS2 Digital in High-side input driver V - HS3 Digital in High-side input driver W - LS1 Digital in Low-side input driver U - LS2 Digital in Low-side input driver V Overcurrent comparator input Op amp 1 output Op amp 2 output Op amp 3 output Ground Test mode input DocID030766 Rev 2.0 19/41 Pin description 20/41 STSPIN32F0A Pinout name Pad name Type Function - LS3 Digital in Low-side input driver W - OC_SEL Digital in OC protection selection - OC_COMP_INT2 Digital out OC comparator output - SWD_IO_INT Digital in System debug data (connected to the output through the analog IC) - OC_TH_STBY1 Digital in Overcurrent threshold selection and standby input 1 - OC_TH_STBY2 Digital in Overcurrent threshold selection and standby input 2 DocID030766 Rev 2.0 STSPIN32F0A 6 Device description Device description The STSPIN32F0A is a System-In-Package providing an integrated solution suitable for driving the three-phase BLDC motors. The device will be developed in the BCD8s (0.18 µm) technology. 6.1 UVLO and thermal protections Table 9: "UVLO and OT protection management" summarizes the UVLO and OT protection management. Table 9: UVLO and OT protection management VM UVLO VDD UVLO VREG12 UVLO VBOOT UVLO Lin. Reg OT DC/DC Reg OT DC/DC regulator - - - - - OFF Linear regulator OFF OFF - - OFF - Op amps and OC comp OFF OFF - Block HSU, HSV, HSW output LOW LSU, LSV, LSW output LOW LOW LOW - - - LOW (1) LOW (1), (2) - - LOW (1) - - - Notes: (1)The N-channel of the gate driver is turned ON with all the available supply voltage, refer to Figure 5: "Gate drivers' outputs characteristics in UVLO conditions". (2)Only the high-side gate driver in which the UVLO condition is detected (e.g. UVLO on VBOOTU causes the HSU turning off). Figure 5: Gate drivers' outputs characteristics in UVLO conditions ILVG/HVG (mA) 550 500 Vcc = 6 to 12 V 450 Vcc = 5 V 400 350 300 Vcc = 4 V 250 200 150 Vcc = 3 V 100 Vcc = 2 V Vcc = 1 V Vcc = 0 V Vcc = VREG for LS rails 50 Vcc = VBOOT -VOUT for HS rails 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 DocID030766 Rev 2.0 4.0 4.5 VLVG/HVG (V) 21/41 Device description 6.1.1 STSPIN32F0A UVLO on supply voltages The STSPIN32F0A device provides UVLO protections on all power supplies. The device enters into the undervoltage condition when the power supply voltage falls below the off threshold voltage and expires when the motor supply voltage goes over the on threshold voltage. Table 9: "UVLO and OT protection management" shows the UVLO protection management: which blocks are switched off after an UVLO event. Figure 6: Power-up and power-down sequence 13 V typ. VMOn PWR_OK PWR_OK VM The DC/DC Reg stops to work The actualVDD voltage falls to 0V discharging the output capacitan ce VDDOn VDD tss The Lin Reg stops to work The actualVREG voltage falls to 0V discharging the output capacitan ce VREG 6.1.2 Thermal protection The device embeds an overtemperature shut-down protection. The thermal sensors are placed next to the DC/DC and linear regulator blocks. When the OT protection is triggered the correspondent block is switched off, the thermal shut-down condition only expires when the temperature goes below the “TSD - Thys” temperature (auto-restart). Table 9: "UVLO and OT protection management" shows the thermal protection management which blocks are switched off after an overtemperature event. 6.2 DC/DC buck regulator The internal DC/DC buck converter provides the 3.3 V supply voltage suitable to supply the MCU and other external devices. The regulator operates in the discontinuous current mode (DCM). A soft-start function with fixed start-up time is implemented to minimize the inrush current at the start-up, refer to Figure 8: "Soft-start timing". An overcurrent and short-circuit protection is provided. If the failure event occurs on the SW pin and the IOVC threshold is reached the regulator is latched off. To restart the DC/DC regulator a power-down and power-up cycle of device supply voltage (VM) is mandatory. 22/41 DocID030766 Rev 2.0 STSPIN32F0A Device description If the failure event occurs on the regulator output (VDDA pin) and the voltage goes below the UVLO threshold (VDDOff), the regulator restarts with a new soft-start sequence until the OC condition is removed. In this case the current in the coil is limited by ISW.peak. The DC/DC regulator embeds a thermal protection as described in Section 6.1.2: "Thermal protection". Figure 7: DC/DC buck regulator topology VM LSW To MCU C VDDA VDDA SW VM VM 3.3 V Co ntrol DC/DC buck conv. AM039986 Figure 8: Soft-start timing VDDA [V] 3.3 4.5 t [ms] tSS 6.2.1 External optional 3.3 V supply voltage It is possible provide externally the 3.3 V supply voltage directly on the VDDA pin. In this case, there are two possible configurations: 1. 2. The SW pin floating or shorted to VM: in this case the internal power switch of the DC/DC converter continues to switch on/off according to the internal clock The SW pin shorted to GND or VDD: in this case the internal power switch detects a short-circuit and it is latched off. DocID030766 Rev 2.0 23/41 Device description STSPIN32F0A It is not allowed to apply VDD voltage externally in case of VM < VDD. 6.3 Linear regulator The internal 12 V linear regulator is a LDO regulator providing the supply voltage for the gate drivers section. An external capacitor connected to the VREG12 pin is required. Figure 9: Linear regulator block diagram C REG VREG12 VM 12 V LIN regulator VREG12 When the VM voltage is below to 12 V, the VM pin and the linear regulator output can be shorted together providing the gate driver supply externally. The linear regulator embeds a thermal protection as described in Section 6.1.2: "Thermal protection". 24/41 DocID030766 Rev 2.0 STSPIN32F0A Device description Figure 10: Linear regulator output characteristics VM [V] 45 13 7.5 7.2 t VREG12 [V] 12 t The linear regulator is designed to supply the internal circuitry only and must not be used to supply external components. 6.4 Standby mode The device is forced into the standby mode to reduce power consumption forcing both the OC_TH_STBY1 and OC_TH_STBY2 analog IC inputs low (see Table 12: "OC threshold values"). When the standby mode is set the analog IC is put into the low consumption mode after a tsleep time, in particular: • • • • The linear regulator is switched off All the output drivers are forced low (external power switches turned off) Op amps and comparators disabled The DC/DC regulator remains operative. When the device exits from the standby mode a set time is necessary to recover a proper value of the 12 V internal regulator. This set time is strictly dependent by the capacitor connected on the VREG12 pin and can be calculated with Equation 1. DocID030766 Rev 2.0 25/41 Device description STSPIN32F0A Figure 11: “Standby to normal” operation timing (CREG = 1 µF) Equation 1 𝑡𝑡𝑅𝑅𝑅𝑅𝑅𝑅 = 6.5 Gate drivers 𝐶𝐶𝑅𝑅𝑅𝑅𝑅𝑅 ∙ 𝑉𝑉𝑅𝑅𝑅𝑅𝑅𝑅12 𝐼𝐼𝑅𝑅𝑅𝑅𝑅𝑅12,𝑙𝑙𝑙𝑙𝑙𝑙 The STSPIN32F0A device integrates a triple half-bridge gate driver able to drive N-channel power MOSFETs or IGBTs. The high-side section is supplied by a bootstrapped voltage technique with an integrated bootstrap diode. All the input lines (refer to Figure 2: "Analog IC block diagram") are connected to a pull-down resistor (60 kΩ typical value) to guarantee the low logic level during the device start-up. The high- and low-side outputs of same half-bridge cannot be simultaneously driven high thanks to an integrated interlocking function. All the input lines of the analog IC have an internal pull-down to guarantee the low logic level during the device start-up and when the MCU lines are not present. 26/41 DocID030766 Rev 2.0 STSPIN32F0A 6.6 Device description Microcontroller unit The integrated MCU is the STM32F031C6 with following main characteristics: • • • • • • • • • • Core: ARM® 32-bit Cortex™-M0 CPU, frequency up to 48 MHz Memories: 4kB of SRAM, 32 kB of Flash memory CRC calculation unit Up to 16 fast I/Os Advanced-control timer dedicated for PWM generation Up to 5 general purpose timers 12-bit ADC (up to 9 channels) Communication interfaces: I2C, USART, SPI Serial wire debug (SWD) Extended temperature range: -40 to 125 °C For more details refer to the STM32F031C6 datasheet on www.st.com 6.6.1 Memories and boot mode The device has the following features: • • 4 Kbytes of the embedded SRAM accessed (read/write) at CPU clock speed with 0 wait states and featuring embedded parity checking with an exception generation for fail-critical applications. The non-volatile memory is divided into two arrays: − 32 Kbytes of the embedded Flash memory for programs and data − Option bytes The option bytes are used to write-protect the memory (with 4 KB granularity) and/or readout-protect the whole memory with the following options: • • • Level 0: no readout protection Level 1: memory readout protection, the Flash memory cannot be read from or written to if either debug features are connected or the boot in the RAM is selected Level 2: chip readout protection, debug features (Cortex-M0 serial wire) and the boot in the RAM selection disabled. At startup the BOOT0 pin and the boot selector option bit are used to select one of the three boot options: • • • Boot from user Flash memory Boot from system memory Boot from embedded SRAM The boot loader is located in the system memory. It is used to reprogram the Flash memory by using USART on pins PA14/PA15. The main Flash memory is aliased in the boot memory space (0x00000000), but still accessible from its original memory space (0x08000000). In other words, the Flash memory contents can be accessed starting from the address 0x00000000 or 0x08000000. 6.6.2 Power management The VDD pin is the power supply for the I/Os and the internal regulator. The VDDA pin is the power supply for the ADC, reset blocks, RCs and PLL. The VDDA voltage can be generated through the internal DC/DC buck converter, otherwise it is possible to provide externally the supply voltage directly on the VDDA pin. DocID030766 Rev 2.0 27/41 Device description STSPIN32F0A The VDDA voltage level must be always greater or equal to the VDD voltage level and must be established first. The MCU has integrated power-on reset (POR) and power-down reset (PDR) circuits. They are always active, and ensure proper operation above a threshold of 2 V. The device remains in the reset mode when the monitored supply voltage is below a specified threshold. • • The POR monitors only the VDD supply voltage. During the startup phase it is required that VDDA should arrive first and be greater than or equal to VDD. The PDR monitors both the VDD and VDDA supply voltages, however the VDDA power supply supervisor can be disabled (by programming a dedicated option bit) to reduce the power consumption if the application design ensures that VDDA is higher than or equal to VDD. The device features an embedded programmable voltage detector (PVD) that monitors the VDD power supply and compares it to the VPVD threshold. An interrupt can be generated when VDD drops below the VPVD threshold and/or when VDD is higher than the VPVD threshold. The interrupt service routine can then generate a warning message and/or put the MCU into a safe state. The PVD is enabled by software. The MCU supports three low-power modes to achieve the best compromise between lowpower consumption, short start-up time and available wake-up sources: • • • • • • • • • 6.6.3 Sleep mode In the sleep mode, only the CPU is stopped. All peripherals continue to operate and can wake-up the CPU when an interrupt/event occurs. Stop mode The stop mode achieves very low-power consumption while retaining the content of the SRAM and registers. All clocks in the 1.8 V domain are stopped, the PLL, the HSI RC and the HSE crystal oscillators are disabled. The voltage regulator can also be put either in the normal or in the low-power mode. The device can be woken-up from the stop mode by any of the EXTI lines (one of the 16 external lines, the PVD output, RTC, I2C1 or USART1). Standby mode The standby mode is used to achieve the lowest power consumption. The internal voltage regulator is switched off so that the entire 1.8 V domain is powered off. The PLL, the HSI RC and the HSE crystal oscillators are also switched off. After entering the standby mode, SRAM and register contents are lost except for registers in the RTC domain and standby circuitry. The device exits the standby mode when an external reset (NRST pin), an IWDG reset, a rising edge on the WKUP pins, or an RTC event occurs. High-speed external clock source The high-speed external (HSE) clock can be generated from the external clock signal or supplied with a 4 to 32 MHz crystal/ceramic resonator oscillator (see Figure 13: "Typical application with 8 MHz crystal"). The external clock signal has to respect the I/O characteristics and follows the recommended clock input waveform (refer to Figure 12: "HSE clock source timing diagram"). 28/41 DocID030766 Rev 2.0 STSPIN32F0A Device description Figure 12: HSE clock source timing diagram Figure 13: Typical application with 8 MHz crystal In the application, the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and startup stabilization time. The REXT value depends on the crystal characteristics (refer to the crystal resonator manufacturer for more details on them). 6.6.4 Advanced-control timer (TIM1) The advanced-control timer (TIM1) can be seen as a three-phase PWM multiplexed on six channels. It has complementary PWM outputs with programmable inserted deadtimes. This timer is used to generate the PWM signal for the three half-bridge gate drivers as shown in Table 10: "TIM1 channel configuration". Table 10: TIM1 channel configuration MCU I/O Analog IC input TIM1 channel PB13 LS1 TIM1_CH1N PB14 LS2 TIM1_CH2N PB15 LS3 TIM1_CH3N PA8 HS1 TIM1_CH1 PA9 HS2 TIM1_CH2 PA10 HS3 TIM1_CH3 DocID030766 Rev 2.0 29/41 Device description 6.7 STSPIN32F0A Test mode A dedicated pin TESTMODE is available to enter into the test mode. In the application, the TESTMODE pin should be shorted to GND in order not to enter the test mode inadvertently. 6.8 Operational amplifiers The device integrates three rail-to-rail operational amplifiers suitable for signal conditioning, in particular for current sensing. The operational amplifiers provide a rail-to-rail output stage with fast recovery in the saturation condition. The output stage saturation happens in linear applications when a high amplitude input signal occurs and causes the output of the operational amplifier to move outside its real capabilities. Figure 14: Operational amplifiers To input ADC OPxO I NN OP xN I NP 6.9 OPAMP OP xP Comparator A comparator is available to perform an overcurrent protection. The OC Comp pin can be connected to the shunt resistor to monitor the load current, the internal OC threshold can be set via MCU (PF6 and PF7 port, see Table 12: "OC threshold values"). When an OC event is triggered, the OC comparator output signals the OC event to the PB12 and PA12 inputs of MCU (BKIN and ETR). 30/41 DocID030766 Rev 2.0 STSPIN32F0A Device description Depending on the status of the OC_SEL signal (see Table 11: "OC protection selection") the OC event is acting directly on the control logic of the gate driver switching off all highside gate outputs, and consequently the external high-side power switches. Figure 15: Comparator VM To PB12 and PA12 of MCU and control logic OC_COMP COMP OC th Rshunt Table 11: OC protection selection OC_SEL (PA11) Function 0 OC comparator output signal is visible only to MCU (default) 1 OC comparator output signal is visible to MCU and also acts on gate driver control logic Table 12: OC threshold values OC_TH_STBY2 (PF6) OC_TH_STBY1 (PF7) OC threshold [mV] 0 0 N.A. 0 1 100 - 1 0 250 - 1 1 500 - Note Standby mode (see Section 6.4: "Standby mode") When the overcurrent condition disappears, the latched overcurrent signal is released only after all the high-side outputs are kept low for at least tOCrelease time. (Refer to Figure 16: "Driver logic overcurrent management signals"). DocID030766 Rev 2.0 31/41 Device description STSPIN32F0A Figure 16: Driver logic overcurrent management signals t > OCdeglitch tCPD tCPD t < OCdeglitch Whenthe OCdisappears, the latched OCsignal isreleased after the first HS_inputrising edge OC_COMP PB12 t > OCrelease OC_blk_n (latched signal) HS1 HS2 HS3 32/41 DocID030766 Rev 2.0 STSPIN32F0A 6.10 Device description ESD protection strategy Figure 17: ESD protection strategy VDD(3.3 V) AnalogI/O DigitalI/O GND VM(45 VMAX.) VBOOT POWER BOOTSTRAP DIODE Linear reg. POWER HVU/V/W ESD active POWER clamp POWER REG SW OUT POWER ESD active High-side driver(X3) LVU/V/W clamp ESD active clamp POWER GND Low- sidedriver(X3) BELOW GND DocID030766 Rev 2.0 33/41 Application example 7 STSPIN32F0A Application example Figure 18: "Application example" shows an application example using the STSPIN32F0A device to drive a three-phase motor with triple shunt configuration and field oriented control algorithm. The others features implemented are: • • • • • • • • • • 34/41 VDD (3.3 V) power supply internally generated via DC/DC regulator VREG12 (12 V) power supply internally generated via LDO linear regulator USART serial interface (PB6 and PB7) Serial wire debug ports (PA13_SWD_IO, PA14_SWD_CLK) Ready and alarm lines (PF0, PF1) Reset dedicated pin Overcurrent protection using internal comparator Current sensing using internal operational amplifiers and ADCs (PA0, PA1, PA2) Bus voltage compensation using internal ADC (PA3) Application temperature monitoring using internal ADC (PA4) DocID030766 Rev 2.0 VDD DocID030766 Rev 2.0 fromOpAmps outputs RBUS2 RBUS1 VM CDDA CRST CBUS PA3 PA2 PA1 PA0 VDDA NRST PF0 PF1 OP2N OP2P OP3P OP2O STSPIN32F0A OP3N SWDCLKPA14 BOOT0 VDD PB1 PA7 PA6 PA5 PA4 toPA0,PA1,PA2 MCUGPIO Signals condioning OP1P OP1N OP1O RTH CVM CREG CVDD U,V,Wphases currentsensing D1 OC_COMP CTH + SW NTC CDD VM VDD CLP VREG12V VDD RESERVED Alarm RBOOT SWDIO PA13 Ready CDD VDD L1 VBOOTU RLP RGL RGH CBOOT toOpAmpsinput andOC_COMP LS OUT HS VBOOT VM LS HS 3xPowerHalf-Bridge Currentsensing feedback LSW OUTW HSW VBOOTW LSV OUTV HSV VBOOTV LSU OUTU HSU M THREE-PHASE MOTOR STSPIN32F0A Figure 18: Application example Application example OP3O GND PA15 TESTMODE USART _RX PB7 USART _TX PB6 35/41 Package information 8 STSPIN32F0A Package information In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. A customized VFQFPN48 7 x 7 package is proposed. A smaller EPAD, internally connected to the ground pin, is desired to place through holes on the bottom of the package. Lead plating is Nickel/Palladium/Gold (Ni/Pd/Au). 36/41 DocID030766 Rev 2.0 STSPIN32F0A 8.1 Package information VFQFPN48 7 x 7 package information Figure 19: VFQFPN48 7 x 7 x 1.0 - 48L, pitch 0.5 package outline DocID030766 Rev 2.0 37/41 Package information STSPIN32F0A Table 13: VFQFPN48 7 x 7 x 1.0 - 48L, pitch 0.5 - package mechanical data Dimensions (mm) Symbol Min. Typ. Max. A 0.90 0.95 1.00 A1 0.0 - 0.05 A2 0.75 A3 0.203 b 0.20 0.25 0.30 D 6.90 7.00 7.10 E 6.90 7.00 7.10 e 0.50 D2 2.50 2.60 2.70 E2 2.50 2.60 2.70 K L 1.80 0.30 0.40 Figure 20: VFQFPN48 7 x 7 x 1.0 - 48L, pitch 0.5 - suggested footprint 38/41 DocID030766 Rev 2.0 0.50 STSPIN32F0A 9 Ordering information Ordering information Table 14: Order codes Order code Package Packaging STSPIN32F0A VFQFPN 7 x 7 x 1.0 - 48L Tray STSPIN32F0ATR VFQFPN 7 x 7 x 1.0 - 48L Tape and reel DocID030766 Rev 2.0 39/41 Revision history 10 STSPIN32F0A Revision history Table 15: Document revision history 40/41 Date Revision Changes 21-Jul-2017 1 Initial release. 21-Sep-2017 2 Updated document status to Production data. Added availability FW boot loader in whole document. Minor modifications throughout document. DocID030766 Rev 2.0 STSPIN32F0A IMPORTANT NOTICE – PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement. Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers’ products. No license, express or implied, to any intellectual property right is granted by ST herein. Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners. Information in this document supersedes and replaces information previously supplied in any prior versions of this document. © 2017 STMicroelectronics – All rights reserved DocID030766 Rev 2.0 41/41