STSPIN32F0B

STSPIN32F0B Datasheet Advanced single shunt BLDC controller with embedded STM32 MCU Features • • Extended operating voltage from 6.7 to 45 V Three-phase gate drivers – 600 mA sink/source – Integrated bootstrap diodes – Cross-conduction prevention • 32-bit ARM® Cortex®-M0 core: – Up to 48 MHz clock frequency – 4-kByte SRAM with HW parity – 32-kByte Flash memory with option bytes used for write/readout protection – Bootloader FW available 3.3. V DC/DC buck converter regulator with overcurrent, short-circuit, and thermal protection 12 V LDO linear regulator with thermal protection 20 general-purpose I/O ports (GPIO) 5 general-purpose timers 12-bit ADC converter (up to 9 channels) • • • • • Product status link • • • • • I2C, USART and SPI interfaces One rail-to-rail operational amplifier for signal conditioning Comparator for overcurrent protection with programmable threshold Standby mode for low power consumption UVLO protection on each power supply: – VM, VDD, VREG and VBOOTx • • On-chip debug support via SWD Extended temperature range: -40 to +125 °C STSPIN32F0B Product summary Order Codes STSPIN32F0B Tray STSPIN32F0BTR Tape and Reel Marking STSPIN32F0B Package VFQFPN48 7x7x1mm Applications • • • • Power tools FANs and pumps Industrial automation Battery powered home appliances DS12907 - Rev 1 - February 2019 For further information contact your local STMicroelectronics sales office. www.st.com STSPIN32F0B Description 1 Description The STSPIN32F0B is a System-In-Package providing an integrated solution suitable for driving three-phase brushless motors using different driving modes. It embeds a triple half-bridge gate driver able to drive power MOSFETs with a current capability of 600 mA (sink and source). The high- and low-side switches of same half-bridge cannot be simultaneously driven high thanks to an integrated interlocking function. An internal DC/DC buck converter provides the 3.3 V voltage suitable to supply both the MCU and external components. An internal LDO linear regulator provides the supply voltage for gate drivers. The integrated operational amplifier is available for the signal conditioning, e.g. the current sensing across the shunt resistor. A comparator with a programmable threshold is integrated to perform the overcurrent protection. The integrated MCU (STM32F031C6 with extended temperature range, suffix 7 version) allows performing fieldoriented control, the 6-step sensorless and other advanced driving algorithms. It has the write-protection and read-protection feature for the embedded Flash memory to protect against unwanted writing and/or reading. It is possible to download the firmware on-the-field through the serial interface thanks to the embedded bootloader. The STSPIN32F0B device also features overtemperature and undervoltage lockout protections and can be put in the standby mode to reduce the power consumption. The device provides 20 general-purpose I/O ports (GPIO) with the 5 V tolerant capability, one 12-bit analog-to-digital converter with up to 9 channels performing conversions in a single-shot or scan modes, 5 synchronizable general-purpose timers and supports an easy to use debugging serial interface (SWD). DS12907 - Rev 1 page 2/36 STSPIN32F0B Block diagrams 2 Block diagrams OUTW LSW LS HS VREG12 LS VREG12 VBOOTW HSW LSV OUTV VREG12 VREG12 VREG12 Control Logic Gate Driver COMP OC_COMP ADJ REF 6 2 12V VREG VREG 12V VM HSV VBOOTV LS HS LSU OUTU VREG12 HSU VREG12 HS VBOOTU Figure 2. STSPIN32F0B System-In-Package block diagram to VDDA OP1P OP1N OP1O OC_SEL OC comp threshold select 3.3V VM VM OPAMP DC/DC Buck conv control SW PA13_SWD_IO 3.3V RESERVED RESERVED RESERVED GND PF7 PF6 PA13 PA12 PA11 PA10 PA9 PA8 PB15 PB14 PB13 PB12 connected to EPAD PA14_SWD_CLK TEST MODE PB6 PB7 BOOT0 VDD VSS STM32F031 PA14 PA15 PB3 PB4 PB5 PB6 PB7 BOOT0 PB8 PB9 VSS PA15 PB11 PB10 PB2 PB1 PB0 PA7 PA6 PA5 PA4 VDD VBAT PB8 PA5 PA4 VDDA PA0 PA1 PA2 PA3 PC13 PC14 PC15 PF0 PF1 NRST VSSA PB9 PB1 PA7 PA6 DS12907 - Rev 1 PA3 PA2 PA1 PA0 VDDA PF1 NRST PC15 PF0 PC14 VDD page 3/36 STSPIN32F0B Block diagrams Figure 3. Analog IC block diagram VREG 12V SW VM VDD_3V3 PA13_SWD_IO RESERVED RESERVED RESERVED 3.3V VM VM 12V VREG VREG12 VREG12 VBOOTU HS control SWDIO_INT VREG12 DC/DC Buck conv OC_TH_STBY1 OC_TH_STBY2 OC_COMP_INT2 OC_SEL HS3 HS2 HS1 LS3 LS2 LS1 2 OC comp threshold select LS HSU OUTU LSU VREG12 OC_SEL VBOOTV Control Logic Gate Driver 6 HS HSV OUTV VREG12 LS OC_COMP_INT1 LSV VREG12 VBOOTW HS 3.3V VDD OUTW VREG12 LS LSW ADJ REF OPAMP OC Comp OP1P OP1N OP1O DS12907 - Rev 1 COMP TEST MODE GND HSW page 4/36 STSPIN32F0B 3 Electrical data 3.1 Absolute maximum ratings Stresses above the absolute maximum ratings listed in Table 1. Absolute maximum ratings may cause permanent damage to the device. Exposure to maximum rating conditions for extended periods may affect device reliability. Table 1. Absolute maximum ratings Symbol VM VREG12 Parameter Power supply voltage Linear regulator output and gate driver supply voltage Test condition Value Unit - -0.3 to 48 V VREG12 shorted to VM 15 V VOPP Op amp positive input voltage - -0.2 to VDD + 0.2 V VOPN Op amp negative input voltage - -0.2 to VDD + 0.2 V VCP Comparator input voltage - -2 to 2 V VHS High-side gate output voltage - VOUT - 0.3 to VBOOT + 0.3 V VLS Low-side gate output voltage - -0.3 to VREG12 + 0.3 V VBOOT Bootstrap voltage - VOUT Output voltage (OUTU, OUTV, OUTW) - dVOUT/dt Output slew rate Max. (VOUT - 0.3 or -0.3) to min. ('VOUT + VREG12 + 0.3' or 60) TTa type VIO IIO ΣIIO VDD VDDA Tstg Tj MCU logic input -2 to VM + 2 V ± 10 V/ns - voltage(1) FT, FTf (1) type(1) V -0.3 to 4 -0.3 to VDD + 4 (2) V BOOT0 0 to 9.0 (1) -25 to 25 mA , (3) (1) -80 to 80 mA MCU digital supply voltage (1) -0.3 to 4 V MCU analog supply voltage (1) -0.3 to 4 V Storage temperature - -55 to 150 °C Operating junction temperature - -40 to 150 °C MCU I/O output current MCU I/O total output current 1. See Table 15 Voltage characteristics in the STM32F031C6 datasheet (suffix 7 version). 2. Valid only if the internal pull-up/pull-down resistors are disabled. If internal the pull-up or pull-down resistor is enabled, the maximum limit is 4 V. 3. If the MCU supply voltage is provided by an integrated DC/DC regulator, the application current consumption is limited at IDDA,max value (see Table 5. Electrical characteristics). DS12907 - Rev 1 page 5/36 STSPIN32F0B ESD protections 3.2 ESD protections Table 2. ESD protection ratings Symbol 3.3 Parameter Test condition Conforming to ANSI/ESDA/JEDEC HBM Human body model CDM Charge device model JS-001-2014 Conforming to ANSI/ESDA/JEDEC JS-002-2014 Class Value Unit H2 2 kV C2 750 V Recommended operating conditions Table 3. Recommended operating conditions Symbol VM dVM/dt Parameter Test condition Min. Typ. Max. Unit - 6.7 (1) - 45 V VM = 45 V - - 0.75 V/µs Power supply voltage Power supply voltage slope VDDA DC/DC regulator output voltage - - 3.3 - V LSW Output inductance - - 22 - µH CDDA Output capacitance - 47 - - µF ESRDDA Output capacitor ESR - - - 200 mΩ VREG12 Linear regulator output and gate driver supply voltage 13 < VM < 45 V - 12 - Shorted to VM 6.7(1) - 15 - 1 10 - µF CREG ESRREG Load capacitance - - - 1.2 Ω VBO Floating supply voltage (2) - - VREG12 - 1 15 V VCP Comparator input voltage - 0 - 1 V Analog IC -40 - 125 °C MCU (3) -40 - 125 °C Tj ESR load capacitance V Operating junction temperature 1. UVLO threshold VMOn_max. 2. VBO = VBOOT - VOUT. 3. See the STM32F031C6 datasheet (suffix 7 version). 3.4 Thermal data Thermal values are calculated by simulation with the following boundary conditions: 2s2p board as per the std. JEDEC (JESD51-7) in natural convection, board dimensions: 114.3 x 76.2 x 1.6 mm, ambient temperature: 25 °C. Table 4. Thermal data DS12907 - Rev 1 Symbol Parameter Value Unit Rth (JA) Thermal resistance junction to ambient 45.6 °C/W page 6/36 STSPIN32F0B Electrical characteristics 4 Electrical characteristics Testing conditions: VM = 15 V; VDD = 3.3 V, unless otherwise specified. Typical values are tested at Tj = 25 °C, minimum and maximum values are guaranteed by thermal characterization in the temperature range of -40 to 125 °C, unless otherwise specified. Table 5. Electrical characteristics Symbol Parameter Test condition Min. Typ. Max. Unit Power supply and standby mode VM = 45 V; VDD = 3.5 V externally supplied IM VM current consumption Standby PF7 = '0' PF6 = '0' VM = 45 V; VDD = 3.5 V externally supplied - 2 2.6 mA - 880 1100 µA VMOn VM UVLO turn-on threshold VM rising from 0 V 6.0 6.3 6.6 V VMOff VM UVLO turn-off threshold VM falling from 8 V 5.8 7.1 6.4 V VMHys VM UVLO threshold hysteresis - - 0.2 - V VDD = 3.5 V externally supplied - 2.5 5 - 2.5 5 - 400 550 - 80 125 IDD VDD current consumption Standby PF7 = '0' PF6 = '0' VDD = 3.5 V externally supplied VDD = 3.5 V externally supplied IDDA VDDA current consumption Standby PF7 = '0' PF6 = '0' VDD = 3.5 V externally supplied mA µA VDDOn VDD UVLO turn-on threshold VDD rising from 0 V 2.5 2.65 2.8 V VDDOff VDD UVLO turn-off threshold VDD falling from 3.3 V 2.2 2.35 2.5 V VDDHys VDD UVLO threshold hysteresis - - 0.3 - V - 800 1200 VREG = 13 V externally supplied, VM = 45 V; IREG12 VREG current consumption no commutation Standby PF7 = '0' PF6 = '0' VREG = 13 V externally supplied µA - 800 1200 VREG12On VREG12 UVLO turn-on threshold VREG12 rising from 0 V 6.0 6.3 6.6 V VREG12Off VREG12 UVLO turn-off threshold VREG12 falling from 8 V 5.8 6.1 6.4 V VREG12Hys VREG12 UVLO threshold hysteresis - - 0.25 - V IBOOT VBO current consumption HS on, VBO = 13 V - 200 290 µA VBOOn VBO UVLO turn-on threshold VBO rising from 0 V 5.5 5.8 6.1 V VBOOff VBOUVLO turn-off threshold VBO falling from 8 V 5.3 5.6 5.9 V VBOHys VBO UVLO threshold hysteresis - - 0.15 - V Standby set time - - - 1 µs - 5.6 6 6.4 V 3.09 3.3 3.5 V - - 70 mA tsleep DC/DC switching regulator VPWR_OK Power good voltage VDDA Average output voltage IDDA Output current DS12907 - Rev 1 DC; MCU current consumption included page 7/36 STSPIN32F0B Electrical characteristics Symbol fSW Parameter Maximum SW switching frequency ISW,peak IOVC tSS Open loop, VDDA floating Min. Typ. Max. Unit - 200 330 kHz ISW = 200 mA - 1.4 - Ω Efficiency VM = 8 V; IDDA = IDDA,max - 80 - % Peak current threshold - - 320 - mA Latched overcurrent threshold - - 1 - A Soft-start time - 2.5 5 7.5 ms 11.4 12 12.6 V - 200 400 mV VM = 13 V 20 - 40 mA TJ = 25 °C 400 600 - mA Full temperature range 350 - - mA Input lines pull-down resistor - 30 60 95 kΩ Input-to-output propagation delay (4) - - 20 40 ns Delay matching, HS and LS turn-on/off (5) - - 10 20 ns Bootstrap diode ON resistance - - 120 240 Ω - -0.1 - VDD + 0.1 V Vout = 1.65; Tj = 25 °C - 1 6 mV Vout = 1.65; full temp. range - - 7 mV Vout = 1.65 - - 100 pA - - 100 pA RSWDS(ON) Switch ON resistance η Test condition ISW = 100 mA Linear regulator VREG12 Linear regulator output and gate driver supply voltage VREG12,drop Drop voltage IREG12,lim Linear regulator current limit VM = 13 ÷ 45 V (3) IO = 10 mA VM = 8 ÷ 11 V, IO = 10 mA Gate drivers ISI ISO RPDin ton toff MT RDS_diode Maximum sink/source current capabilities Operational amplifier Vicm Input common mode voltage range VOPio Input offset voltage IOPio Input offset current IOPib Input bias current Common mode rejection ratio 0 to 3.3 V; Vout = 1.65 V 70 90 - dB Open loop gain RL = 10 kΩ; Vout = 1.65 - 90 - dB VDD - VOH High level output voltage RL = 10 kΩ - 15 40 mV VOL Low level output voltage RL = 10 kΩ - 15 40 mV Vout = 3.3 V; Tj = 25 °C 18 - - mA Vout = 3.3 V; full temp. range 16 - - Vout = 0 V; Tj = 25 °C 18 - - Vout = 0 V; full temp. range 16 - - 10 18 - MHz - 4 - V/V CMRR AOL Sink output current IOUT Source output current GBP Gain bandwidth product Gain Minimum gain for stability DS12907 - Rev 1 RL = 2 kΩ; CL = 100 pF Vout = 1.65 Phase margin = 45° 0.2 V < Vout < VDD - 0.2 mA page 8/36 STSPIN32F0B Electrical characteristics Symbol SR Parameter Test condition RL = 2 kΩ; CL = 100 pF Slew rate Min. Typ. Max. Unit - 10 - V/µs PF6 = '0' PF7 = '1' 90 100 120 mV PF6 = '1' PF7 =' 0' 235 255 275 mV PF6 = '1' PF7 = '1' 465 505 545 mV - 80 120 ns 35 50 - ns - - 20 ns Vin 1 to 2 V step OC comparator OCth tCPD Overcurrent threshold OCth = 0.5 V; Comparator propagation delay OC_Comp: voltage step from 0 to 1 V tOCdeglitch Comparator input deglitch filter time tOCrelease Minimum overcurrent latch release pulse width Thermal protection TSD Thermal shut-down temperature - 130 140 150 °C Thys Thermal shut-down hysteresis - 20 30 40 °C 1. The current consumption depends on the firmware loaded in the microcontroller. 2. Using the 47 μF capacitor (APXG250ARA470MF61G), 22 μH inductor (MLF1608C220KTA00), and diode 1N4448TR. 3. With 11 < VM < 13 V the linear output voltage can be VREG12 or 'VM-VREG12,drop' depending on the linear regulator is already turned-on or not. 4. See Figure 4. Gate drivers timing 5. MT = max. (|ton(LVG) - toff(LVG)|, |ton(HVG) - toff(HVG)|, |toff(LVG) - ton(HVG)|, |toff(HVG) - ton(LVG)|). 6. Guaranteed by design. 7. Guaranteed by IOUT test. 8. See Figure 17. Driver logic overcurrent management signals. Figure 4. Gate drivers timing LS1 (2) (3) HS1 (2) (3) 50% 50% 90% LSU(V)(W) HSU(V)(W) DS12907 - Rev 1 10% ton toff page 9/36 STSPIN32F0B Pin description 5 Pin description VDD RESERVED PB9 PB8 GND RESERVED BOOT0 PB7 PB6 PA15 PA14_SWD_CLK PA13_SWD_IO Figure 5. STSPIN32F0B SiP pin connection (top view) 48 47 46 45 44 43 42 41 40 39 38 37 PC14 1 36 LSU PC15 2 35 VBOOTU RESERVED 3 34 OUTU PF0 4 33 HSU PF1 5 32 LSV VREG12 6 31 VBOOTV NRST 7 30 OUTV VM 8 29 HSV SW 9 28 LSW VDDA 10 27 VBOOTW PA0 11 26 OUTW PA1 12 25 HSW 15 16 17 18 19 20 21 22 PA3 PA4 PA5 PA6 PA7 PB1 TESTMODE OP1O OP1N 23 24 OC_Comp 14 OP1P 13 PA2 EPAD Table 6. STSPIN32F0B SiP pin description DS12907 - Rev 1 No. Name Type 1 PC14 GPIO MCU PC14 2 PC15 GPIO MCU PC15 3 RESERVED - 4 PF0 GPIO MCU PF0 5 PF1 GPIO MCU PF1 6 VREG12 Power 12 V linear regulator output 7 NRST GPIO MCU reset pin 8 VM Power Power supply voltage (bus voltage) 9 SW Analog out 10 VDDA Power MCU analog power supply voltage 11 PA0 GPIO MCU PA0 Function Reserved for test mode 3.3 V DC/DC buck regulator switching node page 10/36 STSPIN32F0B Pin description DS12907 - Rev 1 No. Name Type Function 12 PA1 GPIO MCU PA1 13 PA2 GPIO MCU PA2 14 PA3 GPIO MCU PA3 15 PA4 GPIO MCU PA4 16 PA5 GPIO MCU PA5 17 PA6 GPIO MCU PA6 18 PA7 GPIO MCU PA7 19 PB1 GPIO MCU PB1 20 TESTMODE Digital In 21 OP1O Analog out 22 OP1N Analog in Operational amplifier inverting input 23 OP1P Analog in Operational amplifier non-inverting input 24 OC_COMP Analog in Overcurrent comparator input 25 HSW Analog out 26 OUTW Power W phase high-side (floating) common voltage 27 VBOOTW Power W phase bootstrap supply voltage 28 LSW Analog out W phase low-side driver output 29 HSV Analog out V phase high-side driver output 30 OUTV Power V phase high-side (floating) common voltage 31 VBOOTV Power V phase bootstrap supply voltage 32 LSV Analog out V phase low-side driver output 33 HSU Analog out U phase high-side driver output 34 OUTU Power U phase high-side (floating) common voltage 35 VBOOTU Power U phase bootstrap supply voltage 36 LSU Analog out 37 PA13_SWD_IO GPIO MCU PA13/SWDIO (system debug data via analog IC) 38 PA14_SWD_CLK GPIO MCU PA14/SWDCLK (system debug clock) 39 PA15 GPIO MCU PA15 40 PB6 GPIO MCU PB6 41 PB7 GPIO MCU PB7 42 BOOT0 Digital in 43 RESERVED - 44 GND Power Ground 45 PB8 GPIO MCU PB8 46 PB9 GPIO MCU PB9 47 RESERVED - 48 VDD Power MCU digital power supply EPAD Power Internally connected to ground Test mode input Operational amplifier output W phase high-side driver output U phase low-side driver output MCU BOOT0 Reserved for test mode (can be left floating in application) Reserved for test mode page 11/36 STSPIN32F0B Pin description Table 7. STSPIN32F0B MCU pad mapping MCU pad Type Analog IC pad Alternate and additional functions PC14 I/O - TC - OSC32_IN PC15 I/O - TC - OSC32_OUT PF0 I/O - FT - OSC_IN PF1 I/O - FT - OSC_OUT NRST I/O - RST - Device reset input / internal reset output (active low) VDDA S VDD_3V3 PA0 I/O - TTa - PA1 I/O - TTa - PA2 I/O - TTa - PA3 I/O - TTa - PA4 I/O - TTa - PA5 I/O - TTa - PA6 I/O - TTa - Analog power supply voltage TIM2_CH1_ETR, USART1_CTS ADC_IN0, RTC_TAMP2, WKUP1 TIM2_CH2, EVENTOUT, USART1_RTS ADC_IN1 TIM2_CH3, USART1_TX ADC_IN2 TIM2_CH4, USART1_RX ADC_IN3 SPI1_NSS, I2S1_WS, TIM14_CH1, USART1_CK ADC_IN4 SPI1_SCK, I2S1_CK, TIM2_CH1_ETR ADC_IN5 SPI1_MISO, I2S1_MCK, TIM3_CH1, TIM1_BKIN, TIM16_CH1, EVENTOUT ADC_IN6 PB1 I/O - TTa - PA7 I/O - TTa - TIM3_CH4, TIM14_CH1, TIM1_CH3N ADC_IN9 SPI1_MOSI, I2S1_SD, TIM3_CH2, TIM14_CH1, TIM1_CH1N, TIM17_CH1, EVENTOUT ADC_IN7 DS12907 - Rev 1 PB12 I/O - FT OC_COMP_INT TIM1_BKIN (1) PB13 I/O - FT LS1 TIM1_CH1N(1) PB14 I/O - FT LS2 TIM1_CH2N(1) PB15 I/O - FT LS3 TIM1_CH3N(1) PA8 I/O - FT HS1 TIM1_CH1(1) PA9 I/O - FTf HS2 TIM1_CH2(1) PA10 I/O - FTf HS3 TIM1_CH3 PA11 I/O - FT OC_SEL PA12 I/O - FT PA13_SWD_IO I/O - FT SWDIO_INT IR_OUT, SWDIO PF6 I/O - FTf OC_TH_STBY2 Push-pull output(1) PF7 I/O - FTf OC_TH_STBY1 Push-pull output(1) PA14_SWD_CLK I/O - FT - USART1_TX, SWCLK PA15 I/O - FT - SPI1_NSS, I2S1_WS, TIM2_CH_ETR, EVENTOUT, USART1_RX Push-pull output(1) OC_COMP_INT2 TIM1_ETR(1) page 12/36 STSPIN32F0B Pin description MCU pad Type Analog IC pad Alternate and additional functions PB6 I/O - FTf - I2C1_SCL, USART1_TX, TIM16_CH1N PB7 I/O - FTf - I2C1_SDA, USART1_RX, TIM17_CH1N PB8 I/O - FTf - I2C1_SCL, TIM16_CH1 PB9 I/O - FTf - I2C1_SDA, TIM17_CH1 VBAT, VDD S VDD VSS, VSSA S - Ground BOOT0 I - Boot memory selection PC15, PB0, PB2, PB10, PB11, PA15, PB3, PB4, PB5 - - Not connected Backup and digital power supply 1. The analog IC is designed to support these GPIOs configuration only. Different configuration could cause device malfunctioning. The GPIO input configuration without pull-up or pull-down is always allowed. Note: Each unused GPIO inside the SiP should be configured in the OUTPUT mode low level after the startup by software. Table 8. STSPIN32F0B analog IC pad description DS12907 - Rev 1 Pinout name Pad name Type Function PA13_SWD_IO SYS_SWDIO Digital I/O VDDA VDD_3V3 Power 3.3 V DC/DC buck regulator voltage output VM VM Power Power supply voltage (bus voltage) SW SW Analog out VREG12 VREG12 Power 12 V linear regulator output VBOOTU VBOOTU Power U phase bootstrap supply voltage HSU HSU Analog out OUTU OUTU Power LSU LSU Analog out VBOOTV VBOOTV Power HSV HSV Analog out OUTV OUTV Power LSV LSV Analog out VBOOTW VBOOTW Power System debug data (connected to the output through the analog IC) 3.3 V DC/DC buck regulator switching node U phase high-side driver output U phase high-side (floating) common voltage U phase low-side driver output V phase bootstrap supply voltage V phase high-side driver output V phase high-side (floating) common voltage V phase low-side driver output W phase bootstrap supply voltage HSW HSW Analog out OUTW OUTW Power W phase high-side driver output LSW LSW Analog out OC_Comp OC_COMP Analog in OP1P OP1P Analog out OP1N OP1N Analog in Op amp 1 inverting input OP1O OP1O Analog in Op amp 1 non-inverting input RESERVED RESERVED - Reserved for test mode RESERVED RESERVED - Reserved for test mode RESERVED RESERVED - Reserved for test mode GND GND Power W phase high-side (floating) common voltage W phase low-side driver output Overcurrent comparator input Op amp 1 output Ground page 13/36 STSPIN32F0B Pin description DS12907 - Rev 1 Pinout name Pad name Type Function TESTMODE TESTMODE Digital in - VDD Power - OC_COMP_INT Digital out OC comparator output - HS1 Digital in High-side input driver U - HS2 Digital in High-side input driver V - HS3 Digital in High-side input driver W - LS1 Digital in Low-side input driver U - LS2 Digital in Low-side input driver V - LS3 Digital in Low-side input driver W - OC_SEL Digital in OC protection selection - OC_COMP_INT2 Digital out OC comparator output - SWD_IO_INT Digital in System debug data (connected to the output through the analog IC) - OC_TH_STBY1 Digital in Overcurrent threshold selection and standby input 1 - OC_TH_STBY2 Digital in Overcurrent threshold selection and standby input 2 Test mode input MCU digital power supply page 14/36 STSPIN32F0B Device description 6 Device description The STSPIN32F0B is a System-In-Package providing an integrated solution suitable for driving the three-phase BLDC motors. 6.1 UVLO and thermal protections Table 9. UVLO and OT protection management summarizes the UVLO and OT protection management. Table 9. UVLO and OT protection management VM UVLO VDD UVLO VREG12 UVLO VBOOT UVLO Lin. Reg OT DC/DC Reg OT DC/DC regulator - - - - - OFF Linear regulator OFF OFF - - OFF - Op amps and OC comp OFF OFF - - - - - - - Block HSU, HSV, HSW output LOW LSU, LSV, LSW output LOW - LOW LOW (1) LOW, LOW LOW(1) - (2) (1) 1. The N-channel of the gate driver is turned ON with all the available supply voltage, refer to Figure 6. Gate drivers' outputs characteristics in UVLO conditions. 2. Only the high-side gate driver in which the UVLO condition is detected (e.g. UVLO on VBOOTU causes the HSU turning off). Figure 6. Gate drivers' outputs characteristics in UVLO conditions ILVG/HVG (mA) 550 500 Vcc = 6 to 12 V 450 Vcc = 5 V 400 350 300 Vcc = 4 V 250 200 150 Vcc = 3 V 100 Vcc = 2 V Vcc = 1 V Vcc = 0 V Vcc = VREG for LS rails 50 Vcc = VBOOT -VOUT for HS rails 0 0.5 DS12907 - Rev 1 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 VLVG/HVG (V) page 15/36 STSPIN32F0B DC/DC buck regulator 6.1.1 UVLO on supply voltages The STSPIN32F0B device provides UVLO protections on all power supplies. The device enters into the undervoltage condition when the power supply voltage falls below the off threshold voltage and expires when the motor supply voltage goes over the on threshold voltage. Table 9. UVLO and OT protection management shows the UVLO protection management: which blocks are switched off after an UVLO event. Figure 7. Power-up and power-down sequence 13 V typ. VMOn PWR_OK PWR_OK VM VDDOn VDD The DC/DC Reg stops to work The actualVDD voltage falls to 0V discharging the output capacitan ce tss The Lin Reg stops to work The actualVREG voltage falls to 0V discharging the output capacitan ce VREG 6.1.2 Thermal protection The device embeds an overtemperature shut-down protection. The thermal sensors are placed next to the DC/DC and linear regulator blocks. When the OT protection is triggered the correspondent block is switched off, the thermal shut-down condition only expires when the temperature goes below the “TSD - Thys” temperature (auto-restart). Table 9. UVLO and OT protection management shows the thermal protection management which blocks are switched off after an overtemperature event. 6.2 DC/DC buck regulator The internal DC/DC buck converter provides the 3.3 V supply voltage suitable to supply the MCU and other external devices. The regulator operates in the discontinuous current mode (DCM). A soft-start function with fixed start-up time is implemented to minimize the inrush current at the start-up, refer to Figure 9. Soft-start timing. An overcurrent and short-circuit protection is provided. If a failure event occurs on the SW pin, the regulator is latched off. To restart the DC/DC regulator a power-down and power-up cycle of device supply voltage (VM) is needed. If a failure event occurs on the regulator output (VDDA pin) and the voltage goes below the UVLO threshold (VDDOff), the regulator restarts with a new soft-start sequence until the OC condition is removed. In this case the current in the coil is limited by ISW.peak. The DC/DC regulator embeds a thermal protection as described in Section 6.1.2 Thermal protection. DS12907 - Rev 1 page 16/36 STSPIN32F0B Linear regulator Figure 8. DC/DC buck regulator topology VM LSW To MCU C VDDA VDDA SW VM VM 3.3 V Co ntrol DC/DC buck conv. AM039986 Figure 9. Soft-start timing VDDA [V] 3.3 4.5 t [ms] tSS 6.2.1 External optional 3.3 V supply voltage It is possible provide externally the 3.3 V supply voltage directly on the VDDA pin. In this case, there are two possible configurations: 1. The SW pin floating or shorted to VM: in this case the internal power switch of the DC/DC converter continues to switch on/off according to the internal clock 2. The SW pin shorted to GND or VDD: in this case the internal power switch detects a short-circuit and it is latched off. Note: It is not allowed to apply VDD voltage externally in case of VM < VDD. 6.3 Linear regulator The internal 12 V linear regulator is a LDO regulator providing the supply voltage for the gate drivers section. An external capacitor connected to the VREG12 pin is required. DS12907 - Rev 1 page 17/36 STSPIN32F0B Linear regulator Figure 10. Linear regulator block diagram C REG VREG12 VM 12 V LIN regulator VREG12 When the VM voltage is below to 12 V, the VM pin and the linear regulator output can be shorted together providing the gate driver supply externally. The linear regulator embeds a thermal protection as described in Section 6.1.2 Thermal protection. Figure 11. Linear regulator output characteristics VM [V] 45 13 7.5 7.2 t VREG12 [V] 12 t Note: DS12907 - Rev 1 The linear regulator is designed to supply the internal circuitry only and must not be used to supply external components. page 18/36 STSPIN32F0B Standby mode 6.4 Standby mode The device is forced into the standby mode to reduce power consumption forcing both the OC_TH_STBY1 and OC_TH_STBY2 analog IC inputs low (see Table 12. OC threshold values). When the standby mode is set the analog IC is put into the low consumption mode after a tsleep time, in particular: • • • • The linear regulator is switched off All the output drivers are forced low (external power switches turned off) Op amps and comparators disabled The DC/DC regulator remains operative. When the device exits from the standby mode a set time is necessary to recover a proper value of the 12 V internal regulator. This set time is strictly dependent by the capacitor connected on the VREG12 pin and can be calculated with Equation 1. Figure 12. “Standby to normal” operation timing (CREG = 1 µF) Equation 1 6.5 Gate drivers tREG = CREG ∙ VREG12 IREG12, lim (1) The STSPIN32F0B device integrates a triple half-bridge gate driver able to drive N-channel power MOSFETs or IGBTs. The high-side section is supplied by a bootstrapped voltage technique with an integrated bootstrap diode. All the input lines (refer to Figure 3. Analog IC block diagram) are connected to a pull-down resistor (60 kΩ typical value) to guarantee the low logic level during the device start-up and when the MCU lines are not present. The high- and low-side outputs of same half-bridge cannot be simultaneously driven high thanks to an integrated interlocking function. 6.6 Microcontroller unit The integrated MCU is the STM32F031C6 with following main characteristics: • • • • DS12907 - Rev 1 Core: ARM® 32-bit Cortex™-M0 CPU, frequency up to 48 MHz Memories: 4kB of SRAM, 32 kB of Flash memory CRC calculation unit Up to 20 fast I/Os page 19/36 STSPIN32F0B Microcontroller unit • • • Advanced-control timer dedicated for PWM generation Up to 5 general purpose timers 12-bit ADC (up to 9 channels) • • • Communication interfaces: I2C, USART, SPI Serial wire debug (SWD) Extended temperature range: -40 to 125 °C For more details refer to the STM32F031C6 datasheet on www.st.com 6.6.1 Memories and boot mode The device has the following features: • 4 Kbytes of the embedded SRAM accessed (read/write) at CPU clock speed with 0 wait states and featuring embedded parity checking with an exception generation for fail-critical applications. • The non-volatile memory is divided into two arrays: – 32 Kbytes of the embedded Flash memory for programs and data – Option bytes The option bytes are used to write-protect the memory (with 4 KB granularity) and/or readout-protect the whole memory with the following options: • Level 0: no readout protection • Level 1: memory readout protection, the Flash memory cannot be read from or written to if either debug features are connected or the boot in the RAM is selected • Level 2: chip readout protection, debug features (Cortex-M0 serial wire) and the boot in the RAM selection disabled. At startup the BOOT0 pin and the boot selector option bit are used to select one of the three boot options: • Boot from user Flash memory • Boot from system memory • Boot from embedded SRAM The boot loader is located in the system memory. It is used to reprogram the Flash memory by using USART on pins PA14/PA15. The main Flash memory is aliased in the boot memory space (0x00000000), but still accessible from its original memory space (0x08000000). In other words, the Flash memory contents can be accessed starting from the address 0x00000000 or 0x08000000. 6.6.2 Power management The VDD pin is the power supply for the I/Os and the internal regulator. The VDDA pin is the power supply for the ADC, reset blocks, RCs and PLL. The VDDA voltage can be generated through the internal DC/DC buck converter, otherwise it is possible to provide externally the supply voltage directly on the VDDA pin. Note: The VDDA voltage level must be always greater or equal to the VDD voltage level and must be established first. The MCU has integrated power-on reset (POR) and power-down reset (PDR) circuits. They are always active, and ensure proper operation above a threshold of 2 V. The device remains in the reset mode when the monitored supply voltage is below a specified threshold. • The POR monitors only the VDD supply voltage. During the startup phase it is required that VDDA should arrive first and be greater than or equal to VDD. • The PDR monitors both the VDD and VDDA supply voltages, however the VDDA power supply supervisor can be disabled (by programming a dedicated option bit) to reduce the power consumption if the application design ensures that VDDA is higher than or equal to VDD. The device features an embedded programmable voltage detector (PVD) that monitors the VDD power supply and compares it to the VPVD threshold. An interrupt can be generated when VDD drops below the VPVD threshold DS12907 - Rev 1 page 20/36 STSPIN32F0B Microcontroller unit and/or when VDD is higher than the VPVD threshold. The interrupt service routine can then generate a warning message and/or put the MCU into a safe state. The PVD is enabled by software. The MCU supports three low-power modes to achieve the best compromise between low-power consumption, short start-up time and available wake-up sources: • Sleep mode • In the sleep mode, only the CPU is stopped. All peripherals continue to operate and can wake-up the CPU when an interrupt/event occurs. • Stop mode • The stop mode achieves very low-power consumption while retaining the content of the SRAM and registers. All clocks in the 1.8 V domain are stopped, the PLL, the HSI RC and the HSE crystal oscillators are disabled. The voltage regulator can also be put either in the normal or in the low-power mode. • The device can be woken-up from the stop mode by any of the EXTI lines (one of the 16 external lines, the PVD output, RTC, I2C1 or USART1). • Standby mode • The standby mode is used to achieve the lowest power consumption. The internal voltage regulator is switched off so that the entire 1.8 V domain is powered off. The PLL, the HSI RC and the HSE crystal oscillators are also switched off. After entering the standby mode, SRAM and register contents are lost except for registers in the RTC domain and standby circuitry. • The device exits the standby mode when an external reset (NRST pin), an IWDG reset, • a rising edge on the WKUP pins, or an RTC event occurs. 6.6.3 High-speed external clock source The high-speed external (HSE) clock can be generated from the external clock signal or supplied with a 4 to 32 MHz crystal/ceramic resonator oscillator (see Figure 14. Typical application with 8 MHz crystal). The external clock signal has to respect the I/O characteristics and follows the recommended clock input waveform (refer to Figure 13. HSE clock source timing diagram). Figure 13. HSE clock source timing diagram Figure 14. Typical application with 8 MHz crystal DS12907 - Rev 1 page 21/36 STSPIN32F0B Test mode In the application, the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and startup stabilization time. The REXT value depends on the crystal characteristics (refer to the crystal resonator manufacturer for more details on them). 6.6.4 Advanced-control timer (TIM1) The advanced-control timer (TIM1) can be seen as a three-phase PWM multiplexed on six channels. It has complementary PWM outputs with programmable inserted deadtimes. This timer is used to generate the PWM signal for the three half-bridge gate drivers as shown in Table 10. TIM1 channel configuration. Table 10. TIM1 channel configuration 6.7 MCU I/O Analog IC input TIM1 channel PB13 LS1 TIM1_CH1N PB14 LS2 TIM1_CH2N PB15 LS3 TIM1_CH3N PA8 HS1 TIM1_CH1 PA9 HS2 TIM1_CH2 PA10 HS3 TIM1_CH3 Test mode A dedicated pin TESTMODE is available to enter into the test mode. Note: In the application, the TESTMODE pin should be shorted to GND in order not to enter the test mode inadvertently. 6.8 Operational amplifier The device integrates a rail-to-rail operational amplifier suitable for signal conditioning, in particular for current sensing. The operational amplifier provides a rail-to-rail output stage with fast recovery in the saturation condition. The output stage saturation happens in linear applications when a high amplitude input signal occurs and causes the output of the operational amplifier to move outside its real capabilities. DS12907 - Rev 1 page 22/36 STSPIN32F0B Comparator Figure 15. Operational amplifier To input ADC INN INP 6.9 OP1O OP xN OP1N OP1N OP1P Comparator A comparator is available to perform an overcurrent protection. The OC Comp pin can be connected to the shunt resistor to monitor the load current, the internal OC threshold can be set via MCU (PF6 and PF7 port, see Table 12. OC threshold values). When an OC event is triggered, the OC comparator output signals the OC event to the PB12 and PA12 inputs of MCU (BKIN and ETR). Depending on the status of the OC_SEL signal (see Table 11. OC protection selection) the OC event is acting directly on the control logic of the gate driver switching off all high-side gate outputs, and consequently the external high-side power switches. DS12907 - Rev 1 page 23/36 STSPIN32F0B Comparator Figure 16. Comparator VM To PB12 and PA12 of MCU and control logic OC_COMP OC th COMP Rshunt Table 11. OC protection selection OC_SEL (PA11) Function 0 OC comparator output signal is visible only to MCU (default) 1 OC comparator output signal is visible to MCU and also acts on gate driver control logic Table 12. OC threshold values OC_TH_STBY2 (PF6) OC_TH_STBY1 (PF7) OC threshold [mV] 0 0 N.A. 0 1 100 - 1 0 250 - 1 1 500 - Note Standby mode (see Section 6.4 Standby mode) When the overcurrent condition disappears, the latched overcurrent signal is released only after all the high-side outputs are kept low for at least tOCrelease time. (Refer to Figure 17. Driver logic overcurrent management signals). DS12907 - Rev 1 page 24/36 STSPIN32F0B ESD protection strategy Figure 17. Driver logic overcurrent management signals t > OCdeglitch tCPD Whenthe OCdisappears, the latched OCsignal isreleased after the first HS_inputrising edge tCPD t < OCdeglitch OC_COMP PB12 t > OCrelease OC_blk_n (latched signal) HS1 HS2 HS3 6.10 ESD protection strategy Figure 18. ESD protection strategy VDD(3.3 V) DigitalI/O AnalogI/O GND VM(45 VMAX.) VBOOT POWER BOOTSTRAP DIODE Linear reg. POWER HVU/V/W ESD active POWER clamp POWER REG SW OUT POWER ESD active High-side driver(X3) LVU/V/W clamp ESD active clamp POWER GND Low- sidedriver(X3) DS12907 - Rev 1 BELOW GND page 25/36 STSPIN32F0B Application example 7 Application example Figure 19. Application example shows an application example using the STSPIN32F0B device to drive a threephase motor with single shunt configuration and digital Hall effect sensors. The others features implemented are: • VDD (3.3 V) power supply internally generated via DC/DC regulator • VREG12 (12 V) power supply internally generated via LDO linear regulator • USART serial interface (PB6 and PB7) • Serial wire debug ports (PA13_SWD_IO, PA14_SWD_CLK) • Ready and alarm lines (PF0, PF1) • Reset dedicated pin • Overcurrent protection using internal comparator • Current sensing using operational amplifier and ADC (PA5) • Digital Hall effect sensors decoding (PA0, PA1, PA2) • Bus voltage compensation using internal ADC (PA3) • Application temperature monitoring using internal ADC (PA4) DS12907 - Rev 1 page 26/36 DS12907 - Rev 1 CBUS from Hall ef ect sensors connected to EPAD PB1 PB0 PA7 PA6 PA5 PA4 PA6 PA5 PA4 RTH SWDCLK PA14 NTC OPAMP CTH ADJ REF VDD 3.3V 6 OC_SEL OC comp threshold select 12V VREG VM CREG CVDD COMP RBUS2 STM32F031 control CVM DC/DC Buck conv VM + D1 Control Logic Gate Driver RBUS1 VDD VBAT VM PA3 PA2 PB9 VDDA PA0 PA1 PA2 PA3 VDD PA1 PB8 PA0 BOOT0 CDDA CRST USART_TX PB6 PA14 PA15 PB3 PB4 PB5 PB6 PB7 BOOT0 PB8 PB9 VSS VDD USART_RX PB7 NRST 2 3.3V CDD VM VDD VREG12V VDDA PA15 PF7 PF6 PA13 PA12 PA11 PA10 PA9 PA8 PB15 PB14 PB13 PB12 to VDDA PF1 PC13 PC14 PC15 PF0 PF1 NRST VSSA SWDIO PA13 PF0 RBOOT SW PC15 PC14 CDD VDD L1 CLP RLP VREG12 VREG12 VREG12 VREG12 LS VREG12 HS LS VREG12 HS LS VREG12 HS LSW OUTW HSW VBOOTW LSV OUTV HSV VBOOTV LSU LS OUT HS RGL RGH CBOOT LS HS VM 3x Power Half-Bridge VBOOT HSU OUTU VBOOTU to PA0, PA1, PA2 MCU GPIO Hall M THREE-PHASE MOTOR Application example STSPIN32F0B Figure 19. Application example OC_COMP OP1P OP1N OP1O RESERVED RESERVED RESERVED GND TEST MODE PB11 PB10 PB2 VDD VSS PB1 PA7 page 27/36 STSPIN32F0B Package information 8 Package information In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. A customized VFQFPN48 7 x 7 package is proposed. A smaller EPAD, internally connected to the ground pin, is desired to place through holes on the bottom of the package. Lead plating is Nickel/Palladium/Gold (Ni/Pd/Au). DS12907 - Rev 1 page 28/36 STSPIN32F0B VFQFPN48 7 x 7 package information 8.1 VFQFPN48 7 x 7 package information Figure 20. VFQFPN48 7 x 7 x 1.0 - 48L, pitch 0.5 package outline DS12907 - Rev 1 page 29/36 STSPIN32F0B VFQFPN48 7 x 7 package information Table 13. VFQFPN48 7 x 7 x 1.0 - 48L, pitch 0.5 - package mechanical data Symbol Dimensions (mm) Min. Typ. Max. A 0.90 0.95 1.00 A1 0.0 - 0.05 A2 0.75 A3 0.203 b 0.20 0.25 0.30 D 6.90 7.00 7.10 E 6.90 7.00 7.10 e 0.50 D2 2.50 2.60 2.70 E2 2.50 2.60 2.70 K L 1.80 0.30 0.40 0.50 Figure 21. VFQFPN48 7 x 7 x 1.0 - 48L, pitch 0.5 - suggested footprint DS12907 - Rev 1 page 30/36 STSPIN32F0B Revision history Table 14. Document revision history DS12907 - Rev 1 Date Revision 18-Feb-2019 1 Changes Initial release. page 31/36 STSPIN32F0B Contents Contents 1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2 2 Block diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 3 Electrical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 3.1 Absolute maximum ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3.2 ESD protections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3.3 Recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 3.4 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 4 Electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 5 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 6 Device description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 6.1 6.2 UVLO and thermal protections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 6.1.1 UVLO on supply voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 6.1.2 Thermal protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 DC/DC buck regulator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 6.2.1 External optional 3.3 V supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 6.3 Linear regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 6.4 Standby mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 6.5 Gate drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 6.6 Microcontroller unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 6.6.1 Memories and boot mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 6.6.2 Power management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 6.6.3 High-speed external clock source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 6.6.4 Advanced-control timer (TIM1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 6.7 Test mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 6.8 Operational amplifier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 6.9 Comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 6.10 ESD protection strategy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 7 Application example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 8 Package information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 DS12907 - Rev 1 page 32/36 STSPIN32F0B Contents 8.1 VFQFPN48 7 x 7 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 List of tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 List of figures. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 DS12907 - Rev 1 page 33/36 STSPIN32F0B List of tables List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . ESD protection ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Recommended operating conditions. . . . . . . . . . . . . . . . . . . . . . Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . STSPIN32F0B SiP pin description . . . . . . . . . . . . . . . . . . . . . . . STSPIN32F0B MCU pad mapping . . . . . . . . . . . . . . . . . . . . . . . STSPIN32F0B analog IC pad description . . . . . . . . . . . . . . . . . . UVLO and OT protection management . . . . . . . . . . . . . . . . . . . . TIM1 channel configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . OC protection selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . OC threshold values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VFQFPN48 7 x 7 x 1.0 - 48L, pitch 0.5 - package mechanical data . Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DS12907 - Rev 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 . 6 . 6 . 6 . 7 10 12 13 15 22 24 24 30 31 page 34/36 STSPIN32F0B List of figures List of figures Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. DS12907 - Rev 1 STSPIN32F0B System-In-Package block diagram . . . . . . . Analog IC block diagram . . . . . . . . . . . . . . . . . . . . . . . . . Gate drivers timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . STSPIN32F0B SiP pin connection (top view) . . . . . . . . . . . Gate drivers' outputs characteristics in UVLO conditions . . . Power-up and power-down sequence . . . . . . . . . . . . . . . . DC/DC buck regulator topology. . . . . . . . . . . . . . . . . . . . . Soft-start timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Linear regulator block diagram . . . . . . . . . . . . . . . . . . . . . Linear regulator output characteristics . . . . . . . . . . . . . . . . “Standby to normal” operation timing (CREG = 1 µF) . . . . . . HSE clock source timing diagram . . . . . . . . . . . . . . . . . . . Typical application with 8 MHz crystal . . . . . . . . . . . . . . . . Operational amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . Comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Driver logic overcurrent management signals . . . . . . . . . . . ESD protection strategy . . . . . . . . . . . . . . . . . . . . . . . . . . Application example . . . . . . . . . . . . . . . . . . . . . . . . . . . . VFQFPN48 7 x 7 x 1.0 - 48L, pitch 0.5 package outline . . . . VFQFPN48 7 x 7 x 1.0 - 48L, pitch 0.5 - suggested footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 . 4 . 9 10 15 16 17 17 18 18 19 21 21 23 24 25 25 27 29 30 page 35/36 STSPIN32F0B IMPORTANT NOTICE – PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement. Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers’ products. No license, express or implied, to any intellectual property right is granted by ST herein. Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners. Information in this document supersedes and replaces information previously supplied in any prior versions of this document. © 2019 STMicroelectronics – All rights reserved DS12907 - Rev 1 page 36/36