STSPIN830

STSPIN830 Datasheet Compact and versatile three-phase and three-sense motor driver Features • • Operating voltage from 7 to 45 V Maximum output current 1.5 Arms • RDSon HS + LS = 1 Ω typ. • • • • Supporting both single and three shunts architectures Current control with adjustable OFF time Current sensing based on external shunt resistors Flexible driving methodology user settable between 6 inputs (high side & low side driving) and 3 inputs (direct PWM driving) FOC compatible thanks to three shunts sensing topology support Full protections set: – Non-dissipative overcurrent protection – Short-circuit protection – Underuoltage Lockout – Thermal shutdown – Interlocking function Low standby current consumption • • • Application Product status link STSPIN830 Product summary Order code Package Packing STSPIN830 TFQFPN 4 x 4 x 1.05 - 24L Tape and reel Product label • • • • • • • Industrial robotics Medical and health care Factory automation end-points Home appliances Small pumps Server, computing and general purpose FANs Office and home automation Description STSPIN830 is a compact and versatile field oriented control FOC ready three-phase motor driver. It integrates in a very small 4 x 4 mm QFN package, both the control logic and a fully protected low RDSon triple half-bridge power stage.Thanks to a dedicated MODE input pin the device offers the freedom to decide whether to drive it through 6 inputs (one for each power switch) or a more common 3 PWM direct driving inputs. The STSPIN830 supports both single and three shunts architectures and embeds a PWM current limiter based on user settable values of reference voltage and OFF time.The devices can be forced in a low consumption state reducing the total current consumption down to less than 45 μA. As with all other devices from the STSPIN family, the STSPIN830 integrates a complete set of protections for the power stages (non-dissipative overcurrent, thermal shutdown, short-circuit, undervoltage lockout and interlocking) making it a bulletproof solution for the new wave of demanding industrial applications. DS12584 - Rev 2 - August 2019 For further information contact your local STMicroelectronics sales office. www.st.com STSPIN830 Block diagram 1 Block diagram Figure 1. STSPIN830 block diagram VS UVLO STBY\RESET OVT VS VS EN\FAULT - Vrelease + OC\SC OUTU + SENSEU MODE CONTROL LOGIC INU\INUH OUTV OC\SC ENU\INUL SENSEV INV\INVH ENV\INVL INW\INWH OUTW OC\SC ENW\INWL SENSEW TOFF Oscillator SNS + - GND DS12584 - Rev 2 REF page 2/27 STSPIN830 Electrical data 2 Electrical data 2.1 Absolute maximum ratings Table 1. Absolute maximum ratings Symbol Parameter Value Unit VS Supply voltage -0.3 to 48 V VIN Logic input voltage -0.3 to 5.5 V up to 48 V -2 to 2 V -0.3 to 2 V 1.5 Arms VOUT,diff Differential voltage between VSx, OUTU, OUTV, OUTW and SENSEx pins VSENSE Sense pins voltage(1) VREF Reference voltage input IOUT,RMS Continuous power stage output current (each bridge) Tj Junction temperature -40 to 150 °C TSTG Storage temperature -55 to 150 °C 1. SENSEU, SENSEV, SENSEW, SNS. 2.2 Recommended operating conditions Table 2. Recommended operating conditions Symbol Min Typ Max Unit 7 - 45 V - 5 V VS Supply voltage VIN Logic input voltage VSENSE Sense pins voltage -1 - +1 V Reference voltage input 0.1 - 1 V 400 kHz Value Unit VREF fSW 2.3 Parameter Switching frequency Thermal data Table 3. Thermal data Symbol RthJA Parameter Conditions Junction-to-ambient thermal resistance Natural convection, according to JESD51-2a 1 36.5 °C/W RthJCtop Junction-to-case thermal resistance (top side) Cold plate on top package, according to JESD51-121 27.6 °C/W RthJCbot Junction-to-case thermal resistance (bottom side) Cold plate on exposed pad, according to JESD51-121 5.9 °C/W RthJB Junction-to-board thermal resistance according to JESD51-81 13.6 °C/W ΨJT Junction-to-top characterization According to JESD51-2a1 1 °C/W ΨJB Junction-to-board characterization According to JESD51-2a1 13.7 °C/W 1. Simulated on a 76.2 x 114.3 x 1.6 mm, with vias underneath the component, 2s2p board as per standard Jedec (JESD51-7) in natural convection. DS12584 - Rev 2 page 3/27 STSPIN830 ESD protection ratings 2.4 ESD protection ratings Table 4. ESD protection ratings Symbol HBM CDM Parameter Human body model Charge device model Conditions Class Value Unit Conforming to ANSI/ESDA/JEDEC JS001 H2 2 kV Conforming to ANSI/ESDA/JEDEC JS002 C2a 500 V - 750 V NC 200 V All pins Conforming to ANSI/ESDA/JEDEC JS002 Corner pins only (1, 6, 7, 12, 13, 18, 19, 24) MM DS12584 - Rev 2 Machine model Conforming to EIA/JESD22-A115-C page 4/27 STSPIN830 Electrical characteristics 3 Electrical characteristics Testing conditions: VS = 36 V, Tj = 25 °C unless otherwise specified. Table 5. Electrical characteristics Symbol Parameter Test condition Min Typ Max Unit 6.5 V General VSth(ON) VSth(HYST) VS turn-on threshold VS rising from 0 V 6.0 VS turn-off threshold hysteresis VS falling from 7 V 0.4 V No commutations EN = ‘0’ IS VS supply current 2.3 2.7 mA 2.7 3 mA 0.8 V RTOFF = 10 kΩ No commutations EN = ‘1’ RTOFF = 10 kΩ VSTBYL Standby low voltage VSTBYH Standby high voltage IS, STBY VS supply standby current 2 V STBY = 0 V 45 μA Power stage VS = 21 V 1 IOUT = 1 A RDSon HS+LS Total on resistance HS + LS 1.3 VS = 21 V Ω IOUT = 1 A Tj = 150 °C 1.4 1.6 (1) OUTx = VS= 48 V 20 IDSS Output leakage current VDF Freewheeling diode forward voltage ID = TBD A 1 V trise Rise time VS = 21 V 120 ns tfall Fall time VS = 21 V 60 ns OUTx = -0.3 V -1 μA Logic IO VIH High logic level input voltage VIL Low logic level input voltage VOL Low logic level output voltage VRELEASE DS12584 - Rev 2 2 V IOL = 4 mA FAULT open-drain release voltage 0.8 V 0.3 V 0.6 V RSTBY STBY pull-down resistance 60 kΩ IPDEN Enable pull-down current 5 µA tENd EN input propagation delay From EN falling edge to OUT high impedance 400 ns tINd(ON) Turn-on propagation delay From INxH rising edge to 10% of OUTx 450 ns page 5/27 STSPIN830 Electrical characteristics Symbol tINd(OFF) Parameter Turn-off propagation delay Test condition Min From INxL rising edge to 90% of OUTx Typ Max Unit 250 ns PWM current control VSNS,OFFSET tOFF ΔtOFF tOFF,jitter Current control offset Total OFF time OFF time precision -15 15 mV ROFF = 10 kΩ 13 µs ROFF = 160 kΩ 146 µs Full temperature range (1) 20% +20% % Total OFF time jittering ±2% TjSD Thermal shutdown threshold 160 °C TjSD,Hyst Thermal shutdown hysteresis 40 °C Overcurrent threshold 3 Protections IOC 3.5 A 1. Based on characterization data on a limited number of samples, not tested during production. DS12584 - Rev 2 page 6/27 STSPIN830 Pin description 4 Pin description ENW\INWL INW\INWH ENV\INVL INV\INVH ENU\INUL INU\INUH Figure 2. Pin connection (top view) 24 23 22 21 20 19 REF 1 18 MODE TOFF 2 17 EN\FAULT GND 3 16 STBY\RESET EPAD Note: 5 14 SENSEW GND 6 13 SENSEV 8 9 VS 7 10 11 12 OUTW SENSEU OUTV GND VS 15 NC 4 OUTU SNS the exposed pad must be connected to ground. Table 6. Pin description N. DS12584 - Rev 2 Name Type Function 1 REF Analog input Reference voltage for the PWM current control circuitry 2 TOFF Analog input Internal oscillator frequency adjustment 3, 6, 15 GND Ground 4 SNS Analog input Current limiter sense input 5 SENSEU Power output Sense output of the bridge U 7 OUTU Power output Power bridge output U 9 VS Supply Device supply voltage 10 VS Supply Device supply voltage 11 OUTV Power output Power bridge output V 12 OUTW Power output Power bridge output W 13 SENSEV Power output Sense output of the bridge V 14 SENSEW Power output Sense output of the bridge W Device ground page 7/27 STSPIN830 Pin description N. Name Type 16 STBY\RESET Logic input Function Standby\Reset input When forced low the device enters in low consumption mode 17 18 EN\FAULT MODE Logic input\ Open drain output Logic input Logic input 5 V compliant with open drain output. This is the power stage input enable (when low, the power stage is turned off) and is forced low through the integrated open-drain MOSFET when a failure occurs Inputs driving method selection. When low the ENx\INx option is selected, when high the INxH\INxL option is enabled 19 INU\INUH Logic input Output U high-side driving input (1) 20 ENU\INUL Logic input Output U low-side driving input (1) 21 INV\INVH Logic input Output V high-side driving input (1) 22 ENV\INVL Logic input Output V low-side driving input (1) 23 INW\INWH Logic input Output W high-side driving input (1) 24 ENW\INWL Logic input Output W low-side driving input (1) 8 NC NC Not connected. 1. Refer to :Section 5.2 Logic inputs for more details DS12584 - Rev 2 page 8/27 STSPIN830 Functional description 5 Functional description The STSPIN830 is a 3-phase motor driver integrating a PWM current limiter and a power stage composed by three fully-protected half-bridges. 5.1 Power supply and standby The device is supplied through the VS pins, the two pins must be at the same voltage. At power-up the power stage is disabled and the FAULT pin is forced low until the VS voltage rise above the VSth(ON) threshold. If the VS fall below the VSth(ON) - VSth(HYST) value the power stage is immediately disabled and the FAULT pins are forced low. Figure 3. UVLO protection management VSth(ON) VSth(ON) - VSth(HYST) Vs Internal OD released FAULT POWER stage DISABLED Outputs state according to input status Internal OD released Outputs state according to input status The device provides a low consumption mode which is set forcing the STBY\RESET input below the VSTBYL threshold. When the device is in standby status the power stage is disabled (outputs are in high impedance) and the supply to the integrated control circuitry is strongly reduced. When the device leaves the standby status, all the control circuitry is reset at power-up condition. 5.2 Logic inputs The STSPIN830 offers two alternative method to drive the power stage, the proper can be selected setting the status of MODE pin. If MODE pin is set low (connected to GND) the output of each half bridge is controlled by the respective ENx and INx inputs. If MODE pin is set high the output of each half bridge is controlled by the respective INxH and INxL inputs. In both cases the status of the power bridge is also determined by the PWM current limiter as indicated in Section 5.3 PWM current limiter. Note: DS12584 - Rev 2 The MODE pin status must not be changed during device working. When the EN\FAULT input is forced low the power stage is immediately disabled (all MOSFETs are turned off). The pin is also used as FAULT indication through the integrated open-drain MOSFET as described in paragraph Section 5.4 Device protections and Section 5.5 ESD protection strategy. page 9/27 STSPIN830 PWM current limiter Table 7. ENx and INx inputs truth table (MODE = ‘L’) MODE EN\FAULT ENx INx OUTx ‘x’ Half-bridge condition 0 0 X (1) X(1) High Z (2) Disabled 0 1 0 X(1) High Z (2) Disabled 0 1 1 0 GND LS on 0 1 1 1 VS HS on 1. X: don’t care. 2. High Z: high impedance Table 8. INxL and INxH inputs truth table (MODE = ‘H’) MODE EN\FAULT INxH INxL OUTx ‘x’ Half-bridge condition 1 0 X(1) X(1) High Z (2) Disabled 1 1 0 0 High Z (2) Disabled 1 1 0 1 GND LS on 1 1 1 0 VS HS on 1 1 1 1 High Z (2) Disabled (interlocking) 1. X: don’t care. 5.3 PWM current limiter The device implements a PWM current limiter. The load current is sensed through the SNS pin monitoring the voltage drop across an external resistor connected between the source of the low side power MOSFET (SENSEx pins) and ground. The voltage of the sense pin (VSNS) is compared to the reference voltage pin (VREF). When VSNS > VREF the internal comparator is triggered, the OFF time counter is started and all the power outputs are disabled (high impedance) until the end of count of the timer. During current decays the inputs values are ignored until the system returns to ON condition (decay time expired). The reference voltage value, VREF, has to be selected according the load current target value (peak value) and sense resistors value. Equation 1 (1) VREF = R SENSE × ILOAD, peak The choice of sense resistors value must be take into account two main issues: • The sensing resistor dissipates energy and provides dangerous negative voltages on the SENSE pins during the current recirculation. For this reason the resistance of this component should be kept low (using multiple resistors in parallel will help obtaining the required power rating with standard resistors). • The lower is the RSENSE value, the higher is the peak current error due to noise on VREF pin and to the input offset of the current sense comparator: too small values of RSENSE must be avoided. DS12584 - Rev 2 page 10/27 STSPIN830 PWM current limiter Figure 4. PWM current limit sequence example VS VS VS OUTU M OUTV OUTW OUTU SENSEx R SENSE VS VS VS OUTV M OUTW OUTU M OUTV OUTW SENSEx SENSEx R SENSE RSENSE t OFF VREF/ RSNS Iphase VREF VSENSE - VREF AM040382 Note: When the voltage on the SNS pin exceeds the absolute ratings, fault condition is triggered and the EN\FAULT output is forced low. TOFF adjustment The OFF time is adjusted through an external resistor connected between the TOFF pin and ground as shown in Figure 5. OFF time regulation circuit . Figure 5. OFF time regulation circuit TOFF ROFF AM040383 DS12584 - Rev 2 page 11/27 STSPIN830 Device protections The relation between the OFF time and the external resistor value is shown in the graph of Figure 6. OFF time vs ROFF value. The value typically ranges from 10 μs to 150 μs. The recommended value for ROFF is in the range between 5 kΩ kΩ Figure 6. OFF time vs ROFF value 5.4 Device protections 5.4.1 Overcurrent and short circuit protections The device embeds a circuitry protecting each power MOSFET against the over load and short circuit conditions (short to ground, short to VS and short between outputs). When the overcurrent or the short circuit protection is triggered the power stage is disabled and the EN\FAULT input is forced low through the integrated open drain MOSFET discharging the external CEN capacitor. The power stage is kept disabled and the open drain MOSFET is kept ON until the EN\FAULT input falls below the VRELEASE threshold, then the CEN capacitor is charged through the external REN resistor. DS12584 - Rev 2 page 12/27 STSPIN830 Device protections Figure 7. Overcurrent and short-circuit protections management MCU DEVICE FAULT_MCU VRELEASE EN\FAULT EN_MCU REN RELEASE EN CEN FAULT OC\SC THSD Overcurrent protection VEN VIH VIL VRELEASE Power stage ENABLED DISABLED tdischarge ENABLED t charge t OCSD FAULT t DIS AM040384 The total disable time after an overcurrent event is set sizing properly the external network connected to EN \FAULT pin (refer to Figure 8. Disable time versus REN and CEN values (VDD = 3.3 V) ) and it is the sum of the discharging and charging time of the CEN capacitor: Equation 2 (2) tDIS = tdischarge + tcharge Considering tdischarge is normally significantly lower than tcharge, its contribution is negligible and the disable time is almost equal to tcharge only: Equation 3 (3) VDD − REN × IPD − VRELEASE tDIS ≅ REN × CEN × ln VDD − REN × IPD − VIH Where VDD is the pull-up voltage of REN resistor. The recommended value for REN and CEN are respectively 39 kΩ and 10 nF that allow obtaining 200 µs disable time. DS12584 - Rev 2 page 13/27 STSPIN830 Device protections Figure 8. Disable time versus REN and CEN values (VDD = 3.3 V) Figure 9. Overcurrent threshold versus temperature (normalized at 25 °C) Normalized OC threshold 1.10 1.05 1.00 -40 -20 0 20 40 60 80 100 120 140 160 0.95 0.90 Temperatur e [°C] AM040385 5.4.2 Thermal shutdown The device embeds a circuitry protecting it from the overtemperature condition. When the thermal shutdown temperature is reached the power bridges are disabled and the EN\FAULT input is forced low through the integrated open drain MOSFET (refer to Figure 10. Thermal shutdown management ). The protection and the EN\FAULT output are released when the IC temperature returns below a safe operating value (TjSD - TjSD,Hyst). DS12584 - Rev 2 page 14/27 STSPIN830 ESD protection strategy Figure 10. Thermal shutdown management MCU DEVICE FAULT_MCU V RELEASE EN\FAULT EN_MCU REN RELEASE EN CEN OC\SC THSD FAULT Thermal shutdown TjSD TjSD,hyst Tj VEN VIH VIL VRELEASE Power stage ENABLED DISABLED DISABLED ENABLED t THSD FAULT AM040386 5.4.3 Blanking time The device provides a blanking time tBLANK after each power MOSFET commutation to prevent false triggering of protections and current limiter. During blanking time the protections (overcurrent, short circuit, thermal shutdown) and the comparator of the current limiter are inhibit. 5.5 ESD protection strategy Figure 11. ESD protection strategy VS 48V ESD Active Clamp GND SENSEU SENSEV SENSEW POWER PCH 5 V Internal Reg. OUTU/V/W INV\INVH POWER NCH INx 5V ESD Active Clamp GND INx = ENW\INWL, INW\INWH, ENV\INVL, ENU\INUL, INU\INUH, MODE, STBY\RESET, EN\FAULT, REF, TOFF Below GND SNS DS12584 - Rev 2 page 15/27 STSPIN830 Typical applications 6 Typical applications Table 9. Typical application values Name Value CS 330 nF CSPOL 33 µF RSNS 330 mΩ / 1W CEN 10 nF REN 39 kΩ CSTBY 1 nF RSTBY 18 kΩ ROFF 10 kΩ (TOFF  13 µs) Figure 12. Typical application schematic with single shunt VS VDD R STBY REN CSPOL CS VDD VS STBY\RESET C STBY VS 3-phase Motor OUTU EN\FAULT CEN OUTV MODE OUTW INU\INUH ENU\INUL STSPIN830 INV\INVH SNS SENSEU ENV\INVL SENSEV INW\INWH ENW\INWL PWM SENSEW REF R SNS TOFF R OFF DS12584 - Rev 2 GND page 16/27 STSPIN830 Typical applications Figure 13. Typical application schematic with triple shunt VS VDD R STBY REN CSPOL CS VDD VS STBY\RESET CSTBY VS 3-phase Motor OUTU EN\FAULT CEN OUTV MODE OUTW INU\INUH ENU\INUL STSPIN830 INV\INVH SNS SENSEU ENV\INVL SENSEV INW\INWH ENW\INWL PWM SENSEW REF RSNSW RSNSV RSNSU TOFF ROFF DS12584 - Rev 2 GND page 17/27 STSPIN830 Layout recommendations 7 Layout recommendations The integrates the power stage; in order to improve the thermal dissipation, the exposed pad must be connected to the ground plane on the bottom layer using multiple vias equally spaced. This ground plane acts as a heatsink, for this reason it should be as wide as possible. The voltage supply VS must be stabilized and filtered with a ceramic bypass capacitor, typically 330nF. It must be placed on the same side and as close as possible to VS pin in order to reject high frequency noise components on the supply. A bulk capacitor could also be required (typically a 33 μF). The connection between the power supply connector and the VS pins must be as short as possible using wide traces. In order to ensure the best ground connection between the and the other components, a GND plane surrounding the device is recommended. A capacitor between REF pins and ground should be positioned as near as possible to the device in order to filter the noise and stabilize the reference voltage. Several vias should be positioned as near as possible each sense resistor connecting them to the ground plane on the bottom layer. In this way, both the GND planes provide a path for the current flowing into the power stage. The path between the ground of the shunt resistors and the ceramic bypass capacitor of the device is critical; for this reason it must be as short as possible minimizing parasitic inductances that can cause voltage spikes on SENSE and OUT pins. The OUT pins and the VS nets can be routed using the bottom layer, it is recommended to use two vias for output connections. Figure 14. PCB layout example with triple shunt (top layer) STSPIN830 VREF capacitor for noise filtering placed close to VREF leads Vias on exposed pad to improve thermal dissipation Shunt resistor close to respective SENSE and SNS leads Ground plane: connects all the grounds on the TOP layer to reduce parasitic effects Several vias to connect the shunt ground with the bottom ground plane Several vias to connect the shunt ground with the bottom ground plane OUT tracks vias Ceramic bypass capacitor close to VS leads OUT tracks vias AM040390 In case of single shunt configuration take special care for the SENSE and SNS pins connection. As suggested in the Figure 15. PCB layout example with single shunt (top layer) and Figure 16. PCB layout example with single shunt (bottom layer), the shunt resistor can be placed in the top layer close to SENSEU and SNS pins with a wide copper area and vias. The connection with other sense pins (SENSEV and SENSEW) can be routed in the bottom layer taking care to maximize the track area and add more vias near to the pins. DS12584 - Rev 2 page 18/27 STSPIN830 Layout recommendations Figure 15. PCB layout example with single shunt (top layer) Vias on exposed pad to improve thermal dissipation STSPIN830 VREF capacitor for noise filtering: placed close to VREF leads Shunt resistor close to respective SENSE and SNS leads Ground plane: connects all the grounds on the TOP layer to reduce parasitic effects Several vias to connect the shunt tracks with the bottom plane Several vias to connect the shunt ground with the bottom ground plane Several vias to connect the shunt tracks with the bottom plane OUT tracks vias Ceramic bypass capacitor close to VS leads OUT tracks vias AM040391 Figure 16. PCB layout example with single shunt (bottom layer) STSPIN830 Top layer tracks Bottom layer tracks SENSE GND OUTs AM040392 DS12584 - Rev 2 page 19/27 STSPIN830 Package information 8 Package information In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK®packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. 8.1 TFQFPN 4x4x1.05 24L package information Figure 17. TFQFPN 4 x 4 x 1.05 - 24L package outline BOTTOM VIEW SIDE VIEW TOP VIEW TFQFPN-4x4x1.05-24 DS12584 - Rev 2 page 20/27 STSPIN830 TFQFPN 4x4x1.05 24L package information Table 10. TFQFPN 4x4x1.05 24L package mechanical data Dimensions Symbol (mm) Min. Typ. Max. A 0.90 1.00 1.10 A1 0.00 0.02 0.05 b 0.20 0.25 0.30 D 3.90 4.00 4.10 D2 2.55 2.60 2.65 E 3.90 4.00 4.10 E2 2.55 2.60 2.65 e L NOTES (1) 0.50 0.35 0.40 k 0.30 ddd 0.05 0.45 Dimension “b” does 1. not include dambar protrusion. Allowable dambar protrusion shall not cause the lead width to exceed the maximum “b” dimension by more than 0.08 mm Figure 18. TFQFPN 4 x 4 x 1.05 - 24L suggested footprint TFQFPN 4 x 4 x 1.05 - 24 L DS12584 - Rev 2 page 21/27 STSPIN830 Ordering information 9 Ordering information Table 11. Ordering information DS12584 - Rev 2 Order code Package Packing STSPIN830 TFQFPN 4 x 4 x 1.05 - 24L Tape and reel page 22/27 STSPIN830 Revision history Table 12. Document revision history DS12584 - Rev 2 Date Version Changes 18-May-2018 1 Initial release. 02 Aug-2019 2 Some minor text changes inside the document, cover image updated, updated Table 2. Recommended operating conditions page 23/27 STSPIN830 Contents Contents 1 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2 2 Electrical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 2.1 Absolute maximum ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2.2 Recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2.3 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2.4 ESD protection ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 3 Electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 4 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 5 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 5.1 Power supply and standby . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 5.2 Logic inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 5.3 PWM current limiter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 5.4 Device protections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 5.5 5.4.1 Overcurrent and short circuit protections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 5.4.2 Thermal shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 5.4.3 Blanking time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 ESD protection strategy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 6 Typical applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 7 Layout recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 8 Package information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 8.1 9 [Package name] package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 List of tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 List of figures. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 DS12584 - Rev 2 page 24/27 STSPIN830 List of tables List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Absolute maximum ratings . . . . . . . . . . . . . . . . Recommended operating conditions. . . . . . . . . . Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . ESD protection ratings . . . . . . . . . . . . . . . . . . . Electrical characteristics . . . . . . . . . . . . . . . . . . Pin description. . . . . . . . . . . . . . . . . . . . . . . . . ENx and INx inputs truth table (MODE = ‘L’) . . . . INxL and INxH inputs truth table (MODE = ‘H’). . . Typical application values . . . . . . . . . . . . . . . . . TFQFPN 4x4x1.05 24L package mechanical data Ordering information. . . . . . . . . . . . . . . . . . . . . Document revision history . . . . . . . . . . . . . . . . . DS12584 - Rev 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 . 3 . 3 . 4 . 5 . 7 10 10 16 21 22 23 page 25/27 STSPIN830 List of figures List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. DS12584 - Rev 2 STSPIN830 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin connection (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . UVLO protection management . . . . . . . . . . . . . . . . . . . . . . . . PWM current limit sequence example . . . . . . . . . . . . . . . . . . . OFF time regulation circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . OFF time vs ROFF value . . . . . . . . . . . . . . . . . . . . . . . . . . . . Overcurrent and short-circuit protections management . . . . . . . Disable time versus REN and CEN values (VDD = 3.3 V). . . . . . Overcurrent threshold versus temperature (normalized at 25 °C). Thermal shutdown management . . . . . . . . . . . . . . . . . . . . . . . ESD protection strategy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Typical application schematic with single shunt . . . . . . . . . . . . . Typical application schematic with triple shunt . . . . . . . . . . . . . PCB layout example with triple shunt (top layer) . . . . . . . . . . . . PCB layout example with single shunt (top layer) . . . . . . . . . . . PCB layout example with single shunt (bottom layer) . . . . . . . . . TFQFPN 4 x 4 x 1.05 - 24L package outline . . . . . . . . . . . . . . . TFQFPN 4 x 4 x 1.05 - 24L suggested footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 . 7 . 9 11 11 12 13 14 14 15 15 16 17 18 19 19 20 21 page 26/27 STSPIN830 IMPORTANT NOTICE – PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement. Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers’ products. No license, express or implied, to any intellectual property right is granted by ST herein. Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. ST and the ST logo are trademarks of ST. For additional information about ST trademarks, please refer to www.st.com/trademarks. All other product or service names are the property of their respective owners. Information in this document supersedes and replaces information previously supplied in any prior versions of this document. © 2019 STMicroelectronics – All rights reserved DS12584 - Rev 2 page 27/27