STSPIN840
Compact dual brushed DC motor driver
Datasheet - production data
Description
The STSPIN840 is a compact brushed DC motor
driver able to drive two bi-directional brushed DC
motors simultaneously. It integrates, in a very
small 4 x 4 mm QFN package, both the control
logic and a fully protected low RDSon dual fullbridge power stage.
QFN 4 x 4 - 24 lead
Thanks to a dedicated PARALLEL input pin the
parallel mode function can be enabled,
transforming the device in an equivalent and
more powerful single full-bridge able to deliver up
to 3Arms current at an equivalent HS + LS RDSon
of 500 m.
Features
Operating voltage from 7 to 45 V
Maximum output current 1.5 Arms
RDSon HS + LS = 1 typ.
Current control with adjustable OFF time
Current sensing based on external shunt
resistors
Full protections set
– Non-dissipative overcurrent protection
– Short-circuit protection
– Undervoltage lockout
– Thermal shutdown
Parallel operation mode achieving single fullbridge configuration with output IRMS = 3 Arms
and RDSon HS + LS = 500 m typ.
Low standby current consumption
The STSPIN840 embeds two independent PWM
current controllers (one for each full bridge) based
on user settable values of reference voltage and
OFF time.
The devices can be forced in a low consumption
state reducing the total current consumption down
to less than 45 A.
As with all other devices from the STSPIN family,
the STSPIN840 integrates a complete set of
protections for the power stages (non-dissipative
overcurrent, thermal shutdown, short-circuit and
undervoltage lockout) making it a bulletproof
solution for the new wave of demanding industrial
applications.
Applications
Industrial automation and service robots
Medical and health care
ATM and money handling machines
Stage lighting
Thermal printers
Textile and sewing machines
Vending machines
Office and home automation
May 2018
This is information on a product in full production.
DocID031835 Rev 1
1/28
www.st.com
Contents
STSPIN840
Contents
1
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2
Electrical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.1
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.2
Recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.3
Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.4
ESD protection ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
4
Pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
5
Detailed description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
5.1
Power supply and standby . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
5.2
Logic inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
PARALLEL mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
5.3
PWM current control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
TOFF adjustment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
5.4
5.5
Device protections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
5.4.1
Overcurrent and short-circuit protections . . . . . . . . . . . . . . . . . . . . . . . . 18
5.4.2
Thermal shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
5.4.3
Blanking time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
ESD protection strategy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
6
Typical applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
7
Layout recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
8
Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
8.1
TFQFPN TFQFPN 4 x 4 x 1.05 - 24 L package information . . . . . . . . . . 25
9
Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
10
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
2/28
DocID031835 Rev 1
STSPIN840
List of tables
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
ESD protection ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Truth table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
ON and slow decay states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Typical application values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
TFQFPN 4 x 4 x 1.05 - 24 L package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
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28
List of figures
STSPIN840
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
Figure 13.
Figure 14.
Figure 15.
Figure 16.
Figure 17.
4/28
Block diagram (general) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Pin connection (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
UVLO protection management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Dual brush DC motor driver time diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
PARALLEL mode typical application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
PWM current control sequence example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
OFF time regulation circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
OFF time vs ROFF value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Overcurrent and short-circuit protections management . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Disable time versus REN and CEN values (VDD = 3.3 V) . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Overcurrent threshold versus temperature (normalized at 25 °C) . . . . . . . . . . . . . . . . . . . 20
Thermal shutdown management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
ESD protection strategy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Typical application schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
PCB layout example (top layer) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
TFQFPN 4 x 4 x 1.05 - 24 L package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
TFQFPN 4 x 4 x 1.05 - 24 L suggested footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
DocID031835 Rev 1
STSPIN840
1
Block diagram
Block diagram
Figure 1. Block diagram (general)
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DocID031835 Rev 1
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28
Electrical data
STSPIN840
2
Electrical data
2.1
Absolute maximum ratings
Table 1. Absolute maximum ratings
Symbol
Parameter
Test condition
Value
Unit
VS
Supply voltage
-
-0.3 to 48
V
VIN
Logic input voltage
-
-0.3 to 5.5
V
Differential voltage between VSx, OUT1x, OUT2x and
SENSEx pins
-
up to 48
V
-
-2 to 2
V
-
-0.3 to 2
V
-
1.5
Arms
VOUT,diff
VSENSE Sense pins voltage(1)
VREFX
Reference voltage input
IOUT,RM Continuous power stage output current
(each full bridge)
S
Tj
Junction temperature
-
-40 to 150
°C
Tstg
Storage temperature
-
-55 to 150
°C
1. SENSEA1, SENSEA2, SNSA, SENSEB1, SENSEB2, SNSB.
2.2
Recommended operating conditions
Table 2. Recommended operating conditions
Symbol
Parameter
VS
Supply voltage
VIN
Logic input voltage
VSENSE Sense pins voltage
VREFX
6/28
Reference voltage input
DocID031835 Rev 1
Min.
Typ.
Max.
Unit
7
-
45
V
-
5
V
-1
-
+1
V
0.1
-
1
V
STSPIN840
2.3
Electrical data
Thermal data
Table 3. Thermal data
Symbol
RthJA
Parameter
Junction to ambient thermal
resistance
Conditions
Natural convection, according to
JESD51-2a(1)
Value
Unit
36.5
°C/W
RthJCtop
Junction to case thermal resistance Cold plate on top package, according
(top side)
to JESD51-12(1)
27.6
°C/W
RthJCbot
Junction to case thermal resistance Cold plate on exposed pad,
(bottom side)
according to JESD51-12(1)
5.9
°C/W
Junction to board thermal
resistance
According to JESD51-8(1)
13.6
°C/W
JT
Junction to top characterization
According to JESD51-2a(1)
1
°C/W
JB
Junction to board characterization
According to JESD51-2a(1)
13.7
°C/W
RthJB
1. Simulated on a 76.2 x 114.3 x 1.6 mm, with vias underneath the component, 2s2p board as per standard
JEDEC (JESD51-7) in natural convection.
2.4
ESD protection ratings
Table 4. ESD protection ratings
Symbol
HBM
CDM
MM
Parameter
Human body model
Charge device model
Machine model
Conditions
Class Value Unit
Conforming to ANSI/ESDA/JEDEC JS001
H2
2
kV
Conforming to ANSI/ESDA/JEDEC JS002
All pins
C2a
500
V
-
750
V
NC
200
V
Conforming to ANSI/ESDA/JEDEC JS002
Corner pins only (1, 6, 7, 12, 13, 18, 19, 24)
Conforming to EIA/JESD22-A115-C
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28
Electrical characteristics
3
STSPIN840
Electrical characteristics
Testing conditions: VS = 36 V, Tj = 25 °C unless otherwise specified.
Table 5. Electrical characteristics
Symbol
Parameter
Test condition
Min.
Typ.
Max. Unit
General
VSth(ON)
VSth(HYST)
IS
VS turn-on threshold
VS rising from 0 V
-
6.0
6.5
V
VS turn-off threshold hysteresis
VS falling from 7 V
-
0.4
-
V
No commutations
ENx = '0'
RTOFF = 10 k
-
2.3
2.7
mA
No commutations
ENx = '1'
RTOFF = 10 k
-
2.7
3
mA
VS supply current
VSTBYL
Standby low voltage
-
-
-
0.8
V
VSTBYH
Standby high voltage
-
2
-
-
V
IS, STBY
VS supply standby current
STBY = '0'
-
-
45
A
VS = 21 V
IOUT = 1 A
-
1
1.3
VS = 21 V
IOUT = 1 A
Tj = 150 °C(1)
-
1.4
1.6
OUTx = VS = 48 V
-
-
20
OUTx = -0.3 V
-1
-
-
Power stage
RDSon HS+LS Total on resistance HS + LS
A
IDSS
Output leakage current
VDF
Freewheeling diode forward voltage
ID = 1.5 A
-
1
-
V
trise
Rise time
VS = 21 V
-
120
-
ns
tfall
Fall time
VS = 21 V
-
60
-
ns
VIH
High logic level input voltage
-
2
-
-
V
VIL
Low logic level input voltage
-
-
-
0.8
V
VOL
Low logic level output voltage
IOL = 4 mA
-
-
0.3
V
FAULT open drain release voltage
-
-
-
0.6
V
STBY pull-down resistance
-
-
60
-
k
IENx
Enable pull-down current
-
-
5
-
µA
tENxd
Enable input propagation delay
From ENx falling edge to OUTx
high impedance
-
400
-
ns
tPWM,d(ON)
PWM turn-on propagation delay
(2)
-
-
ns
Logic IO
VRELEASE
RSTBY
8/28
DocID031835 Rev 1
450
STSPIN840
Electrical characteristics
Table 5. Electrical characteristics (continued)
Symbol
tPWM,d(OFF)
tPH,d
Parameter
Test condition
Min.
Typ.
Max. Unit
PWMx turn-off propagation delay
(2)
-
250
-
ns
PHx propagation delay
(2)
-
450
-
ns
-
-15
-
15
mV
-
-
1.5
-
µs
ROFF = 10 k
-
13
-
µs
ROFF = 160 k
-
146
-
µs
-20
-
+20
PWM current control
VSNS,OFFSET Current control offset
tBLANK
Blanking time
tOFF
Total OFF time
tOFF
OFF time precision
Full temperature range(1)
Total OFF time jittering
-
-
±2
-
TjSD
Thermal shutdown threshold
-
-
160
-
°C
TjSD,Hyst
Thermal shutdown hysteresis
-
-
40
-
°C
Overcurrent protection threshold
-
-
3
3.5
A
tOFF,jitter
%
Protections
IOC
1. Based on characterization data on a limited number of samples, not tested during production.
2. See Figure 4.
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28
Pin connection
4
STSPIN840
Pin connection
TOFF
PA RA L LE L
PHB
PW MB
PHA
PW MA
Figure 2. Pin connection (top view)
24
23
22
21
20
19
REFA
1
18
ENB\ FAULTB
REFB
2
17
ENA\ FAULTA
GND
3
16
STBY\RESET
SNSA
4
15
SNSB
SENSEA1
5
14
SENSEB1
SENSEA2
6
13
SENSEB2
7
8
9
10
11
12
OUTA1
OUTA 2
VS
VS
OUTB 2
OUTB 1
EPA D
AM040367
Note:
The exposed pad must be connected to ground.
Table 6. Pin description
10/28
No.
Name
Type
Function
1
REFA
Analog input
Reference voltage for the PWM current control circuitry (side A)
2
REFB
Analog input
Reference voltage for the PWM current control circuitry (side B)
3,
EPAD
GND
Ground
4
SNSA
Analog input
5
SENSEA1
Power output Sense output of the bridge A
6
SENSEA2
Power output Sense output of the bridge A
7
OUTA1
Power output Power bridge output side A1
8
OUTA2
Power output
Device ground
Full bridge A current regulator sense input
Power bridge output side A2
DocID031835 Rev 1
STSPIN840
Pin connection
Table 6. Pin description (continued)
No.
Name
Type
Function
9
VS
Supply
Device supply voltage
10
VS
Supply
Device supply voltage
11
OUTB2
Power output Power bridge output side B2
12
OUTB1
Power output Power bridge output side B1
13
SENSEB2
Power output Sense output of the bridge B
14
SENSEB1
Power output Sense output of the bridge B
15
SNSB
Analog input
16
STBY\
RESET
Logic input
Standby\Reset input.
When forced low the device enter in low consumption mode
17
ENA\
FAULTA
Logic input\
open drain
output
Logic input 5 V compliant with open drain output.
This is the full bridge A enable (when low, the power stage is
turned off) and is forced low through the integrated open-drain
MOSFET when a failure occurs.
18
ENB\
FAULTB
Logic input\
open drain
output
Logic input 5 V compliant with open drain output.
This is the full bridge B enable (when low, the power stage is
turned off) and is forced low through the integrated open-drain
MOSFET when a failure occurs.
19
PWMA
Logic input
Full bridge A PWM input
20
PHA
Logic input
Full bridge A current direction input
21
PWMB
Logic input
Full bridge B PWM input
22
PHB
Logic input
Full bridge B current direction input
23
PARALLEL
Logic input
Parallel mode input (see paragraph PARALLEL mode)
24
TOFF
Analog input
Full bridge B current regulator sense input
Internal oscillator frequency adjustment.
DocID031835 Rev 1
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28
Detailed description
5
STSPIN840
Detailed description
The STSPIN840 is a dual brush DC motor driver integrating two PWM current controllers
and a power stage composed of two fully-protected full-bridges.
5.1
Power supply and standby
The device is supplied through the VS pins, the two pins must be at the same voltage.
At power-up the power stage is disabled and the FAULT pins are forced low until the VS
voltage rise above the VSth(ON) threshold.
If the VS falls below the VSth(ON) - VSth(HYST) value power stage is immediately disabled and
the FAULT pins are forced low.
Figure 3. UVLO protection management
VSth(ON)
VSth(ON) - VSth( HYST)
VS
Internal OD
released
FAULT
POWER
stage
DISABLED
Outputs state
according to
input status
Internal OD
released
Outputs state
according to
input status
AM040368
The device provides a low consumption mode, which is set by forcing the STBY\RESET
input below the VSTBYL threshold.
When the device is in standby status the power stage is disabled (outputs are at high
impedance) and the supply to the integrated control circuitry is strongly reduced. When the
device leaves the standby status, all the control circuitry is reset to the power-up condition.
12/28
DocID031835 Rev 1
STSPIN840
5.2
Detailed description
Logic inputs
The outputs of each full bridge are controlled by the respective PWMx and PHx inputs. The
status of the power bridge is also determined by the PWM current controller as indicated in
Section 5.3.
Table 7. Truth table
ENx
PHx
PWMx
OUTx1
OUTx2
Full bridge condition
0
X(1)
X(1)
High Z(2)
High Z(2)
1
0
0
GND
GND
1
0
1
GND
VS
1
1
0
GND
GND
Both LS on
1
1
1
VS
GND
HS1 and LS2 on (current OUTx1 OUTx2)
Disabled
Both LS on
HS2 and LS1 on (current OUTx1 OUTx2)
1. X: don't care.
2. High Z: high impedance.
Figure 4. Dual brush DC motor driver time diagram
1)Y
18.Y
U 18.
E 0''
U 18.
E 0/
U 1)
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065Y
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065Y
".
DocID031835 Rev 1
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28
Detailed description
STSPIN840
PARALLEL mode
The device can operate in parallel mode by forcing the PARALLEL input pin high.
In this operation mode both the full bridges are driven by the ENA, PWMA and PHA inputs.
The PWM current control comparator of the bridge B is disabled, and bridge A one drives
both the power stages.
The resulting single full-bridge power stage allows an increase in the output current
capability and reduce the device power dissipation. The outputs and sense pins
configuration must be:
OUT1A connected with OUT1B
OUT2A connected with OUT2B
All SENSE and SNS pins connected together as shown in Figure 5.
The ENA\FAULTA pin is also used as FAULT indication through the integrated open-drain
MOSFETs as described in Section 5.4 and Section 5.4.3 on page 21.
Note:
In parallel mode the ENB\FAULTB pin is forced low.
Figure 5. PARALLEL mode typical application
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STSPIN840
5.3
Detailed description
PWM current control
The device implements two independent PWM current controllers, one for each full bridge.
The bridge current is sensed through the SNS pins monitoring the voltage drop across an
external resistor connected between the source of the low side power MOSFET (SENSE
pins) and ground.
The voltage of the SNS pins (VSNSA and VSNSB) is compared to the respective reference
voltage pin (VREFA and VREFB).
When VSNSX > VREFX the current limiter is triggered, the OFF time counter is started and the
low sides of the full bridge are turned on (slow decay) until the end of count of the timer.
During current decays the inputs values are ignored until the system returns to ON condition
(decay time expired).
Table 8. ON and slow decay states
PHx(1)
0
0
1
1
PWMx(1)
ON
Slow decay
0
HSx1 = OFF
LSx1 = ON
HSx2 = OFF
LSx2 = ON
HSx1 = OFF
LSx1 = ON
HSx2 = OFF
LSx2 = ON
1
HSx1 = OFF
LSx1 = ON
HSx2 = ON
LSx2 = OFF
HSx1 = OFF
LSx1 = ON
HSx2 = OFF
LSx2 = ON
0
HSx1 = OFF
LSx1 = ON
HSx2 = OFF
LSx2 = ON
HSx1 = OFF
LSx1 = ON
HSx2 = OFF
LSx2 = ON
1
HSx1 = ON
LSx1 = OFF
HSx2 = OFF
LSx2 = ON
HSx1 = OFF
LSx1 = ON
HSx2 = OFF
LSx2 = ON
1. When the device works in parallel mode the PHA and PWMA inputs drive both Full bridge A and B.
The reference voltage value, VREF, has to be selected according the load current target
value (peak value) and sense resistors value.
Equation 1
VREF = RSENSE ILOAD,peak
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Detailed description
STSPIN840
The choice of sense resistors value must be take into account two main issues:
The sensing resistor dissipates energy and provides dangerous negative voltages on
the SENSE pins during the current recirculation. For this reason the resistance of this
component should be kept low (using multiple resistors in parallel will help obtaining
the required power rating with standard resistors).
The lower is the RSENSE value, the higher is the peak current error due to noise on
VREF pin and to the input offset of the current sense comparator: too small values of
RSENSE must be avoided.
Figure 6. PWM current control sequence example
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16/28
When the voltage on the SNSx pin exceeds the absolute ratings, a fault condition is
triggered and the respective ENx\FAULTx output is forced low.
DocID031835 Rev 1
STSPIN840
Detailed description
TOFF adjustment
The OFF time is adjusted through an external resistor connected between the TOFF pin and
ground as shown in Figure 7.
Figure 7. OFF time regulation circuit
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The relation between the OFF time and the external resistor value is shown in the graph of
Figure 8. The value typically ranges from 10 µs to 150 µs.
The recommended value for ROFF is in the range between 5 k and 180 k.
Figure 8. OFF time vs ROFF value
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28
Detailed description
STSPIN840
5.4
Device protections
5.4.1
Overcurrent and short-circuit protections
The device has circuitry embedded to protect each power MOSFET against the overload
and short-circuit conditions (short-circuit to ground, short-circuit to VS and short-circuit
between outputs).
When the overcurrent or the short-circuit protection is triggered the respective power stage
is disabled and the relative EN\FAULT input is forced low through the integrated open-drain
MOSFET discharging the external CEN capacitor (refer to Figure 9).
The power stage is kept disabled and the open-drain MOSFET is kept ON until the
EN\FAULT input falls below the VRELEASE threshold, then the CEN capacitor is charged
through the external REN resistor.
Figure 9. Overcurrent and short-circuit protections management
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The total disable time after an overcurrent event is set sizing properly the external network
connected to EN\FAULT pins (refer to Figure 10) and it is the sum of the discharging and
charging time of the CEN capacitor:
Equation 2
tDIS = tdischarge + tcharge
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STSPIN840
Detailed description
Considering tdischarge is normally significantly lower than tcharge, its contribution is negligible
and the disable time is almost equal to tcharge only:
Equation 3
V DD – R EN I PD – V RELEASE
t DIS R EN C EN I n --------------------------------------------------------------------------------- V DD – R EN I PD – V IH
Where VDD is the pull-up voltage of REN resistor.
The recommended value for REN and CEN are respectively 39 k and 10 nF that allow
obtaining 300 µs disable time.
Figure 10. Disable time versus REN and CEN values (VDD = 3.3 V)
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Detailed description
STSPIN840
Figure 11. Overcurrent threshold versus temperature (normalized at 25 °C)
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5.4.2
Thermal shutdown
The device has circuitry embedded to protect it from overtemperature conditions.
When the thermal shutdown temperature is reached both the power bridge are disabled and
both the EN\FAULT inputs are forced low through the integrated open-drain MOSFETs (refer
to Figure 12).
The protection and the EN\FAULT outputs are released when the IC temperature returns
below a safe operating value (TjSD - TjSD,Hyst).
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STSPIN840
Detailed description
Figure 12. Thermal shutdown management
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5.4.3
Blanking time
The device provides a blanking time tBLANK after each power MOSFET commutation to
prevent false triggering of protections and current control.
During blanking time the following circuits are inhibited:
Overcurrent and short-circuit protections of commutating power stage
Current control comparator of the commutating power stage
Thermal protection of the commutating power stage.
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Detailed description
5.5
STSPIN840
ESD protection strategy
Figure 13. ESD protection strategy
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STSPIN840
6
Typical applications
Typical applications
Table 9. Typical application values
Name
Value
CS
330 nF
CSPOL
33 µF
RSNSA, RSNSB
330 m / 1 W
CENA, CENB
10 nF
RENA, RENB
39 k
CSTBY
1 nF
RSTBY
18 k
ROFF
10 k (TOFF 13 µs)
Figure 14. Typical application schematic
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DocID031835 Rev 1
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28
Layout recommendations
7
STSPIN840
Layout recommendations
The STSPIN840 device integrates the power stage; in order to improve the thermal
dissipation, the exposed pad must be connected to the ground plane on the bottom layer
using multiple vias equally spaced. This ground plane acts as a heatsink, for this reason it
should be as wide as possible.
The voltage supply VS must be stabilized and filtered with a ceramic bypass capacitor,
typically 330 nF. It must be placed on the same side and as close as possible to the VS pin
in order to reject high frequency noise components on the supply. A bulk capacitor could
also be required (typically a 33 F). The connection between the power supply connector
and the VS pins must be as short as possible using wide traces.
In order to ensure the best ground connection between the STSPIN840 and the other
components, a GND plane surrounding the device is recommended.
A capacitor between REF pins and ground should be positioned as near as possible to the
device in order to filter the noise and stabilize the reference voltage.
Several vias should be positioned as near as possible each sense resistor connecting them
to the ground plane on the bottom layer. In this way, both the GND planes provide a path for
the current flowing into the power stage.
The path between the ground of the shunt resistors and the ceramic bypass capacitor of the
device is critical; for this reason it must be as short as possible minimizing parasitic
inductances that can cause voltage spikes on SENSE and OUT pins.
The OUT pins and the VS nets can be routed using the bottom layer, it is recommended to
use two vias for output connections.
Figure 15. PCB layout example (top layer)
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STSPIN840
8
Package information
Package information
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK® is an ST trademark.
8.1
TFQFPN TFQFPN 4 x 4 x 1.05 - 24 L package information
Figure 16. TFQFPN 4 x 4 x 1.05 - 24 L package outline
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5'2'1/YY
DocID031835 Rev 1
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28
Package information
STSPIN840
Table 10. TFQFPN 4 x 4 x 1.05 - 24 L package mechanical data
Dimensions (mm)
Symbol
Note
Min.
Typ.
Max.
A
0.90
1.00
1.10
-
A1
0.00
0.02
0.05
-
b
0.20
0.25
0.30
(1)
D
3.90
4.00
4.10
-
D2
2.55
2.60
2.65
-
E
3.90
4.00
4.10
-
E2
2.55
2.60
2.65
-
e
-
0.50
-
-
L
0.35
0.40
0.45
k
-
0.30
-
-
ddd
-
0.05
-
-
1. Dimension “b” does not include dambar protrusion. Allowable dambar protrusion shall not cause the lead
width to exceed the maximum “b” dimension by more than 0.08 mm.
Figure 17. TFQFPN 4 x 4 x 1.05 - 24 L suggested footprint
5'2'1/YY-
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STSPIN840
9
Ordering information
Ordering information
Table 11. Device summary
10
Order code
Package
Packaging
STSPIN840
TFQFPN 4 x 4 x 1.05 - 24 L
Tape and reel
Revision history
Table 12. Document revision history
Date
Revision
18-May-2018
1
Changes
Initial release.
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STSPIN840
IMPORTANT NOTICE – PLEASE READ CAREFULLY
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improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on
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acknowledgement.
Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or
the design of Purchasers’ products.
No license, express or implied, to any intellectual property right is granted by ST herein.
Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product.
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Information in this document supersedes and replaces information previously supplied in any prior versions of this document.
© 2018 STMicroelectronics – All rights reserved
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