STTS424
Memory module temperature sensor
Features
■
Temperature sensor compliant with JEDEC
JC42.4
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Temperature sensor
■
Temperature sensor resolution:
0.25°C (typ)/LSB
■
Temperature sensor accuracy:
– ± 1°C from +75°C to +95°C
– ± 2°C from +40°C to +125°C
– ± 3°C from –40°C to +125°C
■
ADC conversion time: 125 ms (max)
■
Supply voltage: 2.7 V to 3.6 V
■
Maximum operating supply current: 200 µA
■
Hysteresis selectable set points from: 0, 1.5, 3,
6.0°C
■
Ambient temperature sensing range: –40°C to
125°C
■
Supports bus timeout
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TDFN8 (DN)
2 mm x 3 mm (max height 0.80 mm)
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Two-wire bus
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2-wire SMBus/I2C - compatible serial interface
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Supports up to 400 kHz transfer rate
■
Does not initiate clock stretching
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Packages
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2 mm x 3 mm TDFN8, height: 0.80 mm (max)(a)
■
RoHS compliant, halogen-free
a. Compliant to JEDEC MO-229, WCED-3
April 2009
Rev 6
1/36
www.st.com
1
Contents
STTS424
Contents
1
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2
Serial communications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3
2.1
Device type identifier (DTI) code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.2
Pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.2.1
A0, A1, A2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.2.2
VSS (ground) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.2.3
SDA (open drain) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.2.4
SCL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.2.5
EVENT (open drain) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.2.6
VDD (power) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
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Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
4
3.1
SMBus/I2C
3.2
SMBus/I2
3.3
SMBus/I2C AC timing consideration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.4
SMBus timeout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
communications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
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C slave sub-address decoding . . . . . . . . . . . . . . . . . . . . . . . . . 12
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Temperature sensor registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
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Capability register (read-only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
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4.3
4.1.1
Alarm window trip . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
4.1.2
Critical trip . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Configuration register (read/write) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.2.1
Event thresholds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.2.2
Interrupt mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.2.3
Comparator mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.2.4
Shutdown mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.2.5
Event output pin functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Temperature register (read-only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
4.3.1
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Temperature format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
4.4
Temperature trip point registers (r/w) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
4.5
Manufacturer ID register (read-only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
4.6
Device ID and device revision ID register (read-only) . . . . . . . . . . . . . . . 25
STTS424
Contents
5
Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
6
DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
7
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
8
Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
9
Package marking information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
10
Landing pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
11
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
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List of tables
STTS424
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Table 18.
Table 19.
Table 20.
Table 21.
Table 22.
Table 23.
Table 24.
Table 25.
Table 26.
Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
AC SMBus and I2C compatibility timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Temperature sensor registers summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Pointer register format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Pointer register select bits (type, width, and default values). . . . . . . . . . . . . . . . . . . . . . . . 15
Capability register format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Capability register bit definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Configuration register format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Configuration register bit definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Hysteresis as applied to temperature movement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Legend for Figure 9: Event output boundary timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Temperature register format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Temperature register bit definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Temperature trip point register format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Alarm temperature upper boundary register format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Alarm temperature lower boundary register format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Critical temperature register format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Manufacturer ID register format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Device ID and device revision ID register format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Operating and AC measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
DC and AC characteristics - temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
TDFN8 – 8-lead thin dual flat, no-lead (2 mm x 3 mm) mechanical data (DN) . . . . . . . . . . 30
Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Parameters for landing pattern - TDFN package (DN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
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STTS424
List of figures
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
TDFN8 connections (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
SMBus/I2C write to pointer register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
SMBus/I2C write to pointer register, followed by a read data word. . . . . . . . . . . . . . . . . . . 11
SMBus/I2C write to pointer register, followed by a write data word . . . . . . . . . . . . . . . . . . 12
SMBus/I2C timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Hysteresis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Event output boundary timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
TDFN8 – 8-lead thin dual flat, no-lead (2 mm x 3 mm) package outline (DN) . . . . . . . . . . 30
Device topside marking information (TDFN-8L) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Landing pattern - TDFN package (DN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
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Description
1
STTS424
Description
The STTS424 is targeted for DIMM modules in mobile personal computing platforms
(laptops), server memory modules, and other industrial applications. The thermal sensor
(TS) in the STTS424 is fully compliant with the JEDEC specification which defines memory
module thermal sensors requirements for mobile platforms.
The TS provides space as well as cost savings for mobile and server platform dual inline
memory modules (DIMM) manufacturers as it is packaged in the compact 2 mm x 3 mm
(height 0.80 mm) 8-lead TDFN package which is compliant to JEDEC MO-229, variation
WCED-3.
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The temperature sensor includes a band gap-based temperature sensor and 10-bit analogto-digital converter (ADC) which monitor and digitize the temperature to a resolution of up to
0.25°C. The typical accuracies over these temperature ranges are:
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±3°C (max) over the full temperature measurement range of –40°C to 125°C
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±2°C in the +40°C to +125°C temperature range and
●
±1°C in the +75°C to +95°C temperature range
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The temperature sensor in the STTS424 is specified for operating at supply voltages from
2.7 V to 3.6 V. Operating at 3.3 V, the supply current is 100 µA (typ).
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The on-board sigma delta ADC converts the measured temperature to a digital value that is
calibrated in °C. For Fahrenheit applications, a lookup table or conversion routine is
required. The STTS424 is factory-calibrated and requires no external components to
measure temperature.
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The digital temperature sensor component has user-programmable registers that provide
the capabilities for DIMM temperature-sensing applications. The open drain event output pin
is active when the monitoring temperature exceeds a programmable limit, or it falls above or
below an alarm window. The user has the option to set the event output as a critical
temperature output. This pin can be configured to operate in either a comparator mode for
thermostat operation or in interrupt mode.
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STTS424
2
Serial communications
Serial communications
The STTS424 has a simple 2-wire SMBus/I2C-compatible digital serial interface which
allows the user to access the data in the temperature register at any time. It communicates
via the serial interface with a master controller which operates at speeds of up to 400 kHz. It
also gives the user easy access to all of the STTS424 registers in order to customize device
operation.
2.1
Device type identifier (DTI) code
The JC42.4 temperature sensor has its own unique I2C address, which ensures that there
are no compatibility or data translation issues. The DTI code is the unique 4-bit address,
'0011'.
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The full I2C address consists of the unique DTI code and 3 bits determined by the A0, A1,
and A2 pins. This allows up to 8 unique addresses, hence 8 STTS424 devices may be
connected on the same bus.
Figure 1.
Logic diagram
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VDD
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SDA(1)
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EVENT(1)
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SCL
A2
A1
A0
STTS424
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VSS
AI12947
1. SDA and EVENT are open drain.
Table 1.
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Signal names
Pin
Symbol
Description
1
A0
Serial bus address selection pin. Can be tied to VSS or VDD.
Input
2
A1
Serial bus address selection pin. Can be tied to VSS or VDD.
Input
3
A2
Serial bus address selection pin. Can be tied to VSS or VDD.
Input
4
VSS
Supply ground
5
SDA(1)
Serial data
Input/output
6
SCL
Serial clock
Input
Event output pin. Open drain and active-low.
Output
7
EVENT
8
VDD
(1)
Direction
Supply power (2.7 V to 3.6 V)
1. SDA and EVENT are open drain.
See Section 2.2: Pin descriptions on page 9 for details.
7/36
Serial communications
Figure 2.
STTS424
TDFN8 connections (top view)
A0
A1
A2
GND
8
7
6
5
1
2
3
4
VDD
EVENT(1)
SCL
SDA(1)
AI12262
1. SDA and EVENT are open drain.
Figure 3.
Block diagram
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8
VDD
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Temperature
Sensor
Logic Control
Comparator
Timing
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Configuration
Register
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Upper
Register
Lower
Register
Temperature
Register
Critical
Register
Manufacturer
ID
Address Pointer
Register
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ADC
Capability
Register
EVENT
Device ID/
Revision
1
2
3
SCL
A0
A1
A2
6
SMBus/I2C
Interface
SDA
5
VSS
4
AI12948
8/36
STTS424
Serial communications
2.2
Pin descriptions
2.2.1
A0, A1, A2
A2, A1, and A0 are selectable address pins for the 3 LSBs of the I2C interface address.
They can be set to VDD or GND to provide 8 unique address selections.
2.2.2
VSS (ground)
This is the reference for the power supply. It must be connected to system ground.
2.2.3
SDA (open drain)
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This is the serial data input/output pin.
2.2.4
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SCL
This is the serial clock input pin.
2.2.5
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EVENT (open drain)
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This output pin is open drain and active-low and functions as an alert interrupt.
2.2.6
VDD (power)
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This is the supply voltage pin, and ranges from +2.7 V to +3.6 V.
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Operation
3
STTS424
Operation
The STTS424 TS continuously monitors the ambient temperature and updates the
temperature data registers at least eight times per second. Temperature data is latched
internally by the device and may be read by software from the bus host at any time.
The SMBus/I2C slave address selection pins allow up to 8 such devices to co-exist on the
same bus. This means that up to 8 memory modules can be supported, given that each
module has one such slave device address slot.
After initial power-on, the configuration registers are set to the default values. The software
can write to the configuration register to set bits per the bit definitions in Section 3.1:
SMBus/I2C communications.
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SMBus/I2C communications
3.1
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The registers in this device are selected by the pointer register. At power-up, the pointer
register is set to “00”, which is the capability register location. The pointer register latches
the last location it was set to. Each data register falls into one of three types of user
accessibility:
1.
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Read-only
2.
Write-only and
3.
WRITE/READ same address.
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A WRITE to this device will always include the address byte and the pointer byte. A WRITE
to any register other than the pointer register, requires two data bytes.
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Reading this device is achieved in one of two ways:
●
●
Note:
10/36
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If the location latched in the pointer register is correct (most of the time it is expected
that the pointer register will point to one of the read temperature registers because that
will be the data most frequently read), then the READ can simply consist of an address
byte, followed by retrieval of the two data bytes.
If the pointer register needs to be set, then an address byte, pointer byte, repeat start,
and another address byte will accomplish a READ.
The data byte transfers the MSB first. At the end of a READ, this device can accept either an
acknowledge (ACK) or no acknowledge (No ACK) status from the master. The No ACK
status is typically used as a signal for the slave that the master has read its last byte. This
device subsequently takes up to 125 ms to measure the temperature.
STTS424 does not initiate clock stretching which is an optional I2C bus feature.
STTS424
Figure 4.
Operation
SMBus/I2C write to pointer register
1
SCL
9
1
9
SDA
0
0
Start
by
Master
1
1
A2 A1 A0 R/W
0
0
0
0
0
D2 D1 D0
Pointer Byte
Address Byte
ACK
by
STTS424
ACK
by
STTS424
AI12264
Figure 5.
1
SCL
9
1
0
0
Start
by
Master
1
1
A2 A1 A0 R/W
SDA
(continued)
Repeat
Start
by
Master
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0
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A2 A1 A0 R/W
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0
0
D2 D1 D0
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ACK
by
STTS424
9
0
0
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Pointer Byte
Address Byte
1
SCL
(continued)
0
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9
SDA
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SMBus/I2C write to pointer register, followed by a read data word
D15
Address Byte
D14
D13
D12 D11 D10
D9
9
D8
MSB Data Byte
ACK
by
STTS424
ACK
by
STTS424
1
D7
9
D6
D5
D4
D3
D2
LSB Data Byte
ACK
by
Master
D1
D0
Stop
Cond.
No ACK
by
by
Master
Master
AI12265
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Operation
STTS424
SMBus/I2C write to pointer register, followed by a write data word
Figure 6.
1
SCL
9
1
9
SDA
0
0
1
Start
by
Master
1
A2 A1 A0 R/W
SDA
(continued)
0
0
0
0
D2 D1 D0
Pointer Byte
Address Byte
ACK
by
STTS424
ACK
by
STTS424
1
SCL
(continued)
0
D15
9
D14
D13
D12 D11 D10
D9
D8
1
D7
9
D6
MSB Data Byte
D5
D4
D2
LSB Data Byte
u
d
o
D1
r
P
e
ACK
by
STTS424
t
e
l
o
)
(s
D3
)
s
(
ct
D0
Stop
Cond.
No ACK
by
by
Master
STTS424
AI14012
s
b
O
SMBus/I2C slave sub-address decoding
3.2
The physical address for the TS is binary 0 0 1 1 A2 A1 A0 RW, whereas A2, A1, and A0
are the three slave sub-address pins, and the LSB “RW” is the READ/WRITE flag.
t
c
u
d
o
r
SMBus/I2C AC timing consideration
3.3
P
e
In order for this device to be both SMBus- and I2C-compatible, it complies to a subset of
each specification. These interoperability requirements which will enable this device to coexist with devices on either an SMBus or an I2C bus:
t
e
l
o
bs
O
Note:
12/36
●
The SMBus minimum clock frequency is required.
●
The 300 ns SMBus data hold time (THD:DAT) is required (see Figure 7 and Table 2 on
page 13).
●
The SMBus time-out is maximum 50 ms.
Since the voltage levels are specified only within 3.3 V ±10%, there are no compatibility
concerns with the SMBus/I2C DC specifications.
STTS424
Operation
Figure 7.
SMBus/I2C timing diagram
tR
tLOW
tF
SCL
VIH
VIL
tSU:STA
tHD:STA
tHIGH
tBUF
tHD:DAT
SDA
tSU:STO
tSU:DAT
VIH
VIL
P
S
S
P
)
s
(
ct
A12266
Table 2.
AC SMBus and I2C compatibility timings
Symbol
tBUF
tHD:STA
tSU:STA(1)
3.4
Max
Units
Bus free time between stop (P) and start (S) conditions
1.3
–
µs
Hold time after (repeated) start condition. After this period,
the first clock cycle is generated.
0.6
–
µs
Repeated start condition setup time
1.3
–
µs
0.6
–
µs
1.3
–
µs
–
300
ns
–
300
ns
100
–
ns
Clock high period
tLOW
Clock low period
)-
Clock/data fall time
tR
Clock/data rise time
e
t
e
ol
s
b
O
s
(
t
c
tF
u
d
o
Data setup time
Pr
tHD:DAT
Data hold time
300
–
ns
tSU:STO
Stop condition setup time
0.6
–
µs
SMBUS/I2C clock frequency
10
400
kHz
Bus timeout
25
50
ms
e
t
e
l
fSCL
b
O
Pr
Min
tHIGH
tSU:DAT
so
Parameter
u
d
o
ttimeout
1. For a restart condition, or following a WRITE cycle
SMBus timeout
The STTS424 supports the SMBus timeout feature. If the host holds SCL low for more than
25 ms, the STTS424 resets and releases the bus. This feature is turned on by default.
13/36
Temperature sensor registers
4
STTS424
Temperature sensor registers
The temperature sensor component is comprised of various user-programmable registers.
These registers are required to write their corresponding addresses to the Pointer register.
They can be accessed by writing to their respective addresses (see Table 3). Pointer
register Bits 7-3 must always be written to '0' (see Table 4). This must be maintained, as not
setting these bits to '0' may keep the device from performing to specifications.
The main registers include:
●
Capability register (read-only)
●
Configuration register (read/write)
●
Temperature register (read-only)
●
Temperature trip point registers (r/w), including
–
Alarm temperature upper boundary,
–
Alarm temperature lower boundary, and
–
Critical temperature.
●
Manufacturer ID register format
●
Device ID and device revision ID register format
)
s
(
ct
u
d
o
r
P
e
t
e
l
o
Note:
See Table 5 on page 15 for pointer register selection bit details.
Table 3.
Temperature sensor registers summary
Address (Hex)
Not applicable
Register name
)
(s
Address pointer
t
c
u
s
b
O
Power-on default
Undefined
00
Capability
B-grade only
0x002F
01
Configuration
02
Alarm temperature upper boundary trip
0x0000
03
Alarm temperature lower boundary trip
0x0000
0x0000
od
e
t
e
ol
Pr
04
Critical temperature trip
05
Temperature
06
Manufacturer’s ID
0x104A
07
Device ID/revision
0x0101
s
b
O
Table 4.
0x0000
Undefined
Pointer register format
MSB
LSB
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
0
0
0
0
0
P2
P1
P0
Pointer/register select bits
14/36
STTS424
Table 5.
Temperature sensor registers
Pointer register select bits (type, width, and default values)
Width
(bits)
Type
(R/W)
Default
state
(POR)
16
R
00 2F
Configuration
16
R/W
00 00
UPPER
Alarm temperature upper boundary
16
R/W
00 00
1
LOWER
Alarm temperature lower boundary
16
R/W
00 00
0
0
CRITICAL
Critical temperature
16
R/W
00 00
1
0
1
TEMP
Temperature
16
R
00 00
1
1
0
MANU
Manufacturer ID
16
R
1
1
1
ID
Device ID/revision
16
R
P2
P1
P0
0
0
0
CAPA
Thermal sensor capabilities
0
0
1
CONF
0
1
0
0
1
1
4.1
Name
Register description
B-grade only
u
d
o
)
s
(
ct
104A
01 01
r
P
e
Capability register (read-only)
This 16-bit register is read-only, and provides the TS capabilities which comply with the
minimum JEDEC 424.4 specifications (see Table 6 and Table 7 on page 16). The STTS424
provides temperatures at 0.25 resolution (10-bit).
4.1.1
t
e
l
o
Alarm window trip
)
(s
s
b
O
The device provides a comparison window with an upper temperature trip point in the alarm
upper boundary register, and a lower trip point in the alarm lower boundary register. When
enabled, the event output will be triggered whenever entering or exiting (crossing above or
below) the alarm window.
t
c
u
d
o
r
4.1.2
Critical trip
P
e
The device can be programmed in such a way that the event output is only triggered when
the temperature exceeds the critical trip point. The critical temperature setting is
programmed in the critical temperature register. When the temperature sensor reaches the
critical temperature value in this register, the device is automatically placed in comparator
mode, which means that the critical event output cannot be cleared by using software to set
the clear event bit.
s
b
O
t
e
l
o
15/36
Temperature sensor registers
Table 6.
STTS424
Capability register format
Bit15
Bit14
Bit13
Bit12
Bit11
Bit10
Bit9
Bit8
RFU
RFU
RFU
RFU
RFU
RFU
RFU
RFU
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
RFU
RFU
VHV
TRES1
TRES0
Wider
range
Higher
precision
Alarm and
critical trips
C
Table 7.
Capability register bit definitions
Bit
Definition
Basic capability
– 0 = Alarm and critical trips turned OFF.
– 1 = Alarm and critical trips turned ON.
1
Accuracy
– 0 = Accuracy ±2°C over the active range and ±3°C over the monitoring range
(C - Grade).
– 1 = High accuracy ±1°C over the active range and ±2°C over the monitoring range
(B - Grade).
2
4:3
5
t
e
l
o
16/36
s
b
O
Range width
– 0 = Values lower than 0°C will be clamped and represented as binary value '0'.
– 1 = Temperatures below 0°C can be read and the Sign bit will be set accordingly.
)
(s
Temperature resolution
– 01 = This 10-bit value is fixed for STTS424, providing temperatures at 0.25°C resolution
(LSB).
t
c
u
(VHV) High voltage support for A0 (pin 1)
– 1 = STTS424 supports a voltage up to 10 volts on the A0 pin (default).
d
o
r
P
e
t
e
l
o
u
d
o
r
P
e
Reserved
15:6
These values must be set to '0'.
s
b
O
)
s
(
ct
0
STTS424
4.2
Temperature sensor registers
Configuration register (read/write)
The 16 bit Configuration register stores various configuration modes that are used to set up
the sensor registers and configure according to application and JEDEC 42.4 requirements
(see Table 8 on page 17 and Table 9 on page 18).
4.2.1
Event thresholds
All event thresholds use hysteresis as programmed in register address 0x01 (bits 10 through
9) to be set when they de-assert.
4.2.2
Interrupt mode
)
s
(
ct
The interrupt mode allows an event to occur where software may write a '1' to the clear
event bit (bit 5) to de-assert the event Interrupt output until the next trigger condition occurs.
4.2.3
u
d
o
Comparator mode
r
P
e
Comparator mode enables the device to be used as a thermostat. READs and WRITEs on
the device registers will not affect the event output in comparator mode. The event signal will
remain asserted until temperature drops outside the range or is re-programmed to make the
current temperature “out of range”.
4.2.4
t
e
l
o
Shutdown mode
s
b
O
The STTS424 features a shutdown mode which disables all power-consuming activities
(e.g. temperature sampling operations), and leaves the serial interface active. This is
selected by setting shutdown bit (bit 8) to '1'. In this mode, the devices consume the
minimum current (ISHDN), as shown in Table 22 on page 28.
)
(s
t
c
u
Note:
Bit 8 cannot be set to '1' while bits 6 and 7 (the lock bits) are set to '1'.
d
o
r
The device may be enabled for continuous operation by clearing bit 8 to '0'. In shutdown
mode, all registers may be read or written to. Power recycling will also clear this bit and
return the device to continuous mode as well.
P
e
let
Table 8.
O
o
s
b
Configuration register format
Bit15
Bit14
Bit13
Bit12
Bit11
Bit10
Bit9
Bit8
RFU
RFU
RFU
RFU
RFU
Hysteresis
Hysteresis
Shutdown
mode
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
Critical
lock bit
Alarm
lock bit
Clear
event
Critical
event only
Event
polarity
Event
mode
Event output Event output
status
control
17/36
Temperature sensor registers
Table 9.
STTS424
Configuration register bit definitions
Bit
Definition
0
Event mode
– 0 = Comparator output mode (this is the default)
– 1 = Interrupt mode; when either of the lock bits is set, this bit cannot be altered until it is unlocked.
1
Event polarity
– 0 = Active-low (this is the default).
– 1 = Active-high; when either of the lock bits is set, this bit cannot be altered until it is unlocked.
2
Critical event only
– 0 = Event output on alarm or critical temperature event (this is the default).
– 1 = Event only if the temperature is above the value in the critical temperature register; when the alarm
window lock bit is set, this bit cannot be altered until it is unlocked.
3
Event output control
– 0 = Event output disabled (this is the default).
– 1 = Event output enabled; when either of the lock bits is set, this bit cannot be altered until it is unlocked.
4
Event status (read-only)(1)
– 0 = Event output condition is not being asserted by this device.
– 1 = Event output condition is being asserted by this device via the alarm window or critical trip event.
5
Clear event (write-only)(2)
– 0 = No effect
– 1 = Clears the active Event in Interrupt mode.
6
Alarm window lock bit
– 0 = Alarm trips are not locked and can be altered (this is the default).
– 1 = Alarm trip register settings cannot be altered. This bit is initially cleared. When set, this bit returns a
logic '1' and remains locked until cleared by an internal power-on reset. These bits can be written to with a
single WRITE, and do not require double WRITEs.
7
Critical trip lock bit
– 0 = Critical trip is not locked and can be altered (this is the default).
– 1 = Critical trip register settings cannot be altered. This bit is initially cleared. When set, this bit returns a
logic '1' and remains locked until cleared by an internal power-on reset. These bits can be written to with a
single WRITE, and do not require double WRITEs.
)
s
(
ct
u
d
o
)
(s
r
P
e
t
e
l
o
s
b
O
t
c
u
d
o
r
P
e
t
e
l
o
Shutdown mode
– 0 = TS is enabled (this is the default).
– 1 = Shutdown TS when the shutdown, device, and A/D converter are disabled in order to save power. No
event conditions will be asserted; when either of the lock bits is set, this bit cannot be altered until it is
unlocked. However, it can be cleared at any time.
s
b
O
8
Hysteresis enable(3) (see Figure 8 and Table 10)
– 00 = Hysteresis is disabled.
10:9 – 01 = Hysteresis is enabled at 1.5°C.
– 10 = Hysteresis is enabled at 3°C.
– 11 = Hysteresis is enabled at 6°C.
1. The actual incident causing the event can be determined from the read temperature register. Interrupt events can be
cleared by writing to the clear event bit (writing to this bit will have no effect on overall device functioning.
2. Writing to this register has no effect on overall device functioning in comparator mode. When read, this bit will always return
a logic '0' result.
3. Hysteresis is also applied to the EVENT pin functionality. When either of the lock bits is set, these bits cannot be altered.
18/36
STTS424
Temperature sensor registers
Figure 8.
Hysteresis
TH
TH - HYS
TL
TL - HYS
Below Window bit
)
s
(
ct
Above Window bit
u
d
o
AI12270
r
P
e
1. TU = Value stored in the alarm temperature upper boundary trip register.
2. TL = Value stored in the alarm temperature lower boundary trip register.
t
e
l
o
3. Hys = Absolute value of selected hysteresis.
Table 10.
Hysteresis as applied to temperature movement
s
b
O
Below alarm window bit
)-
Temperature
slope
s
(
t
c
Sets
Falling
u
d
o
Clears
Rising
Above alarm window bit
Temperature
threshold
Temperature
slope
Temperature
threshold
TL - HYS
Rising
TH
TL
Falling
TH - HYS
r
P
e
t
e
l
o
s
b
O
19/36
Temperature sensor registers
4.2.5
STTS424
Event output pin functionality
The EVENT pin is an open drain output and requires a pull-up resistor to VDD on the system
motherboard or incorporated into the master controller.
Figure 9 shows the defined outputs of the EVENT correspondent to the temperature
change.
The event outputs can be programmed to be configured as either a comparator output or as
an interrupt. This is done by enabling the output control bit (bit 3) and setting the event mode
bit (bit 0). The output pin polarity can also be specified as active-high or active-low by setting
the event polarity bit (bit 1).
When the hysteresis bit (bits 10 and 9) is enabled, hysteresis may be used to sense
temperature movement around trigger points. For example, when using the “above alarm
window” bit (temperature register bit 14, see Table 12 on page 22) and hysteresis is set to
3°C, as the temperature rises, bit 14 is set (bit 14 = 1). The temperature is above the alarm
window and the temperature register contains a value that is greater than the value set in
the alarm temperature upper boundary register (see Table 15 on page 23).
)
s
(
ct
u
d
o
r
P
e
If the temperature decreases, bit 14 will remain set until the measured temperature is less
than or equal to the value in the alarm temperature upper boundary register minus 3°C (see
Figure 8 on page 19 and Table 10 on page 19 for details.
t
e
l
o
Similarly, when using the “below alarm window” bit (temperature register bit 13, see Table 12
on page 22) will be set to '0'. The temperature is equal to or greater than the value set in the
alarm temperature lower boundary register (see Table 16 on page 24). As the temperature
decreases, bit 13 will be set to '1' when the value in the temperature register is less than the
value in the alarm temperature lower boundary register minus 3°C (see Figure 8 on page 19
and Table 10 on page 19 for details).
)
(s
s
b
O
The device will retain the previous state when entering the shutdown mode. If the device
enters the shutdown mode while the EVENT pin is low, the shutdown current will increase
due to the additional event output pull-down current.
t
c
u
d
o
r
If in interrupt mode and the temperature reaches the critical temperature, the EVENT pin
remains asserted until the temperature drops below the critical limit minus hysteresis.
Note:
t
e
l
o
s
b
O
20/36
P
e
Hysteresis is also applied to the EVENT pin functionality. When either of the lock bits (bits 6
or 7) is set, these bits cannot be altered.
STTS424
Temperature sensor registers
Figure 9.
Event output boundary timings
TCRIT - THYS
TCRIT
TUPPER - THYS
TUPPER - THYS
TUPPER
TA
TLOWER - THYS
TLOWER
TLOWER - THYS
Event Output (active-low)
Comparator
)
s
(
ct
Interrupt
u
d
o
r
P
e
S/W Int. Clear
t
e
l
o
Critical
1
Table 11.
Note
Note:
s
b
O
35 7 6 4
2
AI12271
)
(s
Event output
TA bits
ct
du
Comparator Interrupt
Critical
15
14
13
TA ≥ TLOWER
H
L
H
0
0
0
TA ≥ TLOWER - THYS
L
L
H
0
0
1
TA > TUPPER
L
L
H
0
1
0
4
TA ≥ TUPPER - THYS
H
L
H
0
0
0
5
TA ≥ TCRIT
L
L
L
1
1
0
6
TA < TCRIT - THYS
L
H
H
0
1
0
ro
P
e
3
O
4
Event output boundary conditions
2
o
s
b
1 3
Legend for Figure 9: Event output boundary timings
1
let
2
7
When TA ≥ TCRIT and TA < TCRIT - THYS, the event output is in comparator mode and bit 0
of the configuration register (interrupt mode) is ignored.
Systems that use the active high mode for event output must be wired pont-to-point between
the STTS424 and the sensing controller. Wire-OR configurations should not be used with
active high EVENT since any device pulling the event output signal low will mask the other
devices on the bus. Also note that the normal state of EVENT in active high mode is a ‘0’
which will constantly draw power through the pull-up resistor.
21/36
Temperature sensor registers
4.3
STTS424
Temperature register (read-only)
This 16-bit, read-only register stores the temperature measured by the internal band gap TS
as shown inTable 12. The STTS424 meets the JEDEC JC42.4 mandatory 0.25°C resolution
requirement. When reading this register, the MSBs (bit 15 to bit 8) are read first, and then
the LSBs (bit 7 to bit 0) are read. The result is the current-sensed temperature. The data
format is 2s complement with one LSB = 0.25°C. The MSB has a 128°C resolution.
The trip status bits represent the internal temperature trip detection, and are not affected by
the status of the event or configuration bits (e.g. event output control or clear event). If
neither of the above or below values are set (i.e. both are 0), then the temperature is exactly
within the user-defined alarm window boundaries.
4.3.1
)
s
(
ct
Temperature format
The 16-bit value used in the trip point set and temperature read-back registers is 2s
complement, with the LSB equal to 0.0625°C (see Table 13). For example:
1.
a value of 019Ch will represent 25.75°C,
2.
a value of 07C0h will represent 124°C, and
3.
a value of 1E74h will represent –24.75°C
u
d
o
r
P
e
t
e
l
o
The 0.0625°C resolution is optional. Supporting a resolution of at least 0.25°C is mandatory.
All unused resolution bits will be set to zero. The MSB will have a resolution of 128°C. The
STTS424 supports the 0.25°C/LSB only.
s
b
O
The upper 3 bits indicate trip status based on the current temperature, and are not affected
by the event output status.
Table 12.
t
c
u
Sign
MSB
Bit
15
Bit
14
Above
critical
input(1)
Above
alarm
window(1)
O
d
o
r
P
e
let
o
s
b
0
)
(s
Temperature register format
Bit
13
Bit
12
Bit Bit Bit Bit Bit Bit Bit Bit Bit
11 10 9
8
7
6
5
4
3
Below
alarm
window(1)
0
0
Bit
0
0
0
0
0
1
1
1
1
1
0
0
0
0
0
0
07C0 h
Example hex value of 1C00 corresponds to –40°C (10-bit)
0
1. See Table 13 for explanation.
22/36
Bit
1
Example hex value of 07C0 corresponds to 124°C (10-bit)
Flag bits
0
Bit
2
Temperature
Flag bits
0
LSB
1
1
1
0
1
1
0
0
0
0
0
0
0
1C00 h
STTS424
Temperature sensor registers
Table 13.
Temperature register bit definitions
Bit
4.4
Definition with hysteresis = 0
13
Below (temperature) alarm window
– 0 = Temperature is equal to or above the alarm window lower boundary temperature.
– 1 = Temperature is below the alarm window.
14
Above (temperature) alarm window
– 0 = Temperature is equal to or below the alarm window upper boundary temperature.
– 1 = Temperature is below the alarm window.
15
Above critical trip
– 0 = Temperature is below the critical temperature setting.
– 1 = Temperature is equal to or above the critical temperature setting.
)
s
(
ct
u
d
o
Temperature trip point registers (r/w)
r
P
e
The STTS424 alarm mode registers provide for 11-bit data in 2s compliment format. The
data provides for one LSB = 0.25°C. All unused bits in these registers are read as '0'.
t
e
l
o
The STTS424 has three temperature trip point registers (see Table 14):
Note:
●
Alarm temperature upper boundary threshold (Table 15),
●
Alarm temperature lower boundary threshold (Table 16), and
●
Critical temperature trip point value (Table 17).
If the upper or lower boundary threshold values are being altered in-system, all interrupts
should be turned off until a known state can be obtained to avoid superfluous interrupt
activity.
Table 14.
let
0
o
s
b
0
)
(s
1
t
c
u
Temperature trip point register format
od
r
P
e
P2
O
s
b
O
Width
(bits)
Type
(R/W)
Default
state
(POR)
Alarm temperature upper boundary
16
R/W
00 00
Alarm temperature lower boundary
16
R/W
00 00
16
R/W
00 00
P1
P0
1
0
UPPER
1
1
LOWER
0
0
CRITICAL Critical temperature
Table 15.
Name
Register description
Alarm temperature upper boundary register format
Sign
MSB
Bit
15
Bit
14
Bit
13
0
0
0
Bit
12
LSB
Bit
11
Bit
10
Bit
9
Bit
8
Bit
7
Bit
6
Bit
5
Bit
4
Alarm window upper boundary temperature
Bit
3
Bit
2
Bit
1
Bit
0
0
0
23/36
Temperature sensor registers
Table 16.
STTS424
Alarm temperature lower boundary register format
Sign
MSB
Bit
15
Bit
14
Bit
13
0
0
0
Table 17.
Bit
12
LSB
Bit
11
Bit
10
Bit
9
Bit
8
Bit
7
Bit
6
Bit
5
Bit
4
Bit
3
Alarm window lower boundary temperature
Bit
1
Bit
0
0
0
Critical temperature register format
Sign
MSB
Bit
15
Bit
14
Bit
13
0
0
0
)
s
(
ct
Bit
12
LSB
Bit
11
Bit
10
Bit
9
Bit
8
Bit
7
Bit
6
Bit
5
Critical temperature trip point
e
t
e
ol
4.5
Bit
2
Bit
4
Bit
3
Bit
2
u
d
o
Pr
Bit
1
Bit
0
0
0
Manufacturer ID register (read-only)
s
b
O
The manufacturer’s ID (programmed value 104Ah) in this register is the STMicroelectronics
identification provided by the Peripheral Component Interconnect Special Interest Group
(PCiSIG).
Table 18.
Bit15
o
s
b
O
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0
Bit13
Bit12
Bit11
Bit10
Bit9
Bit8
0
1
0
0
0
0
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
1
0
0
1
0
1
0
u
d
o
r
P
e
let
ct
Bit14
0
Bit7
)
(s
Manufacturer ID register format
0
STTS424
4.6
Temperature sensor registers
Device ID and device revision ID register (read-only)
The device IDs and device revision IDs are maintained in this register. The register format is
shown in Table 19. The device IDs and device revision IDs are currently '0' and will be
incremented whenever an update of the device is made.
Table 19.
Device ID and device revision ID register format
Bit15
Bit14
Bit13
Bit12
Bit11
Bit10
Bit9
Bit8
0
0
0
0
0
0
0
1
Device ID
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
0
0
0
0
0
0
du
)
s
(
ct
Bit7
Device revision ID
e
t
e
ol
)
(s
0
Bit0
1
o
r
P
s
b
O
t
c
u
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e
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o
s
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Maximum ratings
5
STTS424
Maximum ratings
Stressing the device above the ratings listed in the absolute maximum ratings table may
cause permanent damage to the device. These are stress ratings only and operation of the
device at these or any other conditions above those indicated in the operating sections of
this specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability. Refer also to the STMicroelectronics SURE
Program and other relevant quality documents.
Table 20.
Absolute maximum ratings
Symbol
TSTG
Parameter
Value
TSLD(1)
Storage temperature
Unit
)
s
(
t
–60 to 150
Lead solder temperature for 10 seconds
°C
uc
260
od
°C
VIO
Input or output voltage - all pins
VDD
Supply voltage
VSS – 0.3 to 6.5
VOUT
Output voltage
VDD + 0.5
V
IO
Output current
10
mA
PD
Power dissipation
320
mW
θJA
Thermal resistance
130
°C/W
VSS – 0.3 to VDD + 0.5
e
t
e
l
O
)
o
s
b
Pr
V
V
1. Reflow at peak temperature of 255°C to 260°C for < 30 seconds (total thermal budget not to exceed 180°C
for between 90 to 150 seconds).
s
(
t
c
u
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STTS424
6
DC and AC parameters
DC and AC parameters
This section summarizes the operating measurement conditions, and the dc and ac
characteristics of the device. The parameters in the DC and AC characteristics tables that
follow, are derived from tests performed under the measurement conditions summarized in
Table 21: Operating and AC measurement conditions. Designers should check that the
operating conditions in their circuit match the operating conditions when relying on the
quoted parameters.
Table 21.
Operating and AC measurement conditions
Parameter
Conditions
VDD supply voltage - temperature sensor
2.7 to 3.6
Operating temperature
–40 to 125
Input rise and fall times
≤5
)
s
(
ct
u
d
o
Pr
Unit
V
°C
ns
Input pulse voltages
0.2 to 0.8VDD
V
Input and output timing reference voltages
0.3 to 0.7VDD
V
)
(s
e
t
e
ol
s
b
O
t
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DC and AC parameters
Table 22.
DC and AC characteristics - temperature sensor
Sym
VDD
STTS424
Test condition(1)
Description
Supply voltage
Min
Typ(2)
Max
Unit
2.7
3.3
3.6
V
100
200
µA
VDD supply current, active
temperature conversions
IDD
SCL/SDA = VDD
VDD supply current,
communication only
(no conversions)
100 kHz
40
µA
400 kHz
100
µA
IDD1
Shutdown mode supply current,
serial port inactive
DN package(3) at 125°C
ISINK
SMBUS output low sink current
SDA forced to 0.6 V
IIH, IIL
Input/output leakage current
VPOR
Power on reset (POR) threshold
1.0
+40°C < TA < +125°C
Conversion time
THYS
Hysteresis
VOL1
Low level voltage EVENT
VIL
CIN
)-
s
(
t
c
u
d
o
r
P
e
fSCL
s
b
O
±1.0
°C
±1.0
±2.0
°C
ete
±2.0
±3.0
°C
0.25
°C/L
SB
10
bits
125
ms
o
r
P
10-bit
Default value
500
3.0 V ≤ VDD ≤ 3.6 V;
EVENT;
IOL = 2.1 mA
Input logic high
3.0 V ≤ VDD ≤ 3.6 V;
SCL, SDA
Input logic low
3.0 V ≤ VDD ≤ 3.6 V;
SCL, SDA
t
e
l
o
s
b
O
±0.5
ol
10-bit temperature data
tCONV
VIH
µA
2.0
–40°C < TA < +125°C
SMBus/I2C interface
ct
du
VDD falling edge:
Resolution
2.1
SMBus/I C clock frequency
tTIMEOUT SMBus timeout
Allowable voltage on pin A0
LAO
Leakage on pin A0 in
overvoltage state
VOL2
Low level voltage SDA
0.8
10
400
kHz
25
50
ms
10
V
µA
0.6
1. Guaranteed operating temperature for DN package: TA = –40°C to 125°C; VDD = 2.7 V to 3.6 V (except where noted).
2. Typical numbers taken at VDD = 3.3 V, TA = 25°C.
3. TDFN package max 0.80 mm height.
28/36
V
pF
500
IOL = 6 mA
V
V
5
2
V
mV
0.4
SMBus/I2C Input capacitance
VHV
(s)
mA
±2
Accuracy for corresponding
range 2.7V ≤ VDD ≤ 3.6V
µA
6
+75°C < TA < +95°C
B-grade
3.0
V
STTS424
7
Package mechanical data
Package mechanical data
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK® is an ST trademark.
)
s
(
ct
u
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P
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o
)
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Package mechanical data
STTS424
Figure 10. TDFN8 – 8-lead thin dual flat, no-lead (2 mm x 3 mm) package outline (DN)(a)
)
s
(
ct
u
d
o
r
P
e
t
e
l
o
bs
Table 23.
O
)
s
(
t
c
Typ
Max
Min
Typ
Max
0.75
0.80
0.028
0.030
0.031
0.00
0.05
0.000
0.000
0.002
TDFN8 – 8-lead thin dual flat, no-lead (2 mm x 3 mm) mechanical data (DN)(1)
u
d
o
Sym
Min
Pr
A
0.70
A1
0.00
e
t
e
ol
A3
mm
inches
0.20
0.005
b
0.20
0.25
0.30
0.008
0.010
0.012
D
1.95
2.00
2.05
0.075
0.078
0.079
D2
1.35
1.40
1.45
0.053
0.055
0.057
E
2.95
3.00
3.05
0.116
0.118
0.120
E2
1.25
1.30
1.35
0.049
0.051
0.053
s
b
O
e
L
0.50
0.30
0.35
ddd
1. JEDEC MO-229, variation WCED-3 proposal
a. JEDEC MO-229, variation WCED-3 proposal
30/36
DA_ME
0.020
0.40
0.08
0.012
0.014
0.016
0.003
STTS424
8
Part numbering
Part numbering
Table 24.
Ordering information scheme
Example:
STTS424
B
DN
3
F
Device type
STTS424
Grade
)
s
(
ct
B: Maximum accuracy 75°C to 95°C = ± 1°C
u
d
o
Package
DN = TDFN8 (2 mm x 3 mm) (0.80 mm max height)
r
P
e
t
e
l
o
Temperature range
3 = –40°C to 125°C
Shipping method
)
(s
s
b
O
F = ECOPACK® package, tape & reel packing
E = ECOPACK® package, tube packing
t
c
u
d
o
r
For other options, or for more information on any aspect of this device, please contact the
ST sales office nearest you.
P
e
t
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O
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Package marking information
9
STTS424
Package marking information
Figure 11. Device topside marking information (TDFN-8L)
424B
DN (1)
PYWW (2)
ai13910b
u
d
o
r
P
e
1. TDFN package identifier
DN = 0.80 mm (package height)
2. Traceability codes
P = Plant code
Y = Year
WW = Work Week
)
(s
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s
b
O
t
e
l
o
)
s
(
ct
STTS424
10
Landing pattern
Landing pattern
The landing pattern recommendations for the TDFN package (DN) are shown in Figure 12.
The preferred implementation with wide corner pads enhances device centering during
assembly, but a narrower option is defined for modules with tight routing requirements.
Figure 12. Landing pattern - TDFN package (DN)
e4
e2
e/2
e
)
s
(
ct
e/2
u
d
o
L
r
P
e
t
e
l
o
K
s
b
O
D2
E3
)
(s
D2/2
D2/2
E2
t
c
u
od
r
P
e
s
b
O
t
e
l
o
E3
E2/2
E2/2
K
L
b2
b
b
K2
K2
K2
b4
ai14000
33/36
Landing pattern
STTS424
Table 25 lists variations of landing pattern implementations, ranked as “preferred”, and
minimum acceptable” based on the JEDEC proposal.
Table 25.
Parameters for landing pattern - TDFN package (DN)
Dimension
Parameter
Description
Min
Nom
Max
D2
Heat paddle width
1.40
-
1.60
E2
Heat paddle height
1.40
-
1.60
E3
Heat paddle centerline to contact inner locus
1.00
-
-
L
Contact length
0.70
K
Heat paddle to contact keepout
0.20
K2
Contact to contact keepout
Contact centerline to contact centerline pitch for inner contacts
b
Contact width for inner contacts
e2
Landing pattern centerline to outer contact centerline, “minimum
acceptable” option(1)
b2
Corner contact width, “minimum acceptable option”(1)
ete
bs
ol
Landing pattern centerline to outer contact centerline, “preferred” option
b4
Corner contact width, “preferred” option(2)
)
s
(
ct
-O
1. Minimum acceptable option to be used when routing prevents preferred width contact.
u
d
o
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O
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-
-
-
-
0.50
-
0.25
-
0.30
-
0.50
-
0.25
-
0.30
-
0.60
-
0.45
-
0.50
u
d
o
Pr
e4
2. Preferred option to be used when possible.
0.80
0.20
e
)
s
(
ct
-
(2)
-
STTS424
11
Revision history
Revision history
Table 26.
Document revision history
Date
Revision
Changes
17-Apr-2007
1
Initial release.
09-May-2007
2
Updated Table 3, 5, 6, 7, 22, 23, and 24.
04-June-2007
3
Updated Table 22.
02-Jul-2007
4
Added POR threshold values to Table 22.
22-Oct-2008
5
Added TDFN package (cover page, Figure 10, Table 23) and landing
pattern recommendations (Figure 12, Table 25); updated Section 1,
Section 4.3.1; Table 2, 3, 5, 7, 11, 19, 20, 22, 25, and Figure 2, 4, 5,
11; added Figure 6; removed all TSSOP8 and DFN8 package
references throughout datasheet.
01-Apr-2009
6
Updated Features on cover page, Section 3.1, Section 3.3,
Section 4.2.5, Section 6, Table 3, 5, 9, 12, 22.
)
s
(
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e
t
e
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o
)
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STTS424
)
s
(
ct
Please Read Carefully:
u
d
o
Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the
right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any
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r
P
e
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t
e
l
o
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)
(s
s
b
O
UNLESS OTHERWISE SET FORTH IN ST’S TERMS AND CONDITIONS OF SALE ST DISCLAIMS ANY EXPRESS OR IMPLIED
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t
c
u
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d
o
r
P
e
t
e
l
o
Resale of ST products with provisions different from the statements and/or technical features set forth in this document shall immediately void
any warranty granted by ST for the ST product or service described herein and shall not create or extend in any manner whatsoever, any
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s
b
O
ST and the ST logo are trademarks or registered trademarks of ST in various countries.
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