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STU13N65M2

STU13N65M2

  • 厂商:

    STMICROELECTRONICS(意法半导体)

  • 封装:

    TO-251-3

  • 描述:

    MOSFET N-CH 650V 10A IPAK

  • 数据手册
  • 价格&库存
STU13N65M2 数据手册
STP13N65M2, STU13N65M2 N-channel 650 V, 0.37 Ω typ.,10 A MDmesh™ M2 Power MOSFETs in TO-220 and IPAK packages Datasheet - production data Features Order code TAB VDS RDS(on) max ID 650 V 0.43Ω 10A STP13N65M2 TAB STU13N65M2 3 2 1 3 1 TO-220 • Extremely low gate charge 2 • Excellent output capacitance (Coss) profile IPAK • 100% avalanche tested • Zener-protected Applications Figure 1. Internal schematic diagram , TAB • Switching applications Description These devices are N-channel Power MOSFETs developed using MDmesh™ M2 technology. Thanks to their strip layout and improved vertical structure, the devices exhibit low on-resistance and optimized switching characteristics, rendering them suitable for the most demanding high efficiency converters. AM15572v1 Table 1. Device summary Order code Marking STP13N65M2 Package TO-220 13N65M2 STU13N65M2 December 2014 This is information on a product in full production. Packaging Tube IPAK DocID026894 Rev 1 1/16 www.st.com Contents STP13N65M2, STU13N65M2 Contents 1 Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2.1 Electrical characteristics (curves) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 3 Test circuits 4 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 5 2/16 .............................................. 9 4.1 TO-220, STP13N65M2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 4.2 IPAK, STU13N65M2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 DocID026894 Rev 1 STP13N65M2, STU13N65M2 1 Electrical ratings Electrical ratings Table 2. Absolute maximum ratings Symbol Parameter Gate-source voltage VGS Value Unit ± 25 V ID Drain current (continuous) at TC = 25 °C 10 A ID Drain current (continuous) at TC = 100 °C 6.3 A IDM(1) Drain current (pulsed) 40 A PTOT Total dissipation at TC = 25 °C 110 W Peak diode recovery voltage slope 15 MOSFET dv/dt ruggedness 50 dv/dt(2) V/ns (3) dv/dt Tstg Storage temperature - 55 to 150 °C Tj Max. operating junction temperature 150 1. Pulse width limited by safe operating area. 2. ISD ≤ 10 A, di/dt ≤ 400 A/µs; VDS peak < V(BR)DSS, VDD= 400 V 3. VDS ≤ 520 V Table 3. Thermal data Value Symbol Parameter Unit TO-220 Rthj-case Thermal resistance junction-case max Rthj-amb Thermal resistance junction-ambient max IPAK 1.14 °C/W 62.5 100 Table 4. Avalanche characteristics Symbol Parameter Value Unit IAR Avalanche current, repetitive or not repetitive (pulse width limited by Tjmax) 1.8 A EAS Single pulse avalanche energy (starting Tj = 25 °C, ID = IAR; VDD = 50 V) 350 mJ DocID026894 Rev 1 3/16 16 Electrical characteristics 2 STP13N65M2, STU13N65M2 Electrical characteristics (TC = 25 °C unless otherwise specified) Table 5. On /off states Symbol V(BR)DSS Parameter Drain-source breakdown voltage IDSS Zero gate voltage drain current IGSS Gate-body leakage current Test conditions VGS = 0 V, ID = 1 mA Min. Typ. Max. 650 Unit V VGS = 0 V, VDS = 650 V 1 µA VGS = 0 V, VDS = 650 V, TC = 125 °C 100 µA VDS = 0 V, VGS = ± 25 V ±10 µA 3 4 V 0.37 0.43 Ω Min. Typ. Max. Unit - 590 - pF - 27.5 - pF - 1.1 - pF VGS(th) Gate threshold voltage VDS = VGS, ID = 250 µA RDS(on) Static drain-source on-resistance 2 VGS = 10 V, ID = 5 A Table 6. Dynamic Symbol Parameter Test conditions Ciss Input capacitance Coss Output capacitance Crss Reverse transfer capacitance Coss eq(1) Equivalent output capacitance VGS = 0 V, VDS = 0 to 520 V - 168.5 - pF RG Intrinsic gate resistance f = 1 MHz open drain - 6.5 - Ω Qg Total gate charge - 17 - nC - 3.3 - nC - 7 - nC Qgs Gate-source charge Qgd Gate-drain charge VDS = 100 V, f = 1 MHz, VGS = 0 V VDD = 520 V, ID = 10 A, VGS = 10 V, (see Figure 17) 1. Coss eq. is defined as a constant equivalent capacitance giving the same charging time as Coss when VDS increases from 0 to 80% VDSS Table 7. Switching times Symbol td(on) tr td(off) tf 4/16 Parameter Test conditions Turn-on delay time Rise time Turn-off delay time VDD = 325 V, ID = 5 A, RG = 4.7 Ω, VGS = 10 V (see Figure 16 and Figure 21) Fall time DocID026894 Rev 1 Min. Typ. Max. Unit - 11 - ns - 7.8 - ns - 38 - ns - 12 - ns STP13N65M2, STU13N65M2 Electrical characteristics Table 8. Source drain diode Symbol Parameter Test conditions Min. Typ. Max. Unit Source-drain current - 10 A ISDM (1) Source-drain current (pulsed) - 40 A VSD (2) Forward on voltage - 1.6 V ISD trr VGS = 0 V, ISD = 10 A Reverse recovery time Qrr Reverse recovery charge IRRM Reverse recovery current trr Reverse recovery time Qrr Reverse recovery charge IRRM Reverse recovery current ISD =10 A, di/dt = 100 A/µs VDD = 60 V (see Figure 18) ISD = 10 A, di/dt = 100 A/µs, VDD = 60 V, Tj = 150 °C (see Figure 18) - 312 ns - 2.7 µC - 17.5 A - 464 ns - 4.1 µC - 17.5 A 1. Pulse width limited by safe operating area. 2. Pulsed: pulse duration = 300 µs, duty cycle 1.5% DocID026894 Rev 1 5/16 16 Electrical characteristics 2.1 STP13N65M2, STU13N65M2 Electrical characteristics (curves) Figure 2. Safe operating area for TO-220 ,' $ *,3*$/6 Figure 3. Thermal impedance for TO-220 &* . į  6 RQ 2 /L SHU P DW LWH LR G QL E\ Q P WKL D[ VD 5 UH D ' LV į   —V —V į   =WK . 5 WK-F į W SϨ PV  7M ƒ& 7F ƒ& 6LQJOHSXOVH     WS 6,1*/(38/6(  9'6 9 Figure 4. Safe operating area for IPAK ,' $ į  į  į  PV *,3'$/6  Ϩ       WS V Figure 5. Thermal impedance for IPAK *& . —V  Q į  R —V '6 2S /LP HUDW LWH LRQ G LQ E\ WK P LV D[ DUH 5 D L V     PV 7M ƒ& 7& ƒ& 6LQJOHSXOVH      9'6 9 *,3*$/6 9*6 9  =WK . 5 WK-F į W SϨ    6LQJOHSXOVH PV Figure 6. Output characteristics ,' $         WS   Ϩ  WS V Figure 7. Transfer characteristics ,' $  *,3*$/6  9'6 9 9        6/16  9     9'6 9   DocID026894 Rev 1     9*6 9 STP13N65M2, STU13N65M2 Electrical characteristics Figure 8. Normalized VBR(DSS) vs temperature 9 %5 '66 *,3')65 QRUP Figure 9. Static drain-source on-resistance 5'6 RQ  *,3')65 ȍ 9*6 9     ,' P$            7- ƒ& Figure 10. Gate charge vs gate-source voltage 9*6 9  *,3*$/6 9'6 9  9'6              ,' $ Figure 11. Capacitance variations *,3*$/6 & S)  &LVV  9'' 9 ,' $     &RVV          4J Q& Figure 12. Normalized gate threshold voltage vs temperature 9*6 WK  *,3')65 QRUP &UVV     9'6 9 Figure 13. Normalized on-resistance vs temperature *,3')65 5'6 RQ  QRUP   ,' —$                7- ƒ&   DocID026894 Rev 1 9*6 9     7- ƒ& 7/16 16 Electrical characteristics STP13N65M2, STU13N65M2 Figure 14. Source-drain diode forward characteristics 96' 9 *,3*$/6 7- ƒ& Figure 15. Output capacitance stored energy (266 —- *,3*$/6    7- ƒ&   7- ƒ&      8/16       ,6' $   DocID026894 Rev 1       9'6 9 STP13N65M2, STU13N65M2 3 Test circuits Test circuits Figure 16. Switching times test circuit for resistive load Figure 17. Gate charge test circuit 9'' 9 μF VDD VD VGS ,* &2167 9L 9 9*0$; RG Nȍ Q) 3.3 μF 2200 RL Nȍ  —) D.U.T. ȍ '87 Nȍ 9* PW Nȍ Nȍ 3: $0Y AM01468v1 Figure 18. Test circuit for inductive load switching and diode recovery times A A Figure 19. Unclamped inductive load test circuit L A D G D.U.T. FAST DIODE B B S VD L=100μH 3.3 μF B 25 Ω 1000 μF D VDD 2200 μF 3.3 μF VDD ID G RG S Vi D.U.T. Pw AM01470v1 AM01471v1 Figure 20. Unclamped inductive waveform Figure 21. Switching time waveform 9 %5 '66 WRQ 9' WG RQ WRII WU WG RII   ,'0    ,' 9'' WI 9'' $0Y 9*6  DocID026894 Rev 1  9'6  $0Y 9/16 16 Package mechanical data 4 STP13N65M2, STU13N65M2 Package mechanical data In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. 10/16 DocID026894 Rev 1 STP13N65M2, STU13N65M2 4.1 Package mechanical data TO-220, STP13N65M2 Figure 22. TO-220 type A drawing BW\SH$B5HYB7 DocID026894 Rev 1 11/16 16 Package mechanical data STP13N65M2, STU13N65M2 Table 9. TO-220 type A mechanical data mm Dim. Min. Typ. A 4.40 4.60 b 0.61 0.88 b1 1.14 1.70 c 0.48 0.70 D 15.25 15.75 D1 12/16 Max. 1.27 E 10 10.40 e 2.40 2.70 e1 4.95 5.15 F 1.23 1.32 H1 6.20 6.60 J1 2.40 2.72 L 13 14 L1 3.50 3.93 L20 16.40 L30 28.90 ∅P 3.75 3.85 Q 2.65 2.95 DocID026894 Rev 1 STP13N65M2, STU13N65M2 4.2 Package mechanical data IPAK, STU13N65M2 Figure 23. IPAK (TO-251) drawing 0068771_L DocID026894 Rev 1 13/16 16 Package mechanical data STP13N65M2, STU13N65M2 Table 10. IPAK (TO-251) mechanical data mm. DIM min. typ. A 2.20 2.40 A1 0.90 1.10 b 0.64 0.90 b2 b4 0.95 5.20 B5 5.40 0.30 c 0.45 0.60 c2 0.48 0.60 D 6.00 6.20 E 6.40 6.60 e e1 2.28 4.40 H 14/16 max. 4.60 16.10 L 9.00 9.40 L1 0.80 1.20 L2 0.80 V1 10° DocID026894 Rev 1 1.00 STP13N65M2, STU13N65M2 5 Revision history Revision history Table 11. Document revision history Date Revision 19-Dec-2014 1 Changes First release. DocID026894 Rev 1 15/16 16 STP13N65M2, STU13N65M2 IMPORTANT NOTICE – PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement. Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers’ products. No license, express or implied, to any intellectual property right is granted by ST herein. Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners. Information in this document supersedes and replaces information previously supplied in any prior versions of this document. © 2014 STMicroelectronics – All rights reserved 16/16 DocID026894 Rev 1
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