STU1HN60K3

STD1HN60K3, STU1HN60K3 N-channel 600 V, 6.7 Ω typ., 1.2 A SuperMESH3™ Power MOSFET in DPAK and IPAK packages Datasheet − production data Features VDS RDS(on) max ID PTOT 600 V 8Ω 1.2 A 27 W Order codes STD1HN60K3 TAB TAB STU1HN60K3 3 3 1 2 • 100% avalanche tested 1 DPAK IPAK • Extremely high dv/dt capability • Gate charge minimized • Very low intrinsic capacitance • Improved diode reverse recovery characteristics Figure 1. Internal schematic diagram • Zener-protected D(2, TAB) Applications • Switching applications Description G(1) S(3) AM01476v1 These SuperMESH3™ Power MOSFETs are the result of improvements applied to STMicroelectronics’ SuperMESH™ technology, combined with a new optimized vertical structure. These devices boast an extremely low onresistance, superior dynamic performance and high avalanche capability, rendering them suitable for the most demanding applications. Table 1. Device summary Order codes Marking Package Packaging DPAK Tape and reel IPAK Tube STD1HN60K3 1HN60K3 STU1HN60K3 April 2013 This is information on a product in full production. DocID024422 Rev 1 1/19 www.st.com 19 Contents STD1HN60K3, STU1HN60K3 Contents 1 Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2.1 Electrical characteristics (curves) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 3 Test circuits 4 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 5 Packaging mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 6 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 2/19 .............................................. 9 DocID024422 Rev 1 STD1HN60K3, STU1HN60K3 1 Electrical ratings Electrical ratings Table 2. Absolute maximum ratings Symbol Parameter Value Unit VDS Drain- source voltage 600 V VGS Gate- source voltage ± 30 V (1) ID Drain current (continuous) at TC = 25 °C 1.2 A ID Drain current (continuous) at TC = 100 °C 0.76 A Drain current (pulsed) 4.8 A Total dissipation at TC = 25 °C 27 W IAR Avalanche current, repetitive or notrepetitive (pulse width limited by TJ max) 1.2 A EAS Single pulse avalanche energy (starting TJ = 25 °C, ID = IAR, VDD = 50 V) 60 mJ Peak diode recovery voltage slope 5 V/ns IDM (1) PTOT dv/dt(2) TJ Operating junction temperature Tstg Storage temperature °C -55 to 150 °C 1. Pulse width limited by safe operating area 2. ISD ≤ 1.2 A, di/dt ≤ 400 A/µs,VDS peak ≤ V(BR)DSS, VDD = 80% V(BR)DSS. Table 3. Thermal data Value Symbol Parameter Unit DPAK Rthj-case Thermal resistance junction-case max. Rthj-amb Thermal resistance junction-ambient max Rthj-pcb Thermal resistance junction-pcb max. DocID024422 Rev 1 IPAK 4.63 °C/W 100 50 °C/W °C/W 3/19 Electrical characteristics 2 STD1HN60K3, STU1HN60K3 Electrical characteristics (Tcase =25 °C unless otherwise specified) Table 4. On /off states Symbol V(BR)DSS Parameter Test conditions Drain-source breakdown voltage ID = 1 mA, VGS = 0 Min. Typ. Max. 600 Unit V IDSS Zero gate voltage VDS = 600 V drain current (VGS = 0) VDS = 600 V, TC=125 °C 1 50 µA µA IGSS Gate-body leakage current (VDS = 0) ±10 µA 3.75 4.5 V 6.7 8 Ω Min. Typ. Max. Unit - 140 - pF - 13 - pF - 2 - pF - 9 - pF - 6 - pF VGS = ± 20 V VGS(th) Gate threshold voltage VDS = VGS, ID = 50 µA RDS(on) Static drain-source onVGS = 10 V, ID = 0.6 A resistance 2 Table 5. Dynamic Symbol Parameter Ciss Input capacitance Coss Output capacitance Crss Reverse transfer capacitance Co(tr) (1) Equivalent capacitance time related Co(tr) (2) Equivalent capacitance energy related Test conditions VDS = 50 V, f = 1 MHz, VGS = 0 VDS = 0 to 480 V, VGS = 0 Rg Gate input resistance f=1 MHz open drain - 10 - Ω Qg Total gate charge - 9.5 - nC Qgs Gate-source charge - 1.5 - nC Qgd Gate-drain charge VDD = 480 V, ID = 1.2 A, VGS = 10 V (see Figure 16) - 6.5 - nC 1. Co(tr) is defined as a constant equivalent capacitance giving the same charging time as Coss when VDS increases from 0 to 80% VDS 2. Co(tr) is defined as a constant equivalent capacitance giving the same charging time as Coss when VDS increases from 0 to 80% VDS 4/19 DocID024422 Rev 1 STD1HN60K3, STU1HN60K3 Electrical characteristics Table 6. Switching times Symbol td(on) tr Parameter Test conditions Turn-on delay time VDD = 300 V, ID = 0.6 A, RG = 4.7 Ω, VGS = 10 V (see Figure 10) Rise time td(off) tf Turn-off-delay time Fall time Min. Typ. Max Unit - 7 - ns - 10 - ns - 23 - ns - 31 - ns Table 7. Source drain diode Symbol ISD ISDM (1) VSD (2) Parameter Test conditions Min. Typ. Max Unit Source-drain current - 1.2 A Source-drain current (pulsed) - 4.8 A 1.6 V Forward on voltage ISD = 1.2 A, VGS = 0 - trr Reverse recovery time - 180 ns Qrr Reverse recovery charge - 500 nC IRRM Reverse recovery current ISD = 1.2 A, di/dt = 100 A/µs VDD= 60 V (see Figure 11) - 5.6 A ISD = 1.2 A, di/dt = 100 A/µs VDD= 60 V TJ = 150 °C (see Figure 11) - 200 ns - 570 nC - 6 A trr Reverse recovery time Qrr Reverse recovery charge IRRM Reverse recovery current 1. Pulse width limited by safe operating area 2. Pulsed: pulse duration = 300 µs, duty cycle 1.5% Table 8. Gate-source Zener diode Symbol V(BR)GSO Parameter Test conditions Gate-source breakdown voltage IGS= ± 1 mA, ID=0 Min. Typ. 30 - Max. Unit - V The built-in back-to-back Zener diodes have been specifically designed to enhance not only the device’s ESD capability, but also to make them capable of safely absorbing any voltage transients that may occasionally be applied from gate to source. In this respect, the Zener voltage is appropriate to achieve efficient and cost-effective protection of device integrity. The integrated Zener diodes thus eliminate the need for external components. DocID024422 Rev 1 5/19 Electrical characteristics 2.1 STD1HN60K3, STU1HN60K3 Electrical characteristics (curves) Figure 2. Safe operating area Figure 3. Thermal impedance AM15647v1 ID (A) 10µs 1 n) (o DS Op Lim era ite tion d by in th m is a ax R re a is 100µs 0.1 1ms 10ms Tj=150°C Tc=25°C Single pulse 0.01 0.1 10 1 100 VDS(V) Figure 4. Output characteristics Figure 5. Transfer characteristics AM15648v1 ID (A) AM15649v1 ID (A) VGS=10V 7V 1.6 VDS=15V 1.6 1.2 1.2 6V 0.8 0.8 0.4 0.4 5V 0 0 4 8 12 16 Figure 6. Normalized BVDSS vs temperature AM15650v1 BVDSS (norm) 0 0 VDS(V) ID=1 mA 2 4 8 6 VGS(V) Figure 7. Static drain-source on-resistance RDS(on) (Ω) AM15651v1 VGS=10 V 9 1.10 8 1.05 7 1.00 6 0.95 5 0.90 0.85 -75 -50 -25 6/19 4 0 25 50 75 100 125 TJ(°C) DocID024422 Rev 1 3 0.4 0.5 0.6 0.7 0.8 0.9 1 1.1 1.2 ID(A) STD1HN60K3, STU1HN60K3 Electrical characteristics Figure 8. Gate charge vs gate-source voltage AM15652v1 VDS VGS (V) 10 (V) VDS=480V ID=1.2A VVDS DS Figure 9. Capacitance variations AM15653v1 C (pF) 500 8 400 6 300 4 200 2 100 Ciss 100 10 Coss Crss 0 0 4 2 6 1 0.1 0 Qg(nC) 8 Figure 10. Normalized gate threshold voltage vs temperature AM15654v1 VGS(th) (norm) 1 100 10 VDS(V) Figure 11. Normalized on-resistance vs temperature AM15655v1 RDS(on) (norm) ID=0.6 A VGS=10 A 1.10 2.5 ID=50µA 2.0 1.00 1.5 0.90 1.0 0.80 0.5 0.70 -75 -50 -25 0 25 50 75 100 125 Figure 12. Source-drain diode forward characteristics AM15656v1 25 50 75 100 125 TJ(°C) AM15657v1 Eoss(µJ) 1.0 TJ=-50°C 0.9 0.90 0.8 0.85 TJ=25°C 0.7 0.80 0.6 0.75 0.5 0.70 0.4 TJ=150°C 0.65 0.3 0.60 0.2 0.55 0.50 0.6 0 Figure 13. Output capacitance stored energy VSD (V) 0.95 0 -75 -50 -25 TJ(°C) 0.7 0.8 0.9 1 1.1 1.2 ISD(A) 0.1 0.0 0 DocID024422 Rev 1 200 400 600 VDS(V) 7/19 Electrical characteristics STD1HN60K3, STU1HN60K3 Figure 14. Maximum avalanche energy vs. starting TJ AM15708v1 EAS (mJ) VDD=50V ID=1.2 A 60 50 40 30 20 10 0 0 8/19 25 50 75 100 TJ(°C) DocID024422 Rev 1 STD1HN60K3, STU1HN60K3 3 Test circuits Test circuits Figure 15. Switching times test circuit for resistive load Figure 16. Gate charge test circuit VDD 12V 47kΩ 1kΩ 100nF 3.3 μF 2200 RL μF VGS IG=CONST VDD 100Ω Vi=20V=VGMAX VD RG 2200 μF D.U.T. D.U.T. VG 2.7kΩ PW 47kΩ 1kΩ PW AM01468v1 Figure 17. Test circuit for inductive load switching and diode recovery times A A D.U.T. FAST DIODE B B AM01469v1 Figure 18. Unclamped inductive load test circuit L A D G VD L=100μH S 3.3 μF B 25 Ω 1000 μF D VDD 2200 μF 3.3 μF VDD ID G RG S Vi D.U.T. Pw AM01470v1 AM01471v1 Figure 19. Unclamped inductive waveform Figure 20. Switching time waveform ton V(BR)DSS tdon VD toff tr tdoff tf 90% 90% IDM 10% ID VDD 10% 0 VDD VDS 90% VGS AM01472v1 0 DocID024422 Rev 1 10% AM01473v1 9/19 Package mechanical data 4 STD1HN60K3, STU1HN60K3 Package mechanical data In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. 10/19 DocID024422 Rev 1 STD1HN60K3, STU1HN60K3 Package mechanical data Table 9. DPAK (TO-252) mechanical data mm Dim. Min. Typ. Max. A 2.20 2.40 A1 0.90 1.10 A2 0.03 0.23 b 0.64 0.90 b4 5.20 5.40 c 0.45 0.60 c2 0.48 0.60 D 6.00 6.20 D1 E 5.10 6.40 6.60 E1 4.70 e 2.28 e1 4.40 4.60 H 9.35 10.10 L 1.00 1.50 (L1) 2.80 L2 0.80 L4 0.60 1.00 R V2 0.20 0° 8° DocID024422 Rev 1 11/19 Package mechanical data STD1HN60K3, STU1HN60K3 Figure 21. DPAK (TO-252) drawing 0068772_K 12/19 DocID024422 Rev 1 STD1HN60K3, STU1HN60K3 Package mechanical data Figure 22. DPAK footprint (a) Footprint_REV_K a. All dimensions are in millimeters DocID024422 Rev 1 13/19 Package mechanical data STD1HN60K3, STU1HN60K3 Table 10. IPAK (TO-251) mechanical data mm. DIM min. typ. A 2.20 2.40 A1 0.90 1.10 b 0.64 0.90 b2 b4 0.95 5.20 B5 5.40 0.30 c 0.45 0.60 c2 0.48 0.60 D 6.00 6.20 E 6.40 6.60 e e1 2.28 4.40 H 14/19 max. 4.60 16.10 L 9.00 9.40 L1 0.80 1.20 L2 0.80 V1 10° DocID024422 Rev 1 1.00 STD1HN60K3, STU1HN60K3 Package mechanical data Figure 23. IPAK (TO-251) drawing 0068771_K DocID024422 Rev 1 15/19 Packaging mechanical data 5 STD1HN60K3, STU1HN60K3 Packaging mechanical data Table 11. DPAK (TO-252) tape and reel mechanical data Tape Reel mm mm Dim. Dim. Min. Max. A0 6.8 7 A B0 10.4 10.6 B 1.5 12.1 C 12.8 1.6 D 20.2 G 16.4 50 B1 16/19 Min. Max. 330 13.2 D 1.5 D1 1.5 E 1.65 1.85 N F 7.4 7.6 T K0 2.55 2.75 P0 3.9 4.1 Base qty. 2500 P1 7.9 8.1 Bulk qty. 2500 P2 1.9 2.1 R 40 T 0.25 0.35 W 15.7 16.3 DocID024422 Rev 1 18.4 22.4 STD1HN60K3, STU1HN60K3 Packaging mechanical data Figure 24. Tape for DPAK (TO-252) 10 pitches cumulative tolerance on tape +/- 0.2 mm T P0 Top cover tape P2 D E F B1 W K0 B0 For machine ref. only including draft and radii concentric around B0 A0 P1 D1 User direction of feed R Bending radius User direction of feed AM08852v1 Figure 25. Reel for DPAK (TO-252) T REEL DIMENSIONS 40mm min. Access hole At slot location B D C N A Full radius Tape slot in core for tape start 25 mm min. width G measured at hub AM08851v2 DocID024422 Rev 1 17/19 Revision history 6 STD1HN60K3, STU1HN60K3 Revision history Table 12. Document revision history 18/19 Date Revision 09-Apr-2013 1 Changes First release. DocID024422 Rev 1 STD1HN60K3, STU1HN60K3 Please Read Carefully: Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale. Purchasers are solely responsible for the choice, selection and use of the ST products and services described herein, and ST assumes no liability whatsoever relating to the choice, selection or use of the ST products and services described herein. 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