STU7LN80K5

STU7LN80K5 N-channel 800 V, 0.95 Ω typ., 5 A MDmesh™ K5 Power MOSFET in a IPAK package Datasheet - production data Features TAB 2 • • • • • 3 1 IPAK Order code VDS RDS(on) max. ID STU7LN80K5 800 V 1.15 Ω 5A Industry’s lowest RDS(on) x area Industry’s best figure of merit (FoM) Ultra-low gate charge 100% avalanche tested Zener-protected Applications Figure 1: Internal schematic diagram • Switching applications Description This very high voltage N-channel Power MOSFET is designed using MDmesh™ K5 technology based on an innovative proprietary vertical structure. The result is a dramatic reduction in on-resistance and ultra-low gate charge for applications requiring superior power density and high efficiency. Table 1: Device summary Order code Marking Package Packing STU7LN80K5 7LN80K5 IPAK Tube January 2016 DocID028830 Rev 1 This is information on a product in full production. 1/12 www.st.com Contents STU7LN80K5 Contents 1 Electrical ratings ............................................................................. 3 2 Electrical characteristics ................................................................ 4 2.1 Electrical characteristics (curves) ...................................................... 6 3 Test circuits ..................................................................................... 8 4 Package information ....................................................................... 9 4.1 5 2/12 IPAK type C package information ..................................................... 9 Revision history ............................................................................ 11 DocID028830 Rev 1 STU7LN80K5 1 Electrical ratings Electrical ratings Table 2: Absolute maximum ratings Symbol VGS Parameter Unit ± 30 V ID Drain current (continuous) at TC = 25 °C 5 A ID Drain current (continuous) at TC = 100 °C 3.4 A Drain current (pulsed) 20 A (1) ID PTOT Gate-source voltage Value Total dissipation at TC = 25 °C 85 W dv/dt (2) Peak diode recovery voltage slope 4.5 V/ns dv/dt (3) MOSFET dv/dt ruggedness 50 V/ns - 55 to 150 °C Tstg Tj Storage temperature Operating junction temperature Notes: (1) Pulse width limited by safe operating area. (2) ISD ≤ 5 A, di/dt ≤100 A/μs; VDS peak ≤ V(BR)DSS, VDD = 400 V (3) VDS ≤ 640 V Table 3: Thermal data Symbol Parameter Value Unit Rthj-case Thermal resistance junction-case 1.47 °C/W Rthj-amb Thermal resistance junction-ambient 100 °C/W Value Unit Table 4: Avalanche characteristics Symbol Parameter IAR Avalanche current, repetetive or not repetetive (pulse width limited by Tjmax) 1.5 A EAS (Single pulse avalanche energy (starting Tj = 25 °C, ID = IAR; VDD = 50 V) 200 mJ DocID028830 Rev 1 3/12 Electrical characteristics 2 STU7LN80K5 Electrical characteristics TC = 25 °C unless otherwise specified Table 5: On/off states Symbol Parameter Test conditions V(BR)DSS Drain-source breakdown voltage IDSS Zero gate voltage Drain current IGSS VGS = 0 V, ID = 1 mA Min. Typ. Max. 800 Unit V VGS = 0 V, VDS = 800 V 1 µA VGS = 0 V, VDS = 800 V, TC = 125 °C 50 µA Gate-body leakage current VDS = 0 V, VGS = ±20 V ±10 µA VGS(th) Gate threshold voltage VDS = VGS, ID =100 µA 4 5 V RDS(on) Static drain-source onresistance VGS = 10 V, ID = 2.5 A 0.95 1.15 Ω Min. Typ. Max. Unit - 270 - pF - 22 - pF - 0.5 - pF - 17 - nC - 48 - nC 7.5 - Ω - 12 - nC - 2.6 - nC - 8.6 - nC 3 Table 6: Dynamic Symbol Ciss Parameter Test conditions Input capacitance Coss Output capacitance Crss Reverse transfer capacitance VDS= 100 V, f = 1 MHz, VGS = 0 V (1) Equivalent capacitance energy related Co(tr) (2) Equivalent capacitance time related RG Intrinsic gate resistance f = 1 MHz, open drain Qg Total gate charge Qgs Gate-source charge Qgd Gate-drain charge VDD = 640 V, ID = 5 A, VGS = 10 V (see Figure 15: "Test circuit for gate charge behavior") Co(er) VDS = 0 to 640 V, VGS = 0 V - Notes: (1) Energy related is defined as a constant equivalent capacitance giving the same stored energy as Coss when VDS increases from 0 to 80% VDSS (2) Time related is defined as a constant equivalent capacitance giving the same stored energy as Coss when VDS increases from 0 to 80% VDSS Table 7: Switching times Symbol td(on) tr td(off) tf 4/12 Parameter Turn-on delay time Rise time Turn-off-delay time Fall time Test conditions VDD = 400 V, ID = 2.5 A, RG = 4.7 Ω, VGS = 10 V (see Figure 14: "Test circuit for resistive load switching times" and Figure 19: "Switching time waveform") DocID028830 Rev 1 Min. Typ. Max. Unit - 9.3 - ns - 6.7 - ns - 23.6 - ns - 17.4 - ns STU7LN80K5 Electrical characteristics Table 8: Source drain diode Symbol ISD Test conditions Min. Typ. Max. Unit Source-drain current - 5 A (1) Source-drain current (pulsed) - 20 A (2) Forward on voltage - 1.6 V ISDM VSD Parameter ISD= 5 A, VGS = 0 V trr Reverse recovery time Qrr Reverse recovery charge IRRM Reverse recovery current trr Reverse recovery time Qrr Reverse recovery charge IRRM Reverse recovery current ISD = 5 A, di/dt = 100 A/µs, VDD = 60 V (see Figure 16: "Test circuit for inductive load switching and diode recovery times") ISD = 5 A, di/dt = 100 A/µs, VDD = 60 V, Tj = 150 °C (see Figure 16: "Test circuit for inductive load switching and diode recovery times") - 276 ns - 2.13 µC - 15.4 A - 402 ns - 2.79 µC - 13.9 A Notes: (1) (2) Pulse width is limited by safe operating area Pulsed: pulse duration = 300 µs, duty cycle 1.5% Table 9: Gate-source Zener diode Symbol V(BR)GSO Parameter Gate-source breakdown voltage Test conditions IGS = ±1 mA, ID = 0 A Min. 30 Typ. Max. - Unit V The built-in back-to-back Zener diodes are specifically designed to enhance the ESD performance of the device. The Zener voltage facilitates efficient and cost-effective device integrity protection,thus eliminating the need for additional external componentry. DocID028830 Rev 1 5/12 Electrical characteristics 2.2 6/12 STU7LN80K5 Electrical characteristics (curves) Figure 2: Safe operating area Figure 3: Thermal impedance Figure 4: Output characteristics Figure 5: Transfer characteristics Figure 6: Gate charge vs gate-source voltage Figure 7: Static drain-source on-resistance DocID028830 Rev 1 STU7LN80K5 Electrical characteristics Figure 8: Capacitance variations Figure 9: Normalized gate threshold voltage vs temperature Figure 10: Normalized V(BR)DSS vs temperature Figure 11: Normalized on-resistance vs temperature Figure 12: Source-drain diode forward characteristics Figure 13: Maximum avalanche energy vs starting TJ DocID028830 Rev 1 7/12 Test circuits 3 8/12 STU7LN80K5 Test circuits Figure 14: Test circuit for resistive load switching times Figure 15: Test circuit for gate charge behavior Figure 16: Test circuit for inductive load switching and diode recovery times Figure 17: Unclamped inductive load test circuit Figure 18: Unclamped inductive waveform Figure 19: Switching time waveform DocID028830 Rev 1 STU7LN80K5 4 Package information Package information In order to meet environmental requirements, ST offers these devices in different grades of ® ® ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com. ® ECOPACK is an ST trademark. 4.1 IPAK type C package information Figure 20: IPAK (TO-251) type C package outline 0068771_IK_typeC_rev13 DocID028830 Rev 1 9/12 Package information STU7LN80K5 Table 10: IPAK (TO-251) type C package mechanical data mm Dim. Min. Typ. Max. A 2.20 2.30 2.35 A1 0.90 1.00 1.10 b 0.66 0.79 0.90 b2 10/12 b4 5.23 c 0.46 0.59 c2 0.46 0.59 D 6.00 6.10 6.20 D1 5.20 5.37 5.55 E 6.50 6.60 6.70 E1 4.60 4.78 4.95 e 2.20 2.25 2.30 e1 4.40 4.50 4.60 H 16.18 16.48 16.78 L 9.00 9.30 9.60 L1 0.90 1.00 1.20 L2 0.90 1.08 1.25 θ1 3° 5° 7° θ2 1° 3° 5° DocID028830 Rev 1 5.33 5.43 STU7LN80K5 5 Revision history Revision history Table 11: Document revision history Date Revision 08-Jan-2016 1 DocID028830 Rev 1 Changes First release. 11/12 STU7LN80K5 IMPORTANT NOTICE – PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement. Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers’ products. No license, express or implied, to any intellectual property right is granted by ST herein. Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners. Information in this document supersedes and replaces information previously supplied in any prior versions of this document. © 2016 STMicroelectronics – All rights reserved 12/12 DocID028830 Rev 1