STULPI01A, STULPI01B
High-speed USB On-The-Go ULPI transceiver
Datasheet − production data
Features
■
USB-IF high-speed certified to the universal
serial bus specification rev. 2.0
■
Meets the requirements of the universal serial
bus specification rev. 2.0, On-The-Go
supplement to the USB 2.0 specification 1.0a
and ULPI transceiver specification 1.1
■
Standard ULPI (UTMI+ low pin interface) 1.1
digital interface
■
Fully compliant with ULPI 1.1 register set
■
External square wave clock with VDVIO
amplitude must be applied to oscillator input XI
■
Supports 480 Mbit/s High-speed, 12 Mbit/s
Full-speed and 1.5 Mbit/s Low-speed modes of
operation
■
Supports 2.7 V UART mode
■
Supports session request protocol (SRP) and
host negotiation protocol (HNP) for dual-role
device features
■
Ability to control external charge pump for
higher VBUS currents
■
Single supply, +3 V to +4.5 V voltage range
■
Integrated dual voltage regulator to supply
internal circuits with stable 3.3 V and 1.2 V
■
Integrated overcurrent detector
■
Integrated HS termination and FS/LS/OTG
pull-up/pull-down resistors
■
Integrated USB 2.0 “short-circuit withstand”
protection
■
Power-down mode with very low-power
consumption for battery-powered devices
■
Ideal for system ASICs with built-in USB host,
device or OTG cores
■
Available in µTFBGA36 RoHS package
■
–40 to 85 °C operating temperature range
June 2012
This is information on a product in full production.
µTFBGA36
Applications
■
Mobile phones
■
PDAs
■
MP3 players
■
Digital still cameras
■
Set-top box
■
Portable navigation devices
Description
The STULPI01 is a high-speed USB 2.0
transceiver compliant with ULPI (UTMI+ low pin
interface) and OTG (On-The-Go) specifications,
providing a complete physical layer solution for
any high-speed USB host, device or OTG dualrole core. It allows USB ASICs to interface with
the physical layer of the USB through a 12-pin
interface. It contains VBUS comparators, an ID
line detector, USB differential drivers and
receivers and a complete ULPI register map and
interrupt generator. The STULPI01 transceiver is
suitable for mobile applications and batterypowered devices because of its low-power
consumption, Power-down operating mode and
minimal die/package dimensions.
Doc ID 14817 Rev 4
1/44
www.st.com
1
Contents
STULPI01A, STULPI01B
Contents
1
Application diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2
Bump configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3
Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
4
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
5
Timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
6
Block description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
2/44
6.1
Oscillator and PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
6.2
Voltage reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
6.3
Power-on reset (POR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
6.4
UTMI + CORE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
6.5
ULPI wrapper . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
6.6
External charge pump . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
6.7
VBUS comparators and VBUS overcurrent (OC) detector . . . . . . . . . . . . 19
6.8
VB_REF_FAULT pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
6.9
Voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
6.10
ID detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
6.11
USB 2.0 PHY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
6.12
Power saving features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
6.13
Modes of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
6.13.1
ULPI synchronous mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
6.13.2
6-pin FS/LS serial mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
6.13.3
3-pin FS/LS serial mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
6.14
Car Kit (UART) mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
6.15
Low-power mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
6.16
Power-down mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Doc ID 14817 Rev 4
STULPI01A, STULPI01B
Contents
6.17
VIO OFF mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
6.18
Startup procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
6.18.1
ULPI device detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
6.18.2
SDR mode selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
6.18.3
External clock detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
6.18.4
Reset behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
6.18.5
Interface protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
6.18.6
Software reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
6.18.7
High-speed mode entry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
7
State transitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
8
ULPI registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
9
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
10
Order codes
11
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Doc ID 14817 Rev 4
3/44
List of tables
STULPI01A, STULPI01B
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Table 18.
Table 19.
Table 20.
Table 21.
Table 22.
Table 23.
Table 24.
Table 25.
Table 26.
Table 27.
Table 28.
Table 29.
Table 30.
Table 31.
4/44
Bill of materials - external components . . . . . . . . . . . . . . . . . . . . . . .
Pinout and bump description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . .
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Switching characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
High-speed driver eye pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
VB_REF_FAULT configuration bit settings. . . . . . . . . . . . . . . . . . . .
Car kit signals mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Low-power mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
USB state transitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ULPI register map overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Register access legend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Vendor and product ID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Function control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Interface control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
OTG control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
USB interrupt enable rising register . . . . . . . . . . . . . . . . . . . . . . . . .
USB interrupt enable falling register . . . . . . . . . . . . . . . . . . . . . . . . .
USB interrupt status register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
USB interrupt latch register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Setting rules for interrupt latch register . . . . . . . . . . . . . . . . . . . . . . .
Debug register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Scratch register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Car kit control register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
µTFBGA36 mechanical data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Tape and reel µTFBGA36 mechanical data . . . . . . . . . . . . . . . . . . .
Order codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Doc ID 14817 Rev 4
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. . . . 37
. . . . 37
. . . . 38
. . . . 38
. . . . 38
. . . . 40
. . . . 41
. . . . 42
. . . . 43
STULPI01A, STULPI01B
List of figures
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
Figure 13.
Figure 14.
Peripheral only, configuration with external clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Pin connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
High-speed driver eye pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Rise and fall time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Simplified block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
VB_REF_FAULT pin functionality. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
USB 2.0 PHY block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Startup sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
RESETn behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
High-speed mode entry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
UART mode entry (2.7 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
UART mode exit (2.7 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
µTFBGA36 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Tape and reel µTFBGA36 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Doc ID 14817 Rev 4
5/44
Application diagrams
STULPI01A, STULPI01B
1
Application diagrams
Figure 1.
Peripheral only, configuration with external clock
C
C
F2
F3
CF4
VDVIO
3V3V 1V2V
Battery
voltage
VBAT
VDVIO
XI
VDVIO
XO
CF4
High-speed
USB-OTG
controller
CLK
DIR
STP
NXT
open
External clock
or ground 19.2/26 MHz
VDVIO amplitutde
Mini-B
ID
DP
DM
VBUS
RBUS
D[0]...D[7]
C
D+
DVBUS
GND
T
RREF
RESETn
CSn / PWRDN
RREF
E2
E1
PSWn
GND
CF1
VB_REF_FAULT
5x GND
AM04944v2
Table 1.
Bill of materials - external components
Qty.
1
2
6/44
Symbol
CF1
CF4
Value
Description
0.1 - 1 µF
Filtering capacitor. Suggested components:
Murata 10 V X5R (GRM188R61A105KA61) or
Murata 10 V Y5V (GRM188F51A105ZA01) or
TAIYO YUDEN 25 V X5R (TMK107BJ105KA)
0.1 - 1 µF
Filtering capacitor. Suggested components:
Murata 10 V X5R (GRM188R61A105KA61) or
Murata 10 V Y5V (GRM188F51A105ZA01) or
TAIYO YUDEN 25 V X5R (TMK107BJ105KA)
1
CF2
1 µF - 1.5 µF
Filtering capacitor. Suggested components:
Murata 10 V X5R (GRM188R61A105KA61) or
Murata 10 V Y5V (GRM188F51A105ZA01) or
TAIYO YUDEN 25 V X5R (TMK107BJ105KA)
1
CF3
1 - 4.7 µF
Filtering capacitor. Suggested components:
Murata 10 V Y5V (GRM188F51A475ZE20) or
TAIYO YUDEN 6.3 V X5R (JMK107BJ475KA)
1
CT
4.7 µF
Tank capacitor
1
RREF
12 kΩ
Reference resistor ±1%
1
E1
USBULC6-2F3
1
E2
ESDA14V2-2BF3
1
RBUS
2.2 kΩ
Series overvoltage protection resistor
Doc ID 14817 Rev 4
STULPI01A, STULPI01B
Bump configuration
2
Bump configuration
Figure 2.
Pin connections
1
2
3
4
5
6
F
NC
NC
VBAT
T VBUS
E
GND
VB_REF
_FAULT
3V3V
D
DP
GND
ID
C
DM
RREF
B
D0
1V8
V
DVIO
VIO
A
D1
D2
1
2
XI
XO
GND
DIR
1V2V
PSWn
NXT
STP
GND
D7
A
B
C
D
E
F
CSn/
RESETn
PWRDN
V1V8
DVIO
VIO
GND
GND
V1V8
DVIO
VIO
D6
D3
CLK
D4
D5
4
5
6
3
µTFBGA36 (bottom view)
µTFBGA36 (through top side view)
AM04945v1
Table 2.
Pinout and bump description
Bump
Symbol
Type
Description
B1
D0
I/O
Data bit [0] (VDVIO referred). UART TXD signal.
A1
D1
I/O
Data bit [1] (VDVIO referred). UART RXD signal.
A2
D2
I/O
Data bit [2] (VDVIO referred). UART reserved pin.
A3
D3
I/O
Data bit [3] (VDVIO referred). UART active high interrupt indication.
A4
CLK
O
Clock out (VDVIO referred)
A5
D4
I/O
Data bit [4] (VDVIO referred)
A6
D5
I/O
Data bit [5] (VDVIO referred)
B6
D6
I/O
Data bit [6] (VDVIO referred)
C6
D7
I/O
Data bit [7] (VDVIO referred)
D6
STP
I
ULPI stop signal (VDVIO referred)
D5
NXT
O
ULPI next signal (VDVIO referred)
E5
DIR
O
ULPI direction signal (VDVIO referred)
C3
CSn/PWRDN
I
Chip select active low, power-down active high
C4
RESETn
I
Active low asynchronous reset
D1
DP
I/O
Positive data line of the USB. 5 V tolerant.
C1
DM
I/O
Negative data line of the USB. 5 V tolerant.
D3
ID
I
ID pin of the USB connector for initial device role selection. 5 V tolerant.
F4
VBUS
I/O
VBUS line of the USB interface, requires an external capacitor of 4.7 µF.
Doc ID 14817 Rev 4
7/44
Bump configuration
Table 2.
STULPI01A, STULPI01B
Pinout and bump description (continued)
Bump
Symbol
F1
NC
Not connected
F2
NC
Not connected.
E2
VB_REF_FAULT
I
Voltage reference for internal OC detector input or digital input from
external OC detector (V3V3V referred). 5 V tolerant.
D4
PSWn
O
External charge pump control, active low. 5 V tolerant, open drain.
F5
XI
I
External clock input (VDVIO referred).
F6
XO
O
XO pin must be left floating or grounded (crystal is not supported).
F3
VBAT
PWR
E3
3V3V
PWR 3.3 V LDO output. Bypass 3V3V to GND with a 1.5 µF capacitor.
E6
1V2V
PWR 1.2 V LDO output. Bypass 1V2V to GND with a 1.5 µF capacitor.
C2
RREF
I/O
B2/B3/B5
VDVIO
PWR
C5/D2
GND
PWR Ground
B4/E4/E1
GND
PWR Ground
8/44
Type
Description
Battery power input for the LDO (3 V – 4.5 V). Bypass VBAT to GND with
a 1 µF capacitor.
Reference resistor (12 kΩ ±1%)
Digital I/O supply voltage. Bypass each VDVIO to GND with
a 100 nF-1 μF capacitor. Balls B2-B5 can share common capacitor.
Doc ID 14817 Rev 4
STULPI01A, STULPI01B
Maximum ratings
3
Maximum ratings
Table 3.
Absolute maximum ratings
Symbol
Parameter
Value
Unit
VDVIO
Digital I/O supply voltage
-0.3 to +4.0
V
V1V2
Digital core supply voltage (provided internally by LDO)
-0.3 to +1.4
V
V3V3
Analog supply voltage (provided internally by LDO)
-0.3 to +4.0
V
VBAT
Battery supply voltage
-0.3 to +7.0
V
DC voltage on digital pins (CLK, DIR, STP, NXT, D[0-7], RESETn, XI,
CSn/PWRDN)
-0.3 to +4.0
V
VDCVBUS DC voltage on 5 V tolerant pins (VBUS,VB_REF_FAULT, DP, DM, ID)
-0.3 to +5.5
V
-40 to +125
°C
±2.0
kV
VDCDIG
TSTG
Storage temperature range
VESD-HBM Electrostatic discharge voltage on all pins (according to JESD22-A114-B)
Note:
Absolute maximum ratings are those values above which damage to the device may occur.
Functional operation under these conditions is not implied. All voltages are referenced to
GND.
Table 4.
Thermal data
Symbol
Parameter
Value
Unit
RthJA
Thermal resistance junction-ambient (simulated value as per JEDEC JSD51)
113.8
°C/W
RthJC
Thermal resistance junction-case (simulated value as per JEDEC JSD51)
47
°C/W
RthJB
Thermal resistance junction-base (simulated value as per JEDEC JSD51)
66.2
°C/W
Table 5.
Recommended operating conditions
Symbol
Parameter
Min.
Typ.
Max.
Unit
VBAT
Battery supply voltage
3.0
3.6
4.5
V
VDVIO
Digital I/O supply voltage
1.65
1.80
3.6
V
TA
Operating temperature range
-40
+85
°C
CT
Tank capacitor
RREF
External reference resistor
External square wave (01A, 01B versions)
1
4.7
6.5
µF
11.88
12
12.12
kΩ
19.2 or 26
MHz
4
ns
XTAL
Recommended rise/fall time
Doc ID 14817 Rev 4
9/44
Electrical characteristics
STULPI01A, STULPI01B
4
Electrical characteristics
Table 6.
Electrical characteristics
Symbol
Parameter
Test conditions(1)
Min.
Typ.
Max.
Unit
Power consumption
Active mode (USB bus idle)
IBAT
IDVIO
Supply current
ULPI bus supply current
VDVIO
15
mA
Active mode (FS
transmission, 12 Mb/s
traffic)
30
mA
Active mode (HS
transmission)
50
mA
Suspend mode (not
including DP pull-up
current, external clock
stopped)
120
µA
UART mode (no
transmission)
15
mA
Power-down mode
0.4
2
µA
VIO OFF mode (VDVIO = 0)
0.4
2
µA
Power-down mode
0.1
10
µA
Active mode, 4 pF load
1.8
mA
Logic inputs and outputs
CULPIIN
2.4
ULPI port I/O capacitance
3.5
VDVIO
-0.15
pF
VOH
High level output voltage
(ULPI bus)
IOH = -2 mA
VOL
Low level output voltage
(ULPI bus)
IOL = +2 mA
0.15
V
IOZH_PSWn
High level output leakage
(PSWn)
VOH_PSWn = 3.3 V power
switch disabled
1.0
µA
VOL_PSWn
Low level output voltage
(PSWn)
IOL = +2 mA power switch
enabled
0.15
V
VIH
High level input voltage
(ULPI port and RESETn)
VIL
Low level input voltage
(ULPI port and RESETn)
IIH
High level input leakage
current
10/44
V
0.65 x
VDVIO
VIH = VDVIO -0.2 V
Doc ID 14817 Rev 4
V
0.35 x VDVIO
V
±1.0
µA
STULPI01A, STULPI01B
Table 6.
Electrical characteristics
Electrical characteristics (continued)
Symbol
IIL
Parameter
Test conditions
Min.
Typ.
Low level input leakage curVIL = 0.2 V
rent
Max.
Unit
±1.0
µA
VPDH
High level input voltage
(CSn/PWRDN pin)
VBAT = 3.0 V to 4.5 V
VPDL
Low level input voltage
(CSn/PWRDN pin)
VBAT = 3.0 V to 4.5 V
0.4
V
IPDH
High level input leakage
current (CSn/PWRDN pin)
VPD = 1.4 V, VBAT = 4.5 V
±1.0
µA
IPDL
Low level input leakage
current (CSn/PWRDN pin)
VPD = 0.4 V, VBAT = 4.5 V
±1.0
µA
VFAULTH
High level input voltage
(VB_REF_FAULT pin)
Overcurrent_PD bit is set
VFAULTL
Low level input voltage
(VB_REF_FAULT pin)
Overcurrent_PD bit is set
RIN_VB_REF
VB_REF_FAULT pin input
resistance
1.4
0.65 x V3V3
112
External clock input
hysteresis
XO = ‘0’ at reset
VXIH
High level input voltage
(XI pin)
XO = ‘0’ at reset
VXIL
Low level input voltage
(XI pin)
XO = ‘0’ at reset
VBUS_LKG
VBUS leakage voltage
No load
RVBUS
VBUS input impedance
VBUS_VLD
VBUS valid comparator
threshold
VSESS_VLD
Session valid comparator
threshold for both A and B
device
VSESS_END
Session end comparator
threshold
0.2
RVBUS_PU
VBUS charge pull-up
resistance
650
RVBUS_PD
VBUS discharge pull-down
resistance
800
VXI_HYST_EXT
V
V
148
0.15 x V3V3
V
168
kΩ
500
mV
0.65 x
VDVIO
V
0.15 x VDVIO
V
200
mV
100
kΩ
VBUS
40
1 kΩ series resistors
4.4
4.75
Low to high transition
0.8
1.45
High to low transition
Doc ID 14817 Rev 4
V
2.0
1.25
V
V
0.8
V
950
1150
Ω
1250
1500
Ω
11/44
Electrical characteristics
Table 6.
STULPI01A, STULPI01B
Electrical characteristics (continued)
Symbol
Parameter
Test conditions
Min.
Typ.
Max.
Unit
20
45
95
mV
Overcurrent detector
VOC
Overcurrent trip threshold
VB_REF_FAULT – VBUS
VOC = VB_REF_FAULT –
VBUS
ID pin pull-up current
VID = 0 V
ID
IID_PU
RID_GND
ID line short resistance to
detect ID GND state
RID_FLOAT
ID line short resistance to
detect ID FLOAT state
70
µA
1
kΩ
100
kΩ
VDVIO
- 0.15
V
UART mode (2.7 V ± 5%)
VOH_UART
High level output voltage
(D1, D3)
IOH = -2 mA
VOL_UART
Low level output voltage
(D1, D3)
IOL = +2 mA
VIH_UART_D0
High level input voltage
(D0)
VIL_UART_D0
Low level input voltage (D0)
0.15
0.65 x
VDVIO
V
V
0.35 x VDVIO
V
VOH_DFMS
High level output voltage
(DP)
IOH = -2 mA
2.16
2.85
V
VOL_DFMS
Low level output voltage
(DP)
IOL = +2 mA,
Pull-up = 10 kΩ
-0.10
0.37
V
VIH_DTMS
High level input voltage
(DM)
2.0
3.0
V
VIL_DTMS
Low level input voltage
(DM)
-0.3
0.81
V
40.5
49.5
Ω
2.8
3.6
V
0.0
0.3
V
2.0
V
-10
10
mV
380
440
mV
-10
10
mV
Full-speed/low-speed driver
ZDRV
Output impedance (acting
also as high-speed
termination)
VOH_DRV
High level output voltage
RLH = 14.25 kΩ
VOL_DRV
Low level output voltage
RLL = 1.425 kΩ
VCRS
Driver crossover voltage
CLOAD = 50 to 600 pF
(2)
1.3
1.67
High-speed driver
VHSOI
HS idle level
VHSDPJ
HS data DP J state level
VHSDK
HS data DP K state level
12/44
(2)
Doc ID 14817 Rev 4
STULPI01A, STULPI01B
Table 6.
Electrical characteristics
Electrical characteristics (continued)
Symbol
Parameter
VHSDNJ
HS data DN J state level
VHSDNK
HS data DN K state level
VCHIRPJ
Chirp J level (differential
voltage)
VCHIRPK
Chirp K level (differential
voltage
Test conditions
(2)
(2)
Min.
Typ.
Max.
Unit
380
440
mV
-10
10
mV
700
1100
mV
-900
-500
mV
Full-speed/Low-speed receivers
VDI
VSE_TH
Diff. receiver input
sensitivity (VDP-VDM)
SE receivers switching
threshold
VCM = 0.8 to 2.5 V
200
Low to high transition
0.8
1.6
2.0
V
High to low transition
0.8
1.1
2.0
V
300
RINP
Input resistance
PU/PD resistors
deactivated
CIN
Input capacitance
(2)
ΔCIN
Difference in capacitance
between DP and DM input
VDT_LKG
Data line leakage voltage
mV
kΩ
RPU_EXT = 300 kΩ
5
pF
10
%
342
mV
High-speed receiver
VHSSQ
HS squelch detector
threshold
100
150
mV
VHSDSC
HS disconnect detection
threshold
525
625
mV
VHSCM
HS data signaling common
mode volt. range
(2)
-50
500
mV
VHSTERM
Termination voltage in HS
(2)
-10
10
mV
Data pull-up/pull-down resistors
R PU
Data line pull-up resistance
(DP, DM)
VIHZ
FS idle high level voltage
R PD
Data line pull-down
resistance (DP, DM)
1.425
kΩ
2.7
V
14.25
24.8
kΩ
Voltage regulator
3V3V
3.3 V internal power supply
VBAT = 3.6 V, Active mode
voltage
3.26
3.4
3.54
V
1V2V
1.2 V internal power supply
VBAT = 3.6 V, Active mode
voltage
1.187
1.25
1.31
V
1. Characteristics measured over recommended operating conditions unless otherwise noted. All typical values are referred
to TA = 25 °C, VDVIO = 1.8 V, VBAT = 3.6 V, RREF = 12 kΩ; CT = 4.7 µF.
2. Guaranteed by design.
Doc ID 14817 Rev 4
13/44
Electrical characteristics
Table 7.
STULPI01A, STULPI01B
Switching characteristics
Symbol
Test conditions(1)
Parameter
Min.
Typ.
Max.
Unit
Reset
tRESETEXT
Width of reset pulse on RESETn pin
10
µs
UART mode
tRISE
Switching time (max. low to min.
high)
CLOAD = 185 pF
215
ns
tFALL
Switching time (min. high to max.
low)
CLOAD = 185 pF
215
ns
tPD_RX
Delay time (50% DM to 50% D1)
CL = 10 pF
60
ns
tPD_TX
Delay time (50% D0 to 50% DP)
60
ns
2.5
ms
tUARTON2V7 Turn-on time for TXD line (2V7)
UART_2V7 = 1 measured
from DIR assertion
tUARTOFF2V7 Turn-off time for TXD line (2V7)
UART_2V7 = 1 measured
from STP assertion
1
µs
2
tUARTON
Turn-on time for TXD line
UART_2V7 = 0 measured
from DIR assertion
60
ns
tUARTOFF
Turn-off time for TXD line
UART_2V7 = 0 measured
from DIR de-assertion
60
ns
Low-speed driver
tLR
Data signal rise time
CLOAD = 600 pF
75
100
300
ns
tLF
Data signal fall time
CLOAD = 600 pF
75
100
300
ns
20
%
RFM LS
Rise and fall time matching
-20
DRLS
Low-speed data rate
tDDJ1
Data jitter to next transition
Includes freq. tolerances
-25
25
ns
tDDJ2
Data jitter for paired transitions
Includes freq. tolerances
-14
14
ns
1250
1500
ns
tLEOPT
1.49925
SE0 interval of EOP
1.50075 Mb/s
Full-speed driver
tFR
Data signal rise time
CLOAD = 50 pF
4
20
ns
tFF
Data signal fall time
CLOAD = 50 pF
4
20
ns
-10
+10
%
11.994
12.006
Mb/s
RFMFS
DRHS
Rise and fall time matching
Full-speed data rate
tDJ1
Data jitter to next transition
Includes freq. tolerances
-3.5
3.5
ns
tDJ2
Data jitter for paired transitions
Includes freq. tolerances
-4
4
ns
160
175
ns
tFEOPT
SE0 interval of EOP
Clock generation constants
tPLL
tDLL
14/44
PLL lock time
(2)
200
µs
DLL lock time
(2)
280
µs
Doc ID 14817 Rev 4
STULPI01A, STULPI01B
Table 7.
Electrical characteristics
Switching characteristics (continued)
Symbol
Parameter
Test conditions
Min.
Typ.
Max.
Unit
High-speed driver
tHSR
Data rise time
500
ps
tHSF
Data fall time
500
ps
Waveform requirements including
jitter
DRHS
Specified by eye pattern
(Figure 3)
High-speed data rate
479.76
480.24
Mb/s
ULPI interface
CLOCK (measured on CLK pin)
fSTART_U
Frequency (first transition)
fSTEADY_U
Frequency (steady-state)
DSTART_U
Duty cycle (first transition)
(2)
DSTEADY_U
Duty cycle (steady-state)
(2)
TSTEADY_U
Time to reach steady-state
frequency and duty cycle after first
transition
(2)
TJITTER_U
Jitter
tSCLK60OUT Clock startup time
54
60
66
MHz
59.97
60
60.03
MHz
40
50
60
%
45
50
55
%
1.4
ms
400
Measured from assertion
of STP during suspend, or
after release of RESETn
pin
250
ps
900
µs
ULPI control signals (SDR mode)(2)
TSC_U
Control in setup time
THC_U
Control in hold time
TDC_U
Control output delay
CLOAD = 15 pF
VDVIO = 1.65 - 3.6 V
6.0
ns
0.0
ns
9.0
ns
ULPI data signals (SDR mode)(2)
TSD_U
Data in setup time
THD_U
Data in hold time
TDD_U
Data output delay
CLOAD = 15 pF
VDVIO = 1.65 - 3.6 V
6.0
ns
3.0
ns
9.0
ns
1. Over recommended operating conditions unless otherwise noted. All the typical values are referred to TA = 25 °C,
V DVIO = 1.8 V, VBAT = 3.6 V, CT = 4.7 µF.
2. Guaranteed by design.
Doc ID 14817 Rev 4
15/44
Electrical characteristics
Figure 3.
STULPI01A, STULPI01B
High-speed driver eye pattern
Level 1
Point 3
+400 mV
differential
Point 4
Point 1
0V
differential
Point 2
Point 5
Point 6
-400 mV
differential
Level 2
0%
Unit interval
100 %
AM04946v2
Table 8.
High-speed driver eye pattern
Parameter
Voltage level
(DP – DM)
Time
(% of unit interval)
Level 1
Level 2
525 mV(1) –525 mV(1)
475 mV
–475 mV
Point 1
Point 2
Point 3
Point 4
Point 5
Point 6
0V
0V
300 mV
300 mV
–300 mV
–300 mV
5%
95%
35%
65%
35%
65%
1. This value is valid for unit intervals following a transition. For all other intervals the other value is valid.
16/44
Doc ID 14817 Rev 4
STULPI01A, STULPI01B
Timing diagram
5
Timing diagram
Figure 4.
Rise and fall time
tR
tF
VOH_DRV
90%
90%
10%
VOL_DRV
10%
CS26080
Figure 5.
Simplified block diagram
ID
VBUS
VB_REF_FAULT
PSWn
RESETn
XI
XO
Oscillator
and
PLL
OTG block
Block
Overcurrent
fault
detector
Charge pump,
Pump,
VBUS comparators
Comparators
ID Detector
detector
VDVIO
Power
on reset
GND
CLK
DIR
STP
NXT
ULPI
ULPI
UTMI +
UTMI +
interface
Interface
Core
core
wrapper
USB 2.0
PHY
Dual
voltage
regulator
VBAT
GND
D0 - D7
Voltage
reference
DP
RREF
DM
AM04947v2
Doc ID 14817 Rev 4
17/44
Block description
6
STULPI01A, STULPI01B
Block description
The STULPI01 integrates a comparator for the VBUS, ID line detector, differential HS data
driver, differential and single-ended receivers, low dropout voltage regulators, and control
logic.
The STULPI01 provides a complete solution for the connection of a digital USB
host/device/OTG controller to a USB bus.
6.1
Oscillator and PLL
An external clock (digital square wave VDVIO referred) driven into XI must be used (version
STULPI01A or STULPI01B).
The PLL internally produces all frequencies needed for operation:
6.2
●
60-MHz clock for the UTMI core and ULPI interface controller
●
1.5 MHz for low-speed USB data
●
12 MHz for full-speed USB data
●
480 MHz for high-speed USB data
●
Other internal frequencies for data conversion and data recovery.
Voltage reference
This block provides the precise reference voltage needed by the internal circuit.
It requires a 12 kΩ +/- 1% resistor connected to the RREF pin.
6.3
Power-on reset (POR)
The power-on reset circuit generates a reset pulse upon power-up which is used to initialize
the entire digital logic. Power-on reset senses the V3V3V and V1V2V voltage.
During the power-on reset pulse, the ULPI pins are in a high impedance state with pulldown/pull-up resistors disabled.
6.4
UTMI + core
This is the digital heart of the chip and performs the bit-stuffing, NRZI decoding and serial to
parallel conversion during receive and the reverse operation during transmit for HS and
FS/LS.
6.5
ULPI wrapper
This implements the ULPI related protocol and conversion from UTMI+ to ULPI interface.
This block also implements the interrupt logic and complete ULPI register set.
18/44
Doc ID 14817 Rev 4
STULPI01A, STULPI01B
6.6
Block description
External charge pump
It is possible to use an external charge pump or power switch controlled by the PSWn pin
(active low open drain). This functionality is controlled by DrvVbus and DrvVbusExternal
ULPI OTG control register bits.
6.7
VBUS comparators and VBUS overcurrent (OC) detector
These comparators monitor the VBUS voltage.
VBUS valid status signals that the voltage is above the VBUS_VLD level (4.4 V). Session valid
status signals that the VBUS voltage is above the VSESS_VLD level (0.8 to 2.0 V). Session end
detector signals that VBUS voltage is below VSESS_END level.
The STULPI01 also implements an embedded VBUS overcurrent detector which compares
VBUS voltage to the external analog 5 V reference signal applied to the VB_REF_FAULT pin.
6.8
VB_REF_FAULT pin
VBUS overcurrent conditions can be monitored by either an internal or external OC detector.
The internal OC detector is enabled when the overcurrent_PD bit in the power control
register (vendor-specific area) is set to 0b and Use External VBUS Indicator is set to 1b. In
this mode, the VB_REF_FAULT pin functions as the input of the analog reference for internal
overcurrent detector.
If the external charge pump is already equipped with an overcurrent detector, its output can
be also monitored through the VB_REF_FAULT pin, but the overcurrent_PD bit must be set
to 1b. In this mode, VB_REF_FAULT functions as the standard digital input pin with 5 V
tolerance. Functionality of the VB_REF_FAULT pin can be seen in more detail in Figure 6.
Note:
After reset, the overcurrent_PD bit is 1b, the internal overcurrent detector is disabled.
Doc ID 14817 Rev 4
19/44
Block description
Figure 6.
STULPI01A, STULPI01B
VB_REF_FAULT pin functionality
VBUS
VBUS
VBUSVLD
+
Internal VBUS Valid
[0,X]
REF
-
VBOC
+
VBREF
RX CMD VBUS Valid
[1,0]
VBUS
VBREF_FAULT
0
[1,1]
/EN
1
2
EN
RIN_VBREF
FAULT
[UseExternalVbusIndicator, IndicatorPassthru]
Schmitt
(5 V TOLERANT)
OverCurrent_PD or neg (UseExternalVbusIndicator)
IndicatorComplement
Table 9.
AM04948v2
VB_REF_FAULT configuration bit settings
RX CMD VBUS valid
Use External
Vbus Indicator
Overcurrent_PD
Indicator Pass-Thru
Indicator
complement
VBUSVLD
0
1
X
X
VBOC
1
0
1
X
VBOC and VBUSVLD
1
0
0
X
neg (FAULT)
1
1
1
0
FAULT
1
1
1
1
VBUSVLD and FAULT
1
1
0
1
VBUS_VLD and neg (FAULT)
1
1
0
0
6.9
Voltage regulator
The dual output ultra low dropout voltage regulator provides the power supply for analog and
digital internal circuits. An external capacitor on both the 3V3V and 1V2V pins is needed for
proper operation.
6.10
ID detector
This block provides the sensing of the status of the ID line. It is capable of detecting whether
the pin is floating or tied to the ground.
6.11
USB 2.0 PHY
The USB 2.0 PHY block provides a complete physical layer transceiver for low-speed, fullspeed, and high-speed USB operating modes. The analog part of this block deals with
impedance adaptation, controlled voltage swing, and Common mode voltage generation
20/44
Doc ID 14817 Rev 4
STULPI01A, STULPI01B
Block description
and sensing. The digital part consists of a serializer and deserializer, transforming serial bit
stream to 8-bit parallel port, and finite state machine implementing the PHY protocol layer,
bit stuffing, unstuffing, etc.
Figure 7.
USB 2.0 PHY block diagram
3.3 V
HS
Ser-Des
LS/FS
Ser-Des
DP
3.3 V
DN
HS Disconnect Det.
Squelch Detector
LS/FS SE Receivers
19.25 kΩ
AM04949v2
6.12
Power saving features
To reduce power consumption, the STULPI01 implements 2 Low-power modes of operation.
1.
Low-power mode, which is defined in the ULPI specification.
2.
Power-down mode to save more power in case USB function is not needed.
More information on these modes can be found in the following paragraphs.
6.13
Modes of operation
6.13.1
ULPI synchronous mode
The STULPI01 transceiver supports SDR mode operation (12-pin interface). The selection
of SDR mode is performed during the startup reset procedure.
6.13.2
6-pin FS/LS serial mode
This mode is entered by writing to the corresponding bit in the Interface Control register.
6.13.3
3-pin FS/LS serial mode
This mode is entered by writing to the corresponding bit in the Interface Control register.
Doc ID 14817 Rev 4
21/44
Block description
6.14
STULPI01A, STULPI01B
Car Kit (UART) mode
This mode is entered by writing to the Car Kit mode bit in the interface control register. The
STULPI01 does not implement all features of Car Kit mode, only the UART functionality is
preserved.
Table 10.
Car kit signals mapping
Default car kit signals mapping (UART_DIR = 0)
Signal
ULPI lines
TXD
DATA[0] (input)
RXD
DATA[1] (output)
DM (output)
DP (input)
DATA[2] (input)
DATA[3] (output)
Car kit signals mapping (UART_DIR = 1)
Signal
ULPI lines
TXD
DATA[0] (input)
RXD
DATA[1] (output)
USB lines
DP (output)
DM (input)
DATA[2] (input)
DATA[3] (output)
TXD or RXD paths are activated only when the corresponding bits TXD_EN/RXD_EN in car
kit control register bits (Table 23) are set.
The UART_2V7 bit controls the voltage level of UART signaling. If 2V7 volt signaling is used,
after the UART mode is entered, PLL is disabled and the voltage on the regulator output
starts to decrease to 2.7 V. After a time marked as tUARTON2V7, the TXD output on the USB
bus is enabled.
When leaving Car Kit mode, TXD is disabled immediately when the STP pin is asserted.
The time required to exit Car Kit mode is equivalent to the time needed for PLL startup.
When 3.3 volt UART signaling is selected, the TXD line is enabled immediately after
entering Car Kit mode, and disabled after exiting this mode.
Note:
When Car Kit mode is used with 2V7 signaling, the PLL and output clock are always
stopped regardless of the setting of the ClockSuspendM bit.
6.15
Low-power mode
The STULPI01 enters Low-power mode when the SuspendM bit in the interface control
register is set to 0b. Most of the references are turned off, PLL and clock are turned off, but
the full wake-up capability as defined in the ULPI specification is still maintained.
When in Low-power mode, the PHY drives D3-D0 with the signals listed in Table 11. Line
state is driven combinatorially from the SE receivers. The INT signal is asserted whenever
any unmasked interrupt occurs. The PHY latches interrupt events directly from analog
circuitry because the clock is powered down.
22/44
Doc ID 14817 Rev 4
STULPI01A, STULPI01B
Table 11.
Block description
Low-power mode
Signal
Map to
Dir
Description
Linestate (0)
D0
out
Driven combinatorially from SE receivers
Linestate (1)
D1
out
Driven combinatorially from SE receivers
Reserved
D2
out
Reserved
INT
D3
out
Active high interrupt indication. Asserted whenever
any unmasked interrupt occurs.
Low-power mode is exited by asserting the STP pin high. PLL is started immediately, and
when the clock becomes stable, it is passed on the output of the CLK pin. Then, after a
minimum of 5 clock cycles, DIR is deasserted and Low-power mode is exited. The
SuspendM bit is reset to 1b.
Note:
The STP signal must be kept high until the DIR is deasserted, otherwise Low-power mode is
not exited.
6.16
Power-down mode
Power-down mode is entered by asserting the CSn/PWRDN pin high. Internal voltage
regulators are disabled, and the device has minimum possible power consumption. The
STULPI01 has no wake-up capability or USB functionality during Power-down mode. This
mode can be exited by deasserting the CSn/PWRDN pin. Voltage regulators are turned on
and the internal power-on reset circuit resets the chip to initial state. ULPI interface pins are
in high impedance state during Power-down mode.
6.17
VIO OFF mode
If VDVIO is below the minimum value, VIO OFF mode is entered. The behavior of the device
in VIO OFF mode is the same as in Power-down mode.
6.18
Startup procedure
6.18.1
ULPI device detection
The link detects ULPI device presence by sampling the DIR signal at the reset time
(Figure 8). The NXT signal is '0' after reset to signal an 8-bit device to the link controller.
CLK is '1' to signal a DDR capable device.
6.18.2
SDR mode selection
The STULPI01 samples the D0 line on the first rising edge of the output clock on the CLK
pin. When the sampled value is '0', the STULPI01 remains in SDR mode.
SDR mode can be selected again only after hardware reset. During software reset mode,
selection is not performed.
Doc ID 14817 Rev 4
23/44
Block description
STULPI01A, STULPI01B
Note:
IMPORTANT: The controller must not drive the DATA lines to a value other than 0x00 or
0x01 during the first rising edge of ULPI CLK, otherwise the behavior of the device may be
undefined.
6.18.3
External clock detection
The square wave clock can be applied to the oscillator input. The input square wave clock
amplitude is referenced to VDVIO.
The XO pin can be left floating or grounded.
6.18.4
Reset behavior
A typical startup sequence is shown in Figure 12.
The STULPI01 contains an internal power-on reset generator which senses the V3V3V and
V1V2V voltage. Assertion of RESETn is not necessary for proper initialization. However, if
required, this pin can be also used. The internal reset signal is the combination of the signal
from the RESETn pin and the signal from the internal power-on reset circuit.
When RESETn is asserted, all internal registers are reset to their default values, the output
DIR signal is driven to '1', and data lines are pulled low by weak pull-downs.
During reset, the STP pin can be driven low, high, or can be left floating. It is pulled up by
internal pull-up and the ULPI interface enters a holding state.
During the reset state, the NXT signal is driven low and the CLK is driven high.
When the PLL is stabilized, the clock on the CLK pin is enabled, and DIR is deasserted.
Note:
The minimum duration of the external reset signal is TRESETEXT. (See Table 7).
When internal POR reset is asserted, the reset procedure is equivalent to the RESETn
signal, with the only exception being that the ULPI lines are in high impedance state. All pulldowns and pull-ups on the ULPI signals are also disabled.
6.18.5
Interface protection
The STULPI01 activates weak pull-downs on data lines and pull-up on the STP during reset
and holding state. These are to provide interface protection during startup and anytime the
link is not able to drive the ULPI lines properly.
The holding state is entered when the controller drives the STP for more than 1 clock cycle.
Any command on the ULPI bus is ignored in this state. For more information see ULPI
specification 1.1, section 3.12 (Safeguarding PHY input signals).
Interface protection can be switched off at any time after startup in order to save power, by
writing the Interface Protect Disable bit in the Interface Control register to 1b.
6.18.6
Software reset
The STULPI01 supports software reset by writing the RESET bit in the function control
register to 1b.
During software reset, DIR is asserted and the pull-down resistors on data lines are
enabled, but the ULPI registers remain unaffected. Software reset initializes UTMI core logic
only. Also, during software reset, external clock detection, SDR mode selection is not
performed, and the clock is not turned off (PLL is not restarted).
24/44
Doc ID 14817 Rev 4
STULPI01A, STULPI01B
Block description
Note:
Software reset is not required in the startup procedure for the STULPI. The chip is ready for
operation after the hardware reset procedure.
6.18.7
High-speed mode entry
In High-speed mode, the internal 480-MHz clock is generated by the DLL, which must be
calibrated any time the device enters High-speed mode by writing '00' to the XcvrSel field in
the Function Control register. During the DLL calibration, it is not possible to accept any
commands, therefore, to avoid any communication problems with the controller, the clock on
the ULPI interface is stopped. See Figure 10 for more information.
Figure 8.
Startup sequence
Doc ID 14817 Rev 4
25/44
Block description
Figure 9.
STULPI01A, STULPI01B
RESETn behavior
AM04951v1
Figure 10. High-speed mode entry
26/44
Doc ID 14817 Rev 4
STULPI01A, STULPI01B
Block description
Figure 11. UART mode entry (2.7 V)
Figure 12. UART mode exit (2.7 V)
Doc ID 14817 Rev 4
27/44
State transitions
7
State transitions
Table 12.
USB state transitions
STULPI01A, STULPI01B
TermSelect
OpMode
DpPulldown
DmPulldown
rpu_dp_en
rpu_dm_en
rpd_dp_en
rpd_dm_en
hsterm_en
Resistor settings
XcvrSelect
Register settings
3-state drivers
XXb
Xb
01b
0b
0b
0b
0b
0b
0b
0b
3-state drivers with pull-down enabled
XXb
Xb
01b
1b
1b
0b
0b
1b
1b
0b
Power-up or Vbus < Vth(SESSEND)
01b
0b
00b
1b
1b
0b
0b
1b
1b
0b
Host chirp
00b
0b
10b
1b
1b
0b
0b
1b
1b
1b
Host high-speed
00b
0b
00b
1b
1b
0b
0b
1b
1b
1b
Host full-speed
X1b
1b
00b
1b
1b
0b
0b
1b
1b
0b
Host HS/FS suspend
01b
1b
00b
1b
1b
0b
0b
1b
1b
0b
Host HS/FS resume
01b
1b
10b
1b
1b
0b
0b
1b
1b
0b
Host low-speed
10b
1b
00b
1b
1b
0b
0b
1b
1b
0b
Host low-speed suspend
10b
1b
00b
1b
1b
0b
0b
1b
1b
0b
Host low-speed resume
10b
1b
10b
1b
1b
0b
0b
1b
1b
0b
Host test_J/Test_K
00b
0b
10b
1b
1b
0b
0b
1b
1b
1b
Peripheral chirp
00b
1b
10b
0b
0b
1b
0b
0b
0b
0b
Peripheral high-speed
00b
0b
00b
0b
0b
0b
0b
0b
0b
1b
Peripheral full-speed
01b
1b
00b
0b
0b
1b
0b
0b
0b
0b
Peripheral HS/FS suspend
01b
1b
00b
0b
0b
1b
0b
0b
0b
0b
Peripheral HS/FS resume
01b
1b
10b
0b
0b
1b
0b
0b
0b
0b
Peripheral low-speed
10b
1b
00b
0b
0b
0b
1b
0b
0b
0b
Peripheral low-speed suspend
10b
1b
00b
0b
0b
0b
1b
0b
0b
0b
Peripheral low-speed resume
10b
1b
10b
0b
0b
0b
1b
0b
0b
0b
Peripheral test_J/Test_K
00b
0b
10b
0b
0b
0b
0b
0b
0b
1b
Signaling mode
General settings
Host settings
Peripheral settings
28/44
Doc ID 14817 Rev 4
STULPI01A, STULPI01B
Table 12.
State transitions
USB state transitions (continued)
TermSelect
OpMode
DpPulldown
DmPulldown
rpu_dp_en
rpu_dm_en
rpd_dp_en
rpd_dm_en
hsterm_en
Resistor settings
XcvrSelect
Register settings
OTG device, peripheral chirp
00b
1b
10b
0b
1b
1b
0b
0b
1b
0b
OTG device, peripheral high-speed
00b
0b
00b
0b
1b
0b
0b
0b
1b
1b
OTG device, peripheral full-speed
01b
1b
00b
0b
1b
1b
0b
0b
1b
0b
OTG device, peripheral HS/FS suspend
01b
1b
00b
0b
1b
1b
0b
0b
1b
0b
OTG device, peripheral HS/FS resume
01b
1b
10b
0b
1b
1b
0b
0b
1b
0b
OTG device, peripheral, Test_J/Test_K
00b
0b
10b
0b
1b
0b
0b
0b
1b
1b
Signaling mode
Doc ID 14817 Rev 4
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ULPI registers
STULPI01A, STULPI01B
8
ULPI registers
Table 13.
ULPI register map overview
Address (6 bits)
Field name
Size (bits)
Rd
Wr
Set
Clr
Immediate register set
Vendor ID low
8
00h
-
-
-
Vendor ID high
8
01h
-
-
-
Product ID low
8
02h
-
-
-
Product ID high
8
03h
-
-
-
Function control
8
04-06h
04h
05h
06h
Interface control
8
07-09h
07h
08h
09h
OTG control
8
0A-0Ch
0Ah
0Bh
0Ch
USB interrupt enable rising
8
0D-0Fh
0Dh
0Eh
0Fh
USB interrupt enable falling
8
10-12h
10h
11h
12h
USB interrupt status register
8
13h
-
-
-
USB interrupt latch register
8
14h
-
-
-
Debug
8
15h
-
-
-
Scratch
8
16-18h
16h
17h
18h
Car kit control register
8
16-1Bh
19h
1Ah
1Bh
Reserved
8
Access extended register set (see Table 14)
8
-
-
Reserved
8
1C-2Eh
-
2Fh
30-3Ch
Power control
3D-3Fh
Extended register set
Address (8 bits)
Maps to immediate register set above
8
00-3Fh
Reserved
8
40-FFh
Table 14.
Register access legend
Access code
Expanded name
rd
Read
Register can be read. Read-only if this is the only mode given.
wr
Write
Pattern on the data bus is written over all bits of the register.
s
Set
Pattern on the data bus is OR’d with the register value and written into
the register.
c
Clear
Pattern on the data bus is a mask. If a bit in the mask is set, then the
corresponding register bit is set to zero (cleared).
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Meaning
Doc ID 14817 Rev 4
STULPI01A, STULPI01B
Table 15.
ULPI registers
Vendor and product ID
Register
Bits
Access
Address
Value
Description
VENDOR_ID_LOW
7:0
rd
00h
83 h
Lower byte of vendor ID.
VENDOR_ID_HIGH
7:0
rd
01h
04 h
Upper byte of vendor ID.
PRODUCT_ID_LOW
7:0
rd
02h
4b h
Lower byte of product ID number.
PRODUCT_ID_HIGH
7:0
rd
03h
4f h
Upper byte of product ID number.
Table 16.
Power control register
Field name
Bits
Access
Reset
Reserved
0
rd/wr/s/c
0b
Reserved. The link must never write a 1b to this bit.
Overcurrent_PD
1
rd/wr/s/c
1b
Power control of the internal overcurrent circuit.
0b: enables the overcurrent circuit.
1b: disables the overcurrent circuit.
UART_DIR
2
rd/wr/s/c
0b
0b: Txd on DM and Rxd on DP
1b: Txd on DP and Rxd on DM
UART_2V7
3
rd/wr/s/c
1b
0b: UART signaling at 3V3
1b: UART signaling at 2V7
7:4
rd/wr/s/c
0b
Reserved. The link must never write a 1b to these bits.
Reserved
Note:
Description
3Dh-3Fh(Read), 3Dh(Write), 3Eh(Set), 3Fh(Clear). These addresses control various power
aspects of the USB transceiver.
Doc ID 14817 Rev 4
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ULPI registers
Table 17.
Field name
XcvrSelect
TermSelect
OpMode
Reset
STULPI01A, STULPI01B
Function control register
Bits
1:0
2
4:3
5
Access
rd/wr/s/c
rd/wr/s/c
rd/wr/s/c
rd/wr/s/c
Reset
Description
01b
Selects the required transceiver speed.
00b: enables HS transceiver
01b: enables FS transceiver
10b: enables LS transceiver
11b: enables FS transceiver for LS packets (FS preamble
is automatically pre-pended)
Important note: Every time XcvrSelect is changed to
‘00’, the output ULPI clock is stopped for the time needed
for internal DLL calibration.
0b
Controls the internal pull-up resistors or HS terminations.
Control over these resistors changes depending on
XcvrSelect, OpMode, DpPulldown and DmPulldown, as
shown in Table 24.
00b
Selects the required bit encoding style during transmit.
00b: normal operation
01b: non-driving
10b: disables bit-stuff and NRZI encoding
11b: does not automatically add SYNC and EOP when
transmitting. Must be used only for HS packets.
0b
Active high transceiver reset. After the link sets this bit,
the STULPI01 asserts DIR and reset the UTMI+ core.
When the reset is complete, the STULPI01 de-asserts
DIR and automatically clears this bit. After de-asserting
DIR, the STULPI01 re-asserts DIR and sends an RX
CMD update to the link.
Note: If Reset bit is set to ‘1’ and SuspendM bit is set to
‘0’ in the same register access, SuspendM bit takes
higher priority and the chip enters Low-power mode.
Reset bit is cleared.
SuspendM
6
rd/wr/s/c
1b
Active low PHY suspend. Puts PHY into Low-power
mode. The STULPI01 automatically sets this bit to ‘1’
when Low-power mode is exited.
0b: Low-power mode
1b: Powered
Note: If Reset bit is set to ‘1’ and SuspendM bit is set to
‘0’ in the same register access, SuspendM bit takes
higher priority and the chip enters Low-power mode.
Reset bit is cleared.
Reserved
7
rd/wr/s/c
0b
Reserved
Note:
32/44
04h-06h(Read), 04h(Write), 05h(Set), 06h(Clear). These addresses control UTMI function
setting of the USB transceiver PHY.
Doc ID 14817 Rev 4
STULPI01A, STULPI01B
Table 18.
ULPI registers
Interface control register
Field name
6-pin
FsLsSerialMode
3-pin
FsLsSerialMode
Carkit mode
Bits
0
1
2
Access
rd/wr/s/c
rd/wr/s/c
rd/wr/s/c
Reset
Description
0b
Changes the ULPI interface to 6-pin Serial mode. The
STULPI01 automatically clears this bit when Serial mode is
exited.
0b: FS/LS packets are sent using parallel interface.
1b: FS/LS packets are sent using 6-pin serial interface.
0b
Changes the ULPI interface to 3-pin Serial mode. The
STULPI01 automatically clears this bit when Serial mode is
exited.
0b: FS/LS packets are sent using parallel interface.
1b: FS/LS packets are sent using 4-pin serial interface.
0b
The STULPI01 does not support all the features of Car Kit
mode. Only the UART functionality is implemented.
0b: disables serial Car Kit mode.
1b: enables serial Car Kit mode.
ClockSuspendM
3
rd/wr/s/c
0b
Active low clock suspend. Valid only in Serial mode and Car
Kit mode. Powers down the internal clock circuitry. Valid only
when SuspendM = 1b. The STULPI01 ignores
ClockSuspend when SuspendM = 0b. By default, the clock
is not powered in Serial and Car Kit modes.
0b: clock is not powered in Serial and Car Kit modes.
1b: clock is powered in Serial and Car Kit modes.
Reserved
4
rd/wr/s/c
0b
The STULPI01 does not implement auto-resume feature,
because the clock can be restarted in less than 1ms.
0b
Gives the command to invert the ExternalVbusIndicator
signal, generating the complement output.
0b: The STULPI01 does not invert ExternalVbusIndicator
signal
1b: STULPI01 inverts ExternalVbusIndicator signal.
0b
Controls whether the complement output is qualified with the
Internal VbusValid comparator before being used in the
Vbus State in the RX CMD.
0b: complements output signal is qualified with the Internal
VbusValid comparator.
1b: complements output signal is not qualified with the
Internal VbusValid comparator.
0b
Controls circuitry for protecting the ULPI interface when the
link 3-states STP and DATA. This bit is not intended to affect
the operation of the holding state. Refer to Section 3.12 of
ULPI specification 1.1 for more details.
0b: enables the interface protection circuit (default).
1b: disables the interface protection circuit.
Interface protection circuit consists of pull-down resistors on
DATA and pull-up resistors on STP.
Indicator
complement
5
Indicator
PassThru
6
Interface protect
disable
Note:
7
rd/wr/s/c
rd/wr/s/c
rd/wr/s/c
07h-09h(Read), 07h(Write), 08h(Set), 09h(Clear). These addresses enable alternative
interfaces and STULPI01 features.
Doc ID 14817 Rev 4
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ULPI registers
Table 19.
STULPI01A, STULPI01B
OTG control register
Field name
Bits
Access
Reset
Description
IdPullup
0
rd/wr/s/c
0b
Connects a pull-up to the ID line and enables sampling of the
signal level.
0b: disables sampling of ID line.
1b: enables sampling of ID line.
DpPulldown
1
rd/wr/s/c
1b
Enables the 15 kΩ pull-down resistor on DP.
0b: pull-down resistor not connected to DP.
1b: pull-down resistor connected to DP.
DmPulldown
2
rd/wr/s/c
1b
Enables the 15 kΩ pull-down resistor on DM.
0b: pull-down resistor not connected to DM.
1b: pull-down resistor connected to DM.
DischrgVbus
3
rd/wr/s/c
0b
Discharges VBUS through a resistor. If the link sets this bit to 1,
it waits for an RX CMD indicating SessEnd has transition from 0
to 1, and then resets this bit to 0 to stop the discharge.
0b: does not discharge VBUS
1b: discharges VBUS
ChrgVbus
4
rd/wr/s/c
0b
Charges VBUS through a resistor. Used for VBUS pulsing SRP.
0b: does not charge VBUS
1b: charges VBUS
DrvVbus
5
rd/wr/s/c
0b
Signals the internal charge pump or external supply to drive 5 V
on VBUS.
0b: does not drive VBUS (default)
1b: drives 5 V on VBUS
DrvVbus External
6
rd/wr/s/c
0b
Selects between the internal and the external 5 V VBUS supply.
0b: drives VBUS using the internal charge pump (default).
1b: drives VBUS using external supply.
0b
Tells STULPI01 to use an external VBUS overcurrent indicator.
0b: uses the internal OTG comparator or internal
VBUS valid indicator (default)
1b: uses external VBUS valid indicator signal
UseExternal
VbusIndicator
Note:
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7
rd/wr/s/c
0Ah-0Ch(Read), 0Ah(Write), 0Bh(Set), 0Ch(Clear). These addresses control UTMI + OTG
functions of the PHY.
Doc ID 14817 Rev 4
STULPI01A, STULPI01B
Table 20.
ULPI registers
USB interrupt enable rising register
Field name
Bits
Access
Reset
Description
Host disconnect rise
0
rd/wr/s/c
1b
Generates an interrupt event notification when host
disconnect changes from low to high. Applicable only in
Host mode (DpPulldown and DmPulldown both set to
1b).
VbusValid rise
1
rd/wr/s/c
1b
Generates an interrupt event notification when
VbusValid changes from low to high.
SessValid rise
2
rd/wr/s/c
1b
Generates an interrupt event notification when
SessValid changes from low to high. SessValid is the
same as UTMI+AValid.
SessEnd rise
3
rd/wr/s/c
1b
Generates an interrupt event notification when SessEnd
changes from low to high.
ID rise
Reserved
Note:
4
rd/wr/s/c
1b
Generates an interrupt event notification when ID
changes from low to high. ID is valid 50 ms after
IdPullup is set to 1b, otherwise ID is undefined and
should be ignored.
7:5
rd/wr/s/c
0b
Reserved.
0Dh-0Fh(Read), 0Dh(Write), 0Eh(Set), 0Fh(Clear).
If set, the bits in this register cause an interrupt event notification to be generated when the
corresponding PHY signal changes from low to high. By default, all transitions are enabled.
RxActive and RxError must always be communicated immediately and so are not included
in this register. Interrupt circuitry can be powered down in any mode when both rising and
falling edge enables are disabled. To ensure interrupts are detectable when clock is
powered down, the link should enable both rising and falling edges.
Doc ID 14817 Rev 4
35/44
ULPI registers
Table 21.
STULPI01A, STULPI01B
USB interrupt enable falling register
Field name
Bits
Access
Reset
Host disconnect fall
0
rd/wr/s/c
1b
Generates an interrupt event notification when the host
disconnect changes from high to low. Applicable only in Host
mode.
VbusValid fall
1
rd/wr/s/c
1b
Generates an interrupt event notification when VbusValid
changes from high to low.
SessValid fall
2
rd/wr/s/c
1b
Generates an interrupt event notification when SessValid
changes from high to low. SessValid is the same as
UTMI+AValid.
SessEnd fall
3
rd/wr/s/c
1b
Generates an interrupt event notification when SessEnd
changes from high to low.
ID fall
4
rd/wr/s/c
1b
Generates an interrupt event notification when ID changes from
high to low. ID is valid 50 ms after IdPullup is set to 1b, otherwise
ID is undefined and should be ignored.
7:5
rd/wr/s/c
0b
Reserved
Reserved
Note:
Description
Address 10h-12h(Read), 10h(Write), 11h(Set), 12h(Clear).
If set, the bits in this register cause an interrupt event notification to be generated when the
corresponding PHY signal changes from high to low. By default, all transitions are enabled.
RxActive and RxError must always be communicated immediately and so are not included
in this register. Interrupt circuitry can be powered down in any mode when both rising and
falling edge enables are disabled. To ensure interrupts are detectable when clock is
powered down, the link should enable both rising and falling edges.
Table 22.
USB interrupt status register
Field name
Bits
Access
Reset
Description
Host disconnect
0
rd
0b
Current value of UTMI+Host disconnect output. Applicable only
in Host mode. Automatically reset to 0b when Low-power mode
is entered.
VbusValid
1
rd
0b
Current value of UTMI+VbusValid output.
SessValid
2
rd
0b
Current value of UTMI+SessValid output. SessValid is the same
as UTMI+AValid.
SessEnd
3
rd
0b
Current value of UTMI+SessEnd output.
ID
4
rd
0b
Current value of UTMI+ID output. ID is valid 50 ms after IdPullup
is set to 1b, otherwise ID is undefined and should be ignored.
7:5
rd
0b
Reserved
Reserved
Note:
Address 13h(Read-only).
These bits indicate the current value of the interrupt source signal. Interrupt circuitry can be
powered down in any mode when both rising and falling edge enables are disabled. To
ensure interrupts are detectable when clock is powered down, the link should enable both
rising and falling edges.
36/44
Doc ID 14817 Rev 4
STULPI01A, STULPI01B
Table 23.
ULPI registers
USB interrupt latch register
Field name
Bits
Access
Reset
Description
Host disconnect
latch
0
rd
0b
Set to 1b by the STULPI01 when an unmasked event occurs on
host disconnect. Cleared when this register is read. Applicable
only in Host mode.
VbusValid latch
1
rd
0b
Set to 1b by the STULPI01 when an unmasked event occurs on
VbusValid. Cleared when this register is read.
SessValid latch
2
rd
0b
Set to 1b by the STULPI01 when an unmasked event occurs on
SessValid. Cleared when this register is read. SessValid is the
same as UTMI+AValid.
SessEnd latch
3
rd
0b
Set to 1b by the STULPI01 when an unmasked event occurs on
SessEnd. Cleared when this register is read.
ID latch
4
rd
0b
Set to 1b by the STULPI01 when an unmasked event occurs on
ID. Cleared when this register is read. ID is valid 50 ms after ID
is set to 1b, otherwise ID is undefined and should be ignored.
7:5
rd
0b
Reserved
Reserved
Note:
Address 14h(Read-only with auto-clear).
These bits are set by the STULPI01 when an unmasked change occurs on the
corresponding internal signal. The STULPI01 automatically clears all bits when the link
reads this register, or when Low-power mode is entered. The STULPI01 also clears this
register when Serial mode or Car Kit mode is entered regardless of the value of
ClockSuspendM. The interrupt circuitry is powered down in any mode when both rising and
falling edge enables are disabled. To ensure the interrupts are detectable when the clock is
powered down, the link should enable both rising and falling edges.
The STULPI01 follows the rules in Table 20 for setting any latch register bit. It is important to
note that if the register read data is returned to the link in the same cycle that a USB
interrupt latch bit is to be set, the interrupt condition is given immediately in the register read
data and the latch bit is not set.
Note that it is optional for the link to read the USB interrupt latch register in Synchronous
mode because the RX CMD byte already indicates the interrupt source directly.
Table 24.
Setting rules for interrupt latch register
Input conditions
Resultant value of latch register bit
Register read data returned in
current clock cycle
Interrupt latch bit is to be set in
current clock cycle
No
No
0
No
Yes
1
Yes
No
0
Yes
Yes
0
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ULPI registers
Table 25.
STULPI01A, STULPI01B
Debug register
Field name
Bits
Access
Reset
Description
LineState0
0
rd
0b
Contains the current value of LineState(0)
LineState1
1
rd
0b
Contains the current value of LineState(1)
Reserved
7:2
rd
0b
Reserved
Note:
Address 15h(Read-only) indicates the current value of various signals useful for debugging.
Table 26.
Scratch register
Field name
Bits
Access
Reset
Description
Scratch
7:0
rd/wr/s/c
00b
Empty register byte for testing purposes. The software can
read, write, set, and clear this register and the STULPI01
functionality is not affected.
Note:
Address 16h-18h(Read), 16h(Write), 17h(Set), 18h(Clear).
Table 27.
Car kit control register
Field name
Bits
Access
Reset
Reserved
0
rd/wr/s/c
0b
Reserved
1
rd/wr/s/c
0b
TxdEn
2
rd/wr/s/c
0b
Enables TXD signal in Car Kit mode
RxdEn
3
rd/wr/s/c
0b
Enables RXD signal in Car Kit mode
Reserved
4
rd/wr/s/c
0b
Reserved
5
rd/wr/s/c
0b
Reserved
6
rd/wr/s/c
0b
Reserved
7
rd/wr/s/c
0b
Note:
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Description
Address 19h-1Bh(Read), 19h(Write), 1Ah(Set), 1Bh(Clear).
Doc ID 14817 Rev 4
STULPI01A, STULPI01B
9
Package mechanical data
Package mechanical data
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK is an ST trademark.
Doc ID 14817 Rev 4
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Package mechanical data
STULPI01A, STULPI01B
Figure 13. µTFBGA36 package outline
"
Table 28.
µTFBGA36 mechanical data
Dimensions
Symbol
mm .
Min.
Typ.
Max.
Min.
Typ.
Max.
A
0.93
1.1
1.11
36.6
3.3
43.7
A1
0.15
0.25
5.9
9.8
A2
0.78
0.86
30.7
33.9
b
0.25
0.30
0.35
9.8
11.8
13.8
D
3.5
3.6
3.7
137.8
141.7
145.7
D1
E
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mils.
2.5
3.5
3.6
98.4
3.7
137.8
141.7
E1
2.5
98.4
e
0.5
19.7
F
0 .55
21 .7
Doc ID 14817 Rev 4
145.7
STULPI01A, STULPI01B
Package mechanical data
Figure 14. Tape and reel µTFBGA36 package outline
4A2
4&"'!
1. Drawing not to scale.
Table 29.
Tape and reel µTFBGA36 mechanical data
Dimensions
mm.
Symbol
Min.
Typ.
A
inch.
Max.
Min.
Typ.
330
13.2
12.992
C
12.8
D
20.2
0.795
N
60
2.362
T
Max.
0.504
0.519
14.4
0.567
Ao
3.9
0.154
Bo
3.9
0.154
Ko
1.50
0.059
Po
3.9
4.1
0.154
0.161
P
7.9
8.1
0.311
0.319
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Order codes
STULPI01A, STULPI01B
10
Order codes
Table 30.
Order codes
Order code
STULPI01ATBR(1)
Key differences
Package
Packaging
fOSC = 19.2 MHz, CSn/PWRDN = 0 “ON” µTFBGA36 (3.6 x 3.6 mm typ.) 3000 parts per reel
STULPI01BTBR(1) fOSC = 26 MHz, CSn/PWRDN = 0 “ON”
µTFBGA36 (3.6 x 3.6 mm typ.) 3000 parts per reel
1. All these versions need a digital external clock on the XI pin; the XO pin must be left floating or grounded (crystal is not
supported).
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Doc ID 14817 Rev 4
STULPI01A, STULPI01B
Revision history
11
Revision history
Table 31.
Document revision history
Date
Revision
Changes
20-Jun-2008
1
First release.
24-Sep-2010
2
Replaced “IV8VIO” with “DVIO” throughout datasheet; updated Table 2, 3, 5, 7;
updated ECOPACK® text in Section 9; reformatted document, minor textual changes.
26-Jan-2011
3
Updated Table 2, 3, 12; updated pin name to VDVIO throughout document; minor
formatting changes.
07-Jun-2012
4
Updated Section 9 (data in Table 28, titles of Figure 13 and Figure 14, Table 28 and
Table 29), minor text corrections throughout document.
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STULPI01A, STULPI01B
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