STULPI01B

STULPI01A STULPI01B High speed USB On-The-Go ULPI transceiver Features ■ ■ USB-IF high speed certified to the Universal Serial Bus specification Rev 2.0. Meets the requirements of the Universal Serial Bus specification revision 2.0, On-The-Go supplement to the USB 2.0 specification 1.0a and ULPI transceiver specification 1.1. Standard ULPI (UTMI+ low pin interface) 1.1 digital interface. Fully compliant with ULPI 1.1 register set. External square wave clock with 1V8VIO amplitude must be applied to oscillator input XI. Supports 480 Mbit/s high speed, 12 Mbit/s fullspeed and 1.5 Mbit/s low speed modes of operation. Supports 2.7 V UART mode. Supports session request protocol (SRP) and host negotiation protocol (HNP) for dual-role device features. Ability to control external charge pump for higher VBUS currents. Single supply, +3 V to +4.5 V voltage range. Integrated dual voltage regulator to supply internal circuits with stable 3.3 V and 1.2 V. Integrated over current detector. Integrated HS termination and FS/LS/OTG pull-up/pull-down resistors. Integrated USB 2.0 “short-circuit withstand” protection. Power down mode with very low power consumption for battery-powered devices. Ideal for system ASICs with built-in USB host, device or OTG cores. Available in µTFBGA36 RoHS package. -40 °C to 85 °C operating temperature range. µTFBGA36 ■ ■ ■ ■ Applications ■ ■ ■ ■ ■ ■ Mobile phones PDAs MP3 players Digital still cameras Set top box Portable navigation devices ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ Description The STULPI01 is a high speed USB 2.0 transceiver compliant with ULPI (UTMI+ low pin interface) and OTG (On-The-Go) specifications, providing a complete physical layer solution for any high speed USB host, device or OTG dual role core. It allows USB ASICs to interface with the physical layer of the USB through a 12-pin interface. It contains VBUS comparators, ID line detector, USB differential driver and receivers and complete ULPI register map and interrupt generator. The STULPI01 transceiver is suitable for mobile applications and battery powered devices because of its low power consumption, power down operating mode and minimal die/package dimensions. June 2008 Rev 1 1/44 www.st.com 44 Contents STULPI01A - STULPI01B Contents 1 2 3 4 5 6 Application diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Bump configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Block description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 6.1 6.2 6.3 6.4 6.5 6.6 6.7 6.8 6.9 6.10 6.11 6.12 6.13 Oscillator and PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Voltage reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Power-on-reset (POR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 UTMI + CORE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 ULPI wrapper . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 External charge pump . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 VBUS comparators and VBUS over current (OC) detector . . . . . . . . . . . 19 VB_REF_FAULT pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 ID detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 USB 2.0 PHY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Power saving features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Modes of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 6.13.1 6.13.2 6.13.3 ULPI synchronous mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 6 pin FS/LS serial mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3 pin FS/LS serial mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 6.14 6.15 6.16 6.17 6.18 Car kit (UART) mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Low power mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Power down mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 VIO OFF mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Start-up procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 6.18.1 ULPI device detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 2/44 STULPI01A - STULPI01B 6.18.2 6.18.3 6.18.4 6.18.5 6.18.6 6.18.7 Contents SDR mode selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 External clock detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Reset behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Interface protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Software reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 High speed mode entry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 7 8 9 10 11 State transitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 ULPI registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Order codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 3/44 List of tables STULPI01A - STULPI01B List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Table 24. Table 25. Table 26. Table 27. Table 28. Table 29. Bill of materials - external components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Pinout and bump description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 High-speed driver eye pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 VB_REF_FAULT configuration bit settings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Car kit signals mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Low power mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 USB state transitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 ULPI register map overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Register access legend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Vendor and product ID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Power control registe . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Function control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Interface control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 OTG control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 USB interrupt enable rising register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 USB interrupt enable falling register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 USB interrupt status register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 USB interrupt latch register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Setting rules for interrupt latch register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Debug register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Scratch register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Carkit control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Order codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 4/44 STULPI01A - STULPI01B List of figures List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Peripheral only. Configuration with external clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Pin connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 High-speed driver eye pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Rise and fall time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Simplified block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 VB_REF_FAULT pin functionality. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 USB 2.0 PHY block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Start-up sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 RESETn behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 High speed mode entry. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 UART mode entry (2.7 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 UART mode exit (2.7 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 5/44 Application diagrams STULPI01A - STULPI01B 1 Figure 1. Application diagrams Peripheral only. Configuration with external clock Table 1. Q.ty Bill of materials - external components Symbol Value Description Filtering capacitor. Suggested components: muRata 10 V X5R (GRM188R61A105KA61) or muRata 10 V Y5V (GRM188F51A105ZA01) or Taiyo Yuden 25V X5R (TMK107BJ105KA) Filtering capacitor. Suggested components: muRata 10 V X5R (GRM188R61A105KA61) or muRata 10 V Y5V (GRM188F51A105ZA01) or Taiyo Yuden 25V X5R (TMK107BJ105KA) Filtering capacitor. Suggested components: muRata 10 V X5R (GRM188R61A105KA61) or muRata 10 V Y5V (GRM188F51A105ZA01) or Taiyo Yuden 25V X5R (TMK107BJ105KA) Filtering capacitor. Suggested components: muRata 10 V Y5V (GRM188F51A475ZE20) or Taiyo Yuden 6.3 V X5R (JMK107BJ475KA) Tank capacitor Reference resistor ±1% USBULC6-2F3 ESDA14V2-2BF3 2.2 kΩ Series over-voltage protection resistor 1 CF1 0.1 - 1 µF 2 CF4 0.1 - 1 µF 1 CF2 1µF - 1.5 µF 1 1 1 1 1 1 6/44 CF3 CT RREF E1 E2 RBUS 1 - 4.7 µF 4.7 µF 12 kΩ STULPI01A - STULPI01B Bump configuration 2 Figure 2. Bump configuration Pin connections 1 A B C D E F 2 3 4 5 6 F NC NC VBAT VBUS XI XO E GND VB_REF _FAULT 3V3V GND DIR 1V2V D DP GND ID PSWn NXT STP C DM RREF CSn/ RESETn PWRDN GND D7 B D0 1V8 VIO 1V8 VIO GND 1V8 VIO D6 A D1 D2 D3 CLK D4 D5 1 2 3 4 5 6 µTFBGA36 (through top side view) µTFBGA36 (bottom view) Table 2. Bump B1 A1 A2 A3 A4 A5 A6 B6 C6 D6 D5 E5 C3 C4 D1 C1 D3 F4 F1 Pinout and bump description Symbol D0 D1 D2 D3 CLK D4 D5 D6 D7 STP NXT DIR CSn/PWRDN RESETn DP DM ID VBUS NC Type I/O I/O I/O I/O O I/O I/O I/O I/O I O O I I I/O I/O I I/O Description Data bit[0] (1V8VIO referred). UART TXD signal. Data bit[1] (1V8VIO referred). UART RXD signal. Data bit[2] (1V8VIO referred). UART reserved pin. Data bit[3] (1V8VIO referred). UART active high interrupt indication. Clock out (1V8VIO referred). Data bit[4] (1V8VIO referred). Data bit[5] (1V8VIO referred). Data bit[6] (1V8VIO referred). Data bit[7] (1V8VIO referred). ULPI stop signal (1V8VIO referred). ULPI next signal (1V8VIO referred). ULPI direction signal (1V8VIO referred). Chipselect active low, power down active high. Active low asynchronous reset. Positive data line of the USB. 5V tolerant. Negative data line of the USB. 5V tolerant. ID pin of the USB connector for initial device role selection. 5V tolerant. VBUS line of the USB interface, requires an external capacitor of 4.7µF. Not connected. 7/44 Bump configuration Table 2. Bump F2 E2 D4 F5 F6 F3 E3 E6 C2 B2/B3/B5 C5/D2 B4/E4/E1 STULPI01A - STULPI01B Pinout and bump description (continued) Symbol NC VB_REF_FAULT PSWn XI XO VBAT 3V3V 1V2V RREF 1V8VIO GND GND I O I O PWR Type Not connected. Voltage reference for internal OC detector input or digital input from external OC detector (V3V3V referred). 5V tolerant. External charge pump control, active low. 5V tolerant, open drain. External clock input (1V8VIO referred). Crystal terminal (on request). Left floating or connect to GND when external clock signal is used. Crystal terminal on request. Battery power input for the LDO (3 V – 4.5 V). Bypass VBAT to GND with a 1µF capacitor. Description PWR 3.3V LDO output. Bypass 3V3V to GND with a 1.5µF capacitor. PWR 1.2V LDO output. Bypass 1V2V to GND with a 1.5µF capacitor. I/O PWR Reference resistor (12kΩ ±1%). Digital I/O supply voltage 1.8V. Bypass each 1V8VIO to GND with a 100nF-1uF capacitor. Balls B2-B5 can share common capacitor. PWR Ground. PWR Ground. 8/44 STULPI01A - STULPI01B Maximum ratings 3 Table 3. Symbol V1V8VIO V1V2 V3V3 VBAT VDCDIG VDCANA VDCVBUS TSTG VESD-HBM Maximum ratings Absolute maximum ratings Parameter Digital I/O supply voltage Digital core supply voltage (provided internally by LDO) Analog supply voltage (provided internally by LDO) Battery supply voltage DC voltage on digital pins (CLK, DIR, STP, NXT, D[0-7], RESETn) DC voltage on analog pins (XI, XO, PSWn) DC voltage on 5V tolerant pins (VBUS,VB_REF_FAULT, DP, DM, ID) Storage temperature range Electrostatic discharge voltage on all pins (according to JESD22A114-B) Value -0.3 to +2.0 -0.3 to +1.4 -0.3 to +4.0 -0.3 to +7.0 -0.3 to +2.0 -0.3 to +4.0 -0.3 to +5.5 -40 to +125 ±2.0 Unit V V V V V V V °C kV Note: Absolute maximum ratings are those values above which damage to the device may occur. Functional operation under these conditions is not implied. All voltages are referenced to GND. Thermal data Parameter Thermal resistance junction-ambient (simulated value as per JEDEC JSD51) Thermal resistance junction-case (simulated value as per JEDEC JSD51) Thermal resistance junction-base (simulated value as per JEDEC JSD51) Value 113.8 47 66.2 Unit °C/W °C/W °C/W Table 4. Symbol RthJA RthJC RthJB Table 5. Symbol VBAT Recommended operating conditions Parameter Battery supply voltage Min. 3.0 1.65 -40 1 11.88 4.7 12 19.2 or 26 4 Typ. 3.6 1.80 Max. 4.5 1.95 +85 6.5 12.12 Unit V V °C µF kΩ MHz ns V1V8VIO Digital I/O supply voltage TA CT RREF XTAL Recommended rise/fall time Operating temperature range Tank capacitor External reference resistor External square wave (01A, 01B versions) 9/44 Electrical characteristics STULPI01A - STULPI01B 4 Table 6. Electrical characteristics Electrical characteristics (Characteristics measured over recommended operating conditions unless otherwise noted. All typical values are referred to TA = 25 °C, V1V8IO = 1.8 V, VBAT = 3.6 V, RREF = 12 kΩ; CT = 4.7 µF) Parameter Test conditions Min. Typ. Max. Unit Symbol Power consumption Active mode (USB bus idle) Active mode (FS transmission, 12Mb/s traffic) Active mode (HS transmission) IBAT Supply current Suspend mode (not including DP pull-up current, external clock stopped) UART mode (no transmission) Power down mode VIO OFF mode (1V8VIO=0) I1V8VIO ULPI bus supply current 1V8VIO Power down mode Active mode, 4pF load 15 30 mA mA 50 mA 120 µA 15 0.4 0.4 0.1 1.8 2 2 10 mA µA µA µA mA Logic inputs and outputs CULPIIN VOH VOL IOZH_PSWn VOL_PSWn VIH VIL IIH ULPI port I/O capacitance High level output voltage (ULPI bus) Low level output voltage (ULPI bus) High level output leakage (PSWn) Low level output voltage (PSWn) High level input voltage (ULPI port and RESETn) Low level input voltage (ULPI port and RESETn) High level input leakage current VIH = V1V8VIO-0.2V IOH = -2 mA IOL = +2 mA VOH_PSWn = 3.3V power switch disabled IOL = +2 mA power switch enabled 0.65xV1V8VIO 0.35xV1V8VIO ±1.0 V1V8VIO-0.15 0.15 1.0 0.15 2.4 3.5 pF V V µA V V V µA 10/44 STULPI01A - STULPI01B Table 6. Electrical characteristics Electrical characteristics (continued) (Characteristics measured over recommended operating conditions unless otherwise noted. All typical values are referred to TA = 25 °C, V1V8IO = 1.8 V, VBAT = 3.6 V, RREF = 12 kΩ; CT = 4.7 µF) Parameter Low level input leakage current High level input voltage (CSn/PWRDN pin) Low level input voltage (CSn/PWRDN pin) High level input leakage current (CSn/PWRDN pin) Low level input leakage current (CSn/PWRDN pin) High level input voltage (VB_REF_FAULT pin) Low level input voltage (VB_REF_FAULT pin) VB_REF_FAULT pin input resistance External clock input hysteresis High level input voltage (XI pin) XO = ‘0’ @ reset XO = ‘0’ @ reset 0.65xV1V8VIO 0.15xV1V8VIO Test conditions VIL = 0.2V VBAT=3.0V to 4.5V VBAT=3.0V to 4.5V 1.4 0.4 Min. Typ. Max. ±1.0 Unit µA V V Symbol IIL VPDH VPDL IPDH VPD = 1.4V, VBAT = 4.5V ±1.0 µA IPDL VPD = 0.4V, VBAT = 4.5V ±1.0 µA VFAULTH VFAULTL RIN_VB_REF VXI_HYST_EXT VXIH VXIL VBUS VBUS_LKG RVBUS VBUS_VLD Overcurrent_PD bit is set Overcurrent_PD bit is set 0.65xV3V3 0.15xV3V3 112 148 500 168 V V kΩ mV V V Low level input voltage (XI XO = ‘0’ @ reset pin) VBUS leakage voltage VBUS input impedance VBUS valid comparator threshold No load 40 1kΩ series resistors 4.4 0.8 4.75 1.45 1.25 0.2 650 800 950 1250 200 100 mV kΩ V VSESS_VLD Session valid comparator Low to high transition threshold for both A and B High to low transition device Session end comparator threshold VBUS charge pull-up resistance VBUS discharge pull-down resistance 2.0 V V VSESS_END RVBUS_PU RVBUS_PD 0.8 1150 1500 V Ω Ω 11/44 Electrical characteristics Table 6. STULPI01A - STULPI01B Electrical characteristics (continued) (Characteristics measured over recommended operating conditions unless otherwise noted. All typical values are referred to TA = 25 °C, V1V8IO = 1.8 V, VBAT = 3.6 V, RREF = 12 kΩ; CT = 4.7 µF) Parameter Test conditions Min. Typ. Max. Unit Symbol Overcurrent detector VOC ID IID_PU RID_GND RID_FLOAT ID pin pull-up current ID line short resistance to detect ID GND state ID line short resistance to detect ID FLOAT state 100 VID = 0V 70 1 µA kΩ kΩ Over current trip threshold VOC = VB_REF_FAULT – VB_REF_FAULT – VBUS VBUS 20 45 95 mV UART mode (2.7 V ± 5 %) VOH_UART VOL_UART VIH_UART_D0 VIL_UART_D0 VOH_DFMS VOL_DFMS VIH_DTMS VIL_DTMS High level output voltage (D1,D3) Low level output voltage (D1,D3) High level input voltage (D0) Low level input voltage (D0) High level output voltage (DP) Low level output voltage (DP) High level input voltage (DM) Low level input voltage (DM) IOH = -2mA IOL = +2mA, Pull-up=10kΩ 2.16 -0.10 2.0 -0.3 IOH = -2mA IOL = +2mA 0.65xV1V8VIO 0.35xV1V8VIO 2.85 0.37 3.0 0.81 V1V8VIO-0.15 0.15 V V V V V V V V Full-speed/Low-speed driver ZDRV VOH_DRV VOL_DRV VCRS Output impedance (acting also as high-speed termination) High level output voltage Low level output voltage Driver crossover voltage RLH = 14.25kΩ RLL = 1.425kΩ CLOAD=50 to 600pF (1) 40.5 2.8 0.0 1.3 1.67 49.5 3.6 0.3 2.0 Ω V V V High-speed driver VHSOI VHSDPJ VHSDK 12/44 HS idle level HS data DP J state level HS data DP K state level (1) -10 380 -10 10 440 10 mV mV mV STULPI01A - STULPI01B Table 6. Electrical characteristics Electrical characteristics (continued) (Characteristics measured over recommended operating conditions unless otherwise noted. All typical values are referred to TA = 25 °C, V1V8IO = 1.8 V, VBAT = 3.6 V, RREF = 12 kΩ; CT = 4.7 µF) Parameter HS data DN J state level HS data DN K state level Chirp J level (differential voltage) Chirp K level (differential voltage (1) (1) Symbol VHSDNJ VHSDNK VCHIRPJ VCHIRPK Test conditions Min. 380 -10 700 -900 Typ. Max. 440 10 1100 -500 Unit mV mV mV mV Full-speed/Low-speed receivers VDI VSE_TH RINP CIN Diff. receiver input sensitivity (VDP-VDM) SE receivers switching threshold Input resistance Input capacitance Difference in capacitance between DP and DM input Data line leakage voltage RPU_EXT = 300kΩ VCM = 0.8 to 2.5V Low to high transition High to low transition PU/PD resistors deactivated (1) 200 0.8 0.8 300 5 10 342 1.6 1.1 2.0 2.0 mV V V kΩ pF % mV ΔCIN VDT_LKG High-speed receiver VHSSQ VHSDSC VHSCM VHSTERM HS squelch detector threshold HS disconnect detection threshold HS data signaling (1) common mode volt. range Termination voltage in HS (1) 100 525 -50 -10 150 625 500 10 mV mV mV mV Data pull-up/Pull-down resistors RPU VIHZ RPD Data line pull-up resistance (DP, DM) FS idle high level voltage Data line pull-down resistance (DP, DM) 1.425 2.7 14.25 24.8 kΩ V kΩ Voltage regulator 3V3V 1V2V 3.3V internal power supply voltage 1.2V internal power supply voltage VBAT = 3.6V, active mode VBAT = 3.6V, active mode 3.26 1.187 3.4 1.25 3.54 1.31 V V 1. Guaranteed by design. 13/44 Electrical characteristics Table 7. STULPI01A - STULPI01B Switching characteristics (Over recommended operating conditions unless otherwise noted. All the typical values are referred to TA = 25 °C, V1V8VIO = 1.8 V, VBAT = 3.6 V, CT = 4.7 µF) Parameter Test conditions Min. Typ. Max. Unit Symbol Reset tRESETEXT UART mode tRISE tFALL tPD_RX tPD_TX Width of reset pulse on RESETn pin 10 µs Switching time (max low to min high) CLOAD=185pF Switching time (min high to max low) CLOAD=185pF Delay time (50% DM to 50% D1) Delay time (50% D0 to 50% DP) UART_2V7 = 1 measured from DIR assertion UART_2V7 = 1 measured from STP assertion UART_2V7 = 0 measured from DIR assertion UART_2V7 = 0 measured from DIR de-assertion 2 CL=10pF 215 215 60 60 2.5 1 60 60 ns ns ns ns ms µs ns ns tUARTON2V7 Turn-on time for TXD line (2V7) tUARTOFF2V7 Turn-off time for TXD line (2V7) tUARTON tUARTOFF Turn-on time for TXD line Turn-off time for TXD line Low-speed driver tLR tLF RFMLS DRLS tDDJ1 tDDJ2 tLEOPT Data signal rise time Data signal fall time Rise and fall time matching Low-speed data rate Data jitter to next transition Data jitter for paired transitions SE0 interval of EOP Includes freq. tolerances Includes freq. tolerances CLOAD = 600pF CLOAD = 600pF 75 75 -20 1.49925 -25 -14 1250 100 100 300 300 20 ns ns % 1.50075 Mb/s 25 14 1500 ns ns ns Full-speed driver tFR tFF RFMFS DRHS tDJ1 tDJ2 tFEOPT Data signal rise time Data signal fall time Rise and fall time matching Full-speed data rate Data jitter to next transition Data jitter for paired transitions SE0 interval of EOP Includes freq. tolerances Includes freq. tolerances CLOAD = 50pF CLOAD = 50pF 4 4 -10 11.994 -3.5 -4 160 20 20 +10 12.006 3.5 4 175 ns ns % Mb/s ns ns ns Clock generation constants tPLL tDLL 14/44 PLL lock time DLL lock time (1) (1) 200 280 µs µs STULPI01A - STULPI01B Table 7. Electrical characteristics Switching characteristics (continued) (Over recommended operating conditions unless otherwise noted. All the typical values are referred to TA = 25 °C, V1V8VIO = 1.8 V, VBAT = 3.6 V, CT = 4.7 µF) Parameter Test conditions Min. Typ. Max. Unit Symbol High-speed driver tHSR tHSF Data rise time Data fall time Waveform requirements including jitter 500 500 Specified by eye pattern (Figure 3) 479.76 480.24 ps ps DRHS High-speed data rate Mb/s ULPI interface CLOCK (measured on CLK pin) fSTART_U fSTEADY_U DSTART_U DSTEADY_U TSTEADY_U TJITTER_U Frequency (first transition) Frequency (steady state) Duty cycle (first transition) Duty cycle (steady state) Time to reach steady state frequency and duty cycle after first transition Jitter Measured from assertion of STP during suspend, or after release of RESETn pin (1) (1) 54 59.97 40 45 60 60 50 50 66 60.03 60 55 1.4 MHz MHz % % ms ps (1) 400 tSCLK60OUT Clock start up time 250 900 µs ULPI control signals (SDR mode) (1) TSC_U THC_U TDC_U Control in setup time Control in hold time Control output delay CLOAD = 15pF V1V8VIO = 1.65 - 1.95V 6.0 0.0 9.0 ns ns ns ULPI data signals (SDR mode) (1) TSD_U THD_U TDD_U Data in setup time Data in hold time Data output delay CLOAD = 15pF V1V8VIO = 1.65 - 1.95V 6.0 3.0 9.0 ns ns ns 1. Guaranteed by design. 15/44 Electrical characteristics STULPI01A - STULPI01B Figure 3. High-speed driver eye pattern Level 1 Point 3 Point 4 +400mV differential Point 1 Point 2 0V differential Point 5 Level 2 0% Point 6 -400mV differential Unit Interval 100% Table 8. High-speed driver eye pattern Level 1 Level 2 Point 1 0V Point 2 0V Point 3 300mV Point 4 300mV Point 5 -300mV Point 6 -300mV Voltage Level (DP – DM) Time (% of Unit Interval) 525mV (1) -525mV (1) 475mV -475mV 5% 95% 35% 65% 35% 65% 1. This value is valid for unit intervals following a transition. For all other intervals the other value is valid. 16/44 STULPI01A - STULPI01B Timing diagram 5 Figure 4. Timing diagram Rise and fall time Figure 5. Simplified block diagram ID VBUS PSWn VB_REF_FAULT RESETn XI XO 1V8VIO GND CLK DIR STP NXT D0 - D7 Oscillator & PLL OTG Block Charge Pump, VBUS Comparators ID Detector Over Current Fault Detector Power On Reset UTMI + Interface UTMI + Core USB 2.0 PHY Dual Voltage Regulator VBAT GND ULPI ULPI Wrapper Voltage Reference RREF DP DM 17/44 Block description STULPI01A - STULPI01B 6 Block description The STULPI01 integrates a comparator for the VBUS, ID line detector, differential HS data driver, differential and single-ended receivers, low dropout voltage regulators, and control logic. The STULPI01 provides a complete solution for connection of a digital USB host/device/OTG controller to a USB bus. 6.1 Oscillator and PLL An external clock (digital square wave 1V8VIO referred) driven into XI must be used (version STULPI01A or STULPI01B). The PLL internally produces all frequencies needed for operation: ● ● ● ● ● 60 MHz clock for the UTMI core and ULPI interface controller 1.5 MHz for low speed USB data 12 MHz for full speed USB data 480 MHz for high speed USB data Other internal frequencies for data conversion and data recovery 6.2 Voltage reference This block provides the precise reference voltage needed by internal circuit. It requires a 12 kΩ +/- 1% resistor connected to the RREF pin. 6.3 Power-on-reset (POR) The power-on-reset circuit generates a reset pulse upon power-up which is used to initialize the entire digital logic. Power-on-reset senses the V3V3V and V1V2V voltage. During power-on-reset pulse, the ULPI pins are in a high impedance state with pulldown/pull-up resistors disabled. 6.4 UTMI + CORE This is the digital heart of the chip and performs the bit-stuffing, NRZI decoding and serialto-parallel conversion during receive and the reverse operation during transmit for HS and FS/LS. 6.5 ULPI wrapper This implements the ULPI related protocol and conversion from UTMI+ to ULPI interface. This block also implements the interrupt logic and complete ULPI register set. 18/44 STULPI01A - STULPI01B Block description 6.6 External charge pump It is possible to use an external charge pump or power switch controlled by the PSWn pin (active low open drain). This functionality is controlled by DrvVbus and DrvVbusExternal ULPI OTG Control register bits. 6.7 VBUS comparators and VBUS over current (OC) detector These comparators monitor the VBUS voltage. VBUS valid status signalizes that the voltage is above the VBUS_VLD level (4.4 V). Session valid status signalizes that the VBUS voltage is above the VSESS_VLD level (0.8 to 2.0 V). Session end detector signalizes VBUS voltage is below VSESS_END level. STULPI01 also implements embedded VBUS over current detector which compares VBUS voltage to external analog 5 V reference signal applied to VB_REF_FAULT pin. 6.8 VB_REF_FAULT pin VBUS over-current conditions can be monitored by either internal or an external OC detector. The internal OC detector is enabled when over-current_PD bit in the Power Control register (Vendor-specific area) is set to 0b and Use External VBUS Indicator is set to 1b. In this mode, the VB_REF_FAULT pin functions as the input of the analog reference for internal over-current detector. If the external charge pump is already equipped with an over-current detector, its output can be also monitored through VB_REF_FAULT pin, but over-current_PD bit must be set to 1b. In this mode VB_REF_FAULT will function as standard digital input pin with 5 V tolerance. Functionality of VB_REF_FAULT pin can be seen in more detail (on Figure 6). Note: After reset, over-current_PD bit is 1b, internal over-current detector is disabled. Figure 6. VBUS VB_REF_FAULT pin functionality VBUS + REF - VBUSVLD Internal VBUS Valid [0,X] VBREF_FAULT VBUS + [1,0] RX CMD VBUS Valid VBOC 0 [1,1] /EN 1 VBREF - 2 EN RIN_VBREF FAULT [UseExternalVbusIndicator, IndicatorPassthru] SCHMIT (5 V TOLERANT) OverCurrent_PD or neg (UseExternalVbusIndicator) IndicatorComplement 19/44 Block description STULPI01A - STULPI01B Table 9. VB_REF_FAULT configuration bit settings Use External Vbus Indicator 0 1 1 1 1 1 1 Over-current_PD 1 0 0 1 1 1 1 Indicator Pass-true X 1 0 1 1 0 0 Indicator Complement X X X 0 1 1 0 RX CMD VBUS Valid VBUSVLD VBOC VBOC and VBUSVLD neg (FAULT) FAULT VBUSVLD and FAULT VBUS_VLD and neg (FAULT) 6.9 Voltage regulator Dual output ultra low dropout voltage regulator provides power supply for analog and digital internal circuits. An external capacitor on both 3V3V and 1V2V pins is needed for proper operation. 6.10 ID detector This block provides sensing of status of the ID line. It is capable of detecting whether the pin is floating or tied to the ground. 6.11 USB 2.0 PHY The USB 2.0 PHY block provides complete physical layer transceiver for low-speed, fullspeed, and high-speed USB operating modes. Analog part of this block deals with impedances adaptation, controlled voltage swing, and common mode voltage generation and sensing. Digital part consists of serializer and deserializer, transforming serial bit stream to 8-bit parallel port, and finite state machine implementing the PHY protocol layer, bit stuffing, unstuffing etc. 20/44 STULPI01A - STULPI01B Block description Figure 7. USB 2.0 PHY block diagram 3.3V 1.5kΩ HS Ser-Des DP 19.25kΩ 45 Ω LS/FS Ser-Des 3.3V 1.5kΩ DN HS Disconnect Det. Squelch Detector LS/FS SE Receivers 19.25kΩ 6.12 Power saving features To reduce power consumption STULPI01 implements 2 low power modes of operation. 1. Low power mode, which is defined in ULPI specification. 2. Power-down mode to save more power in case USB function is not needed. More information on these modes can be found in following paragraph: 6.13 6.13.1 Modes of operation ULPI synchronous mode STULPI01 transceiver supports SDR mode operation (12 pin interface). The selection of SDR mode is performed during startup reset procedure. 6.13.2 6 pin FS/LS serial mode This mode is entered by writing to corresponding bit in the Interface Control register. 6.13.3 3 pin FS/LS serial mode This mode is entered by writing to corresponding bit in the Interface Control register. 21/44 Block description STULPI01A - STULPI01B 6.14 Car kit (UART) mode This mode is entered by writing to the car kit mode bit in the interface control register. STULPI01 does not implement all features of car kit mode, only the UART functionality is preserved. Table 10. Car kit signals mapping Default car kit signals mapping (UART_DIR = 0) Signal TXD RXD reserved INT DATA[0] (input) ULPI lines -> USB lines DM (output) DP (input) DATA[1] (output) DP (output) DM (input) USB lines DATA[1] (output)