STUSB4700QTR

STUSB4700 Datasheet Stand-alone autonomous USB PD controller with short-to-VBUS protections Features Product status link STUSB4700 • • • • USB power delivery (PD) controller Type-C attach and cable orientation detection Single role: provider Full hardware solution - no software • • • • I2C interface + interrupt (optional connection to MCU) Supports up to 5 power data objects (PDO) Configurable start-up profiles Integrated VBUS voltage monitoring • Internal and/or external VBUS discharge path • • Short-to-VBUS protections on CC pins (22 V) High voltage protections on VBUS pins (28 V) • High and/or low voltage power supply: – VSYS = [3.0 V; 5.5 V] – • • VDD = [4.1 V; 22 V] Automotive grade available Fully compatible with: – USB Type-C™ rev 1.2 – USB PD rev 2.0 – Certification test ID 1030023 Applications • • • • • AC adapters and power supplies for: computer, consumer or portable consumer applications Smart plugs and wall adapters Power hubs and docking stations Displays Any Type-C source device Description The STUSB4700 is a new family of USB power delivery controllers communicating over Type-C™ configuration channel pin (CC) to negotiate a given amount of power to be sourced to an inquiring consumer device. The STUSB4700 addresses provider/DFP devices such as notebooks, tablets and AC adapters. The device can handle any connections to a sink or DRP without any MCU control, from the device attachment to power negotiation, including VBUS discharge and protections. DS11977 - Rev 7 - November 2022 For further information contact your local STMicroelectronics sales office. www.st.com STUSB4700 Functional description 1 Functional description The STUSB4700 is an autonomous USB power delivery controller optimized as a provider. It offers an open drain GPIO interface to make direct interconnection with a power regulation stage. The STUSB4700 offers the benefits of a full hardware USB PD stack allowing robust and safe USB PD negotiation in line with USB PD standard. The STUSB4700 is ideal for provider applications in which digital or software intelligence is limited or missing. The STUSB4700 main functions are: • • • Detect the connection between two USB ports (attach detection) Establish a valid host to device connection Discover and configure VBUS: Type-C low, medium or high current mode • • • • Resolve cable orientation Negotiate a USB power delivery contract with a PD capable device Configure the power source accordingly Monitor VBUS, manage transitions, handle protections and ensure user and device safety Additionally, the STUSB4700 offers 5 customizable power data objects (PDOs), 5 general purpose I/Os, an integrated discharge path, and is natively robust to high voltage peaks. Figure 1. Functional block diagram VDD VSYS VREG_2V7 Internal supply VBUS status voltage monitoring VREG_1V2 VBUS_EN_SRC ALERT# Discharge path VCONN SW (OVP & OCP) A_B_SIDE SCL SDA VBUS_SENSE Port C controller I²C slave CC line access port status VVAR_ADDR0 VBUS_DISCH GPIO[4..0] RESET VCONN CC1 CC2 Control POR & reset generator Device Policy Manager Policy Engine Protocol Layer Physical Layer BMC driver GND DS11977 - Rev 7 page 2/41 STUSB4700 Inputs/outputs 2 Inputs/outputs 2.1 Pinout VSYS VREG_1V2 VBUS_EN_SRC VBUS_DISCH 1 24 23 22 21 20 19 VDD VREG_2V7 Figure 2. Pin connections (top view) NC VBUS_SENSE CC1 2 17 A_B_SIDE VCONN 3 16 GPIO4 15 GPIO3 14 GPIO2 13 VVAR_ADDR0 CC2 4 NC 5 7 8 9 10 11 12 SDA ALERT# GND GPIO1 GPIO0 6 EP SCL RESET DS11977 - Rev 7 18 page 3/41 STUSB4700 Pin list 2.2 Pin list Table 1. Pin function list Pin Name Type Description Connection 1 NC 2 CC1 HV AIO 3 VCONN PWR 4 CC2 HV AIO 5 NC - 6 RESET DI Reset input (active high) 7 SCL DI I²C clock input To I²C master – ext. pull-up 8 SDA DI/OD I2C data input/output – active low open drain To I²C master – ext. pull-up I2C To I²C master – ext. pull-up Ground reference channel 1 To ground Type-C configuration channel 1 Type-C receptacle A5 Power input for active plug 5 V power source Type-C configuration channel 2 Type-C receptacle B5 Ground reference channel 2 To ground 9 ALERT# OD 10 GND GND 11 GPIO1 OD General purpose I/O #1 12 GPIO0 OD General purpose I/O #0 13 VVAR_ADDR0 AIO Variable voltage output I2C device address 0 bit (at start-up) 14 GPIO2 OD General purpose I/O #2 15 GPIO3 OD General purpose I/O #3 16 GPIO4 OD General purpose I/O #4 17 A_B_SIDE OD Cable orientation - active low open drain USB SuperSpeed mux select – ext. pull-up 18 VBUS_SENSE HV AI VBUS voltage monitoring and discharge path From VBUS 19 VBUS_DISCH HV OD External output discharge path enable, active low open drain 20 VBUS_EN_SRC HV OD VBUS source power path enable – active low open drain To switch or power system – ext. pull-up 21 VREG_1V2 PWR 1.2 V internal regulator output 1 µF typ. decoupling capacitor 22 VSYS PWR Power supply from system System low power (connect to ground if not used) 23 VREG_2V7 PWR 2.7 V internal regulator output 1 µF typ. decoupling capacitor 24 VDD HV PWR Power supply from USB power line From VBUS (system side) - EP Exposed pad Exposed pad is connected to ground To ground DS11977 - Rev 7 interrupt – active low open drain Ground To ground page 4/41 STUSB4700 Pin list Table 2. Legend Type DS11977 - Rev 7 Description D Digital A Analog O Output pad I Input pad IO Bidirectional pad OD Open drain output PD Pull-down PU Pull-up HV High voltage PWR Power GND Ground page 5/41 STUSB4700 Pin description 2.3 Pin description 2.3.1 CC1 / CC2 CC1 and CC2 are the configuration channel pins used for connection and attachment detection, plug orientation determination and system configuration management across USB Type-C cable. CC1 and CC2 are high impedance (HiZ) during reset. 2.3.2 RESET Active high reset. This pin resets all analog signals, states machine and reloads configuration. 2.3.3 I²C interface pins Table 3. I2C interface pin list Name SCL I²C clock – need external pull-up SDA I²C data – need external pull-up ALERT# 2.3.4 Description I²C interrupt – need external pull-up A_B_SIDE This output pin provides cable orientation. It is used to establish USB SuperSpeed signals routing. The cable orientation is also provided by an internal I2C register. This signal is not required in case of USB 2.0 support or in case of supply only. Table 4. USB data mux select Value 2.3.5 CC pin position HiZ CC1 pin is attached to CC line 0 CC2 pin is attached to CC line VBUS_SENSE This input pin is used to sense VBUS presence, monitor VBUS voltage and discharge VBUS on USB Type-C receptacle side. 2.3.6 VBUS_EN_SRC In source power role, this pin allows enabling of the outgoing VBUS power when the connection to a sink is established and VBUS is in the valid operating range. The open-drain output allows a PMOS transistor to be driven directly. The logic value of the pin is also advertised in a dedicated I2C register bit. 2.3.7 VSYS This is the low voltage power supply from the system (if any). VSYS connection is optional, and can be connected directly to a single cell Lithium battery or a system power supply delivering 3.3 V or 5 V. If not used, it is recommended to connect the pin to ground. DS11977 - Rev 7 page 6/41 STUSB4700 Pin description 2.3.8 VDD This is the main power supply from the USB power line for applications powered by VBUS. This pin can be used to sense the voltage level of the main power supply providing VBUS. It allows UVLO and OVLO voltage thresholds to be considered independently on VDD pin as additional conditions to enable the VBUS power path through VBUS_EN_SRC pin. 2.3.9 GND Ground. 2.3.10 VVAR_ADDR0 At start-up, this pin is latched to set I²C device address 0 bit. During operation, this output can be used as an analog voltage output to control the power management unit. Analog value is one tenth of the requested VBUS value. This function can be enabled through appropriate non-volatile-memory (NVM) configuration. 2.3.11 VREG_2V7 This pin is used only for external decoupling of 2.7 V internal regulator. Recommended decoupling capacitor: 1 µF typ. (0.5 µF min.; 10 µF max.). This pin must not be used to supply any external component. 2.3.12 VREG_1V2 This pin is used for external decoupling of 1.2 V internal regulator. Recommended decoupling capacitor: 1 µF typ. (0.5 µF min.; 10 µF max.). This pin must not be used to supply any external component. 2.3.13 VBUS_DISCH This output pin allows an external VBUS discharge path to be controlled in addition to the internal discharge path when required by the application. The output pin is active at the same time as the activation of the internal discharge path. 2.3.14 VCONN This power input is connected to a power source that can be a 5 V power supply, or a lithium battery. It is used to supply e-marked cables. It is internally connected to power switches that are protected against short-circuit and overvoltage. When a valid source-to-sink connection is determined and VCONN power switches enabled, VCONN is provided by the source to the unused CC pin. DS11977 - Rev 7 page 7/41 STUSB4700 Pin description 2.3.15 GPIO [4:0] Table 5. GPIO0 (pin #12) configuration Select NVM value GPIO0_sel Configuration 00b Attach 01b Reserved 10b Reserved 11b Sel_PDO2 Comments Attached to sink (active low) Do not use PDO2 contract (active low) Table 6. GPIO1 (pin #11) configuration Select NVM value GPIO1_sel Configuration 00b VBUS_VALID 01b Reserved 10b Reserved 11b Sel_PDO3 Comments VBUS at expected voltage (active low) Do not use PDO3 contract (active low) Table 7. GPIO2 (pin #14) – GPIO3 (pin #15) – GPIO4 (pin #16) configuration Select NVM value 00b 01b GPIO234_sel[1:0] 10b 11b Configuration Comments GPIO2 = Sel_PDO2 PDO2 contract (active low) GPIO3 = Sel_PDO3 PDO3 contract (active low) GPIO4 = VBUS_EN_SRC_N Not VBUS_EN_SRC (active high) GPIO2 = ADDR1 I2C device address 1 bit (at start-up) GPIO3 = ADDR2 I2C device address 2 bit (at start-up) GPIO4 = DEBUG1 SNK_DEBUG_ACCESSORY from Type-C Reserved Do not use GPIO2 = Sel_PDO4 PDO4 contract (active low) GPIO3 = Sel_PDO5 PDO5 contract (active low) GPIO4 = V_TRANS_UP PDO transition up (active low for 280 ms) Other configurations are available (please contact our customer support). DS11977 - Rev 7 page 8/41 STUSB4700 Block descriptions 3 Block descriptions 3.1 CC interface The STUSB4700 controls the connection to the configuration channel (CC) pins, CC1 and CC2, through two main blocks, the CC lines interface block and the CC control logic block. The CC lines interface block is used to: • • • Configure the pull-up termination mode on the CC pins Monitor the CC pin voltage values relative to the attachment detection thresholds Configure VCONN on the unconnected CC pin when required • Protect the CC pins against over voltage The CC control logic block is used to: • • • • • • • Execute the Type-C FSM relative to the Type-C source power mode Determine the electrical state for each CC pins relative to the detected thresholds Evaluate the conditions relative to the CC pin states and VBUS voltage value to transition from one state to another in the Type-C state machine Detect and establish a valid source-to-sink connection Determine the attached device type: sink or accessory Determine cable orientation to allow external routing of the USB SuperSpeed data Expose VBUS power capability: USB default, Type-C medium or Type-C high current mode • Handle hardware faults The CC control logic block implements the Type-C state machines corresponding to source power role with accessory support. 3.2 BMC This block is the physical link between USB PD protocol layer and CC pin. In TX mode, it converts the data into bi-phase mark coding (BMC), and drives the CC line to correct voltages. In RX mode, it recovers BMC data from the CC line, and converts to baseband signaling for the protocol layer. 3.3 Protocol layer The protocol layer has the responsibility to manage the messages from/to the physical layer. It automatically manages the protocol receive timeouts, the message counter, the retry counter and the GoodCRC messages. It communicates with the internal policy engine. 3.4 Policy engine The policy engine implements the power negotiation with the connected device according to its source role, it implements all states machine that controls protocol layer forming and scheduling the messages. The policy engine uses the protocol layer to send/receive messages. The policy engine interprets the device policy manager’s input in order to implement policy for port and directs the protocol layer to send appropriate messages. 3.5 Device policy manager The device policy manager is managing the power resources. 3.6 3.6.1 VBUS power path control VBUS monitoring The VBUS monitoring block supervises from the VBUS_SENSE input pin the VBUS voltage on the USB Type-C receptacle side. This block is used to check that VBUS is within a valid voltage range: DS11977 - Rev 7 page 9/41 STUSB4700 VBUS power path control • • To establish a valid source-to-sink connection according to USB Type-C standard specification To enable safely the VBUS power path through VBUS_EN_SRC pin It allows detection of unexpected VBUS voltage conditions such as undervoltage or overvoltage relative to the valid VBUS voltage range. When such conditions occur, the STUSB4700 reacts as follows: • At attachment, it prevents the source-to-sink connection and the VBUS power path assertion • After attachment, it deactivates the source-to-sink connection and disables the VBUS power path. The device goes into error recovery state The VBUS voltage value is automatically adjusted at attachment and at each PDO transition. The monitoring is then disabled during T_Transition_To_PDO (default 288 ms changed through NVM programming). Additionally, if a transition occurs to a lower voltage, the discharge path is activated during this time. The valid VBUS voltage range is defined from the VBUS nominal voltage by a high threshold voltage and a low threshold voltage whose minimal values are respectively VBUS+5% and VBUS-5%. The nominal threshold limits can be shifted by a fraction of VBUS from +1% to +15% for the high threshold voltage and from -1% to -15% for the low threshold voltage. It means the threshold limits can vary from VBUS+5% to VBUS+20% for the high limit and from VBUS-5% to VBUS-20% for the low limit. The threshold limits are preset by default in the NVM with different shift coefficients (see Section 8.3 Electrical and timing characteristics). The threshold limits can be changed independently through NVM programming (see Section 4 User-defined start-up configuration) and also by software during attachment through the I2C interface (see Section 6 I²C register map). 3.6.2 VBUS discharge The monitoring block handles also the internal VBUS discharge path connected to the VBUS_SENSE input pin. The discharge path is activated at detachment, during transition to a lower PDO voltage, or when the device goes into the error recovery state (see Section 3.8 Hardware fault management). The automatic VBUS discharge path feature is enabled by default in the NVM and can be disabled through NVM programming only (see Section 4 User-defined start-up configuration). Discharge time duration (T_Transition_To_PDO and T_Transition_To_0V) are also preset by default in the NVM (see Section 8.3 Electrical and timing characteristics). The discharge time duration can be changed through NVM programming (see Section 4 User-defined start-up configuration) and also by software through the I2C interface (see Section 6 I²C register map). 3.6.3 VBUS power path assertion The STUSB4700 can control the assertion of the VBUS power path on USB Type-C port, directly or indirectly, through VBUS_EN_SRC pin. The following table summarizes the configurations of the STUSB4700 and the operation conditions that determine the electrical value of the VBUS_EN_SRC pin during system operations. Table 8. Conditions for VBUS power path assertion Pin Electrical value Operating conditions Type-C attached state VDD monitoring Attached.SRC VDD > VDDUVLO if UVLO threshold detection enabled UnorientedDebug 0 OrientedDebug Accessory.SRC VBUS_EN_SRC HiZ DS11977 - Rev 7 Accessory.SRC Any other state and/or VDD < VDDOVLO if OVLO threshold detection enabled VDD < VDD if UVLO threshold detection enabled or VDD > VDDOVLO if OVLO threshold detection enabled VBUS-SENSE pin monitoring Comment VBUS < VMONUSBH and VBUS > VMONUSBL if VBUS voltage range detection enabled or VBUS > VTHUSB if VBUS voltage range detection disabled The signal is asserted only if all the valid operation conditions are met VBUS > VMONUSBH or VBUS < VMONUSBL if VBUS voltage range detection enabled or VBUS < VTHUSB if VBUS voltage range detection disabled The signal is deasserted when at least one non-valid operation condition is met page 10/41 STUSB4700 High voltage protection Note: Activation of the UVLO and OVLO threshold detections can be done through NVM programming (see Section 4 User-defined start-up configuration) and also by software through the I2C interface (see Section 6 I²C register map). When the UVLO and/or OVLO threshold detection is activated, the VBUS_EN_SRC pin is asserted only if the device is attached and the valid threshold conditions on VDD are met. Once the VBUS_EN_SRC pin is asserted, the VBUS monitoring is done on VBUS_SENSE pin instead of the VDD pin. 3.7 High voltage protection The STUSB4700 can be safely used in systems or connected to systems that handle high voltage on the VBUS power path. The device integrates an internal circuitry on the CC pins that tolerates high voltage and ensures a protection up to 22 V in case of unexpected short circuit with VBUS or in case of connection to a device supplying high voltage on VBUS. 3.8 Hardware fault management The STUSB4700 handles hardware fault conditions related to the device itself and to the VBUS power path during system operation. When such conditions happen, the circuit goes into a transient error recovery state named ErrorRecovery in the Type-C FSM. The error recovery state is equivalent to force a detach event. When entering this state, the device de-asserts the VBUS power path by disabling the VBUS_EN_SRC pin, and it removes the terminations from the CC pins during several tens of milliseconds. Then, it transitions to the unattached source state. The STUSB4700 goes into error recovery state when at least one condition listed below is met: • • • • If an overtemperature is detected, the “THERMAL_FAULT” bit is set to 1b If an internal pull-up voltage on CC pins is below UVLO threshold, the “VPU_VALID” bit is set to 0b If an overvoltage is detected on the CC pins, the “VPU_OVP_FAULT” bit is set to 1b If the VBUS voltage is out of the valid voltage range during attachment, the “VBUS_VALID” bit is set to 0b • If an undervoltage is detected on the VDD pin during attachment when UVLO detection is enabled, the “VDD_UVLO_DISABLE” bit is set to 0b If an overvoltage is detected on the VDD pin during attachment when OVLO detection is enabled, the “VDD_OVLO_DISABLE” bit is set to 0b • The I2C register bits mentioned above in quotes give either the state of the hardware fault when it occurs or the setting condition to detect the hardware fault. 3.9 Accessory mode detection The STUSB4700 supports the detection of audio accessory mode and debug accessory mode as defined in the USB Type-C standard specification source power role with accessory support. 3.9.1 Audio accessory mode detection The STUSB4700 detects an audio accessory device when both the CC1 and CC2 pins are pulled down to ground by a Ra resistor from the connected device. The audio accessory detection is advertised through the CC_ATTACHED_MODE bits of the I2C register CC_CONNECTION_STATUS. 3.9.2 Debug accessory mode detection The STUSB4700 detects a connection to a debug and test system (DTS). The debug accessory detection is advertised through the CC_ATTACHED_MODE bits of the I2C register CC_CONNECTION_STATUS. The VBUS_EN_SRC pin is also asserted to allow the VBUS power path to be enabled as defined in the USB Type-C standard specification. A debug accessory device is detected when both the CC1 and CC2 pins are pulled down to ground by a Rd resistor from the connected device. The orientation detection is performed in two steps as described in the table below. The A_B_SIDE pin indicates the orientation of the connection. The orientation detection is advertised through the TYPEC_FSM_STATE bits of the I2C register CC_OPERATION_STATUS. DS11977 - Rev 7 page 11/41 STUSB4700 Accessory mode detection Table 9. The orientation detection # DS11977 - Rev 7 CC1 pin CC2 pin (CC2 pin) (CC1 pin) A_B_SIDE pin Detection process CC1/CC2 (CC2/CC1) Orientation detection state TYPEC_FSM_STATE bit value 1 Rd Rd 1st step: debug accessory mode detected HiZ (HiZ) UnorientedDebugAccessory.SRC 2 Rd ≤ Ra 2nd step: orientation detected (DTS presents a resistance to GND with a value ≤ Ra on its CC2 pin) HiZ (0) OrientedDebugAccessory.SRC page 12/41 STUSB4700 User-defined start-up configuration 4 User-defined start-up configuration 4.1 Parameter overview The STUSB4700 has a set of user-defined parameters that can be customized by NVM re-programming and/or by software through I2C interface. It allows changing the preset configuration of USB Type-C and PD interface and to define a new configuration to meet specific customer requirements addressing various applications, use cases or specific implementations. The NVM re-programming overrides the initial default setting to define a new default setting that will be used at power-up or after a reset. The default value is copied at power-up, or after a reset, from the embedded NVM into dedicated I2C register bits. The NVM re-programming is possible few times with a customer password. Table 10. PDO configurations in NVM Feature PDO1 PDO2 PDO3 PDO4 PDO5 Parameter Value Voltage 5V Current Configurable – defined by PDO1_I [3:0] Voltage Configurable – defined by PDO2_V [1:0] Current Configurable – defined by PDO2_I [3:0] Voltage Configurable – defined by PDO3_V [1:0] Current Configurable – defined by PDO3_I [3:0] Voltage Configurable – defined by PDO4_V [1:0] Current Configurable – defined by PDO4_I [3:0] Voltage Configurable – defined by PDO5_V [1:0] Current Configurable – defined by PDO5_I [3:0] When a default value is changed during system boot by software, the new settings apply as long as the STUSB4700 operates and until it is changed again. But after power-off and power-up, or after a hardware reset, the STUSB4700 takes back default values defined in the NVM. DS11977 - Rev 7 page 13/41 STUSB4700 PDO – voltage configuration in NVM 4.2 PDO – voltage configuration in NVM PDO2_V [1:0], PDO3_V [1:0], PDO4_V [1:0] and PDO5_V [1:0] can be configured with the following values: Table 11. PDO NVM voltage configuration Value Configuration 2b00 9V 2b01 15 V 2b10 PDO_FLEX_V1 2b11 PDO_FLEX_V2 PDO_FLEX_V1 and PDO_FLEX_V2 are defined in a specific 10-bit register, value is being expressed in 50 mV units. For instance: • • 4.3 PDO_FLEX_V1 = 10b0100100010 → 14.5 V PDO_FLEX_V2 = 10b0110000110 → 19.5 V PDO – current configuration in NVM PDO1_I [3:0], PDO2_I [3:0], PDO3_I [3:0], PDO4_I [3:0] and PDO5_I [3:0] can be configured with the following fixed values: Table 12. PDO NVM current configuration Value Configuration 4b0000 PDO_FLEX_I 4b0001 1.50 A 4b0010 1.75 A 4b0011 2.00 A 4b0100 2.25 A 4b0101 2.50 A 4b0110 2.75 A 4b0111 3.00 A 4b1000 3.25 A 4b1001 3.50 A 4b1010 3.75 A 4b1011 4.00 A 4b1100 4.25 A 4b1101 4.50 A 4b1110 4.75 A 4b1111 5.00 A PDO_FLEX_I is defined in a specific 10-bit register, value is being expressed in 10 mA units. For instance: • 4.4 Monitoring configuration in NVM • DS11977 - Rev 7 PDO_FLEX_I = 10b0011100001 → 2.25 A T_Transition_To_PDO (TDISUSBPDO) can be configured from 20 to 300 ms by increments of 20 ms (0 is not recommended) page 14/41 STUSB4700 Factory settings • 4.5 • T_Transition_To_0V (TDISUSB0V) can be configured from 84 to 1260 ms by increments of 84 ms (0 is not recommended) V_Shift_High (VSHUSBH) can be configured from 1% to 15% of VBUS by step of 1% • V_Shift_Low (VSHUSBL) can be configured from 1% to 15% of VBUS by step of 1% Factory settings Table 13. Factory NVM setting DS11977 - Rev 7 Parameter STUSB4700QTR STUSB4700YQTR Number of PDO 5 3 PDO1 (UVLO; OVLO) 5 V / 3 A (-10%; +12%) 5 V / 3 A (-10%; +12%) PDO2 9 V / 3 A (-10%; +10%) 9 V / 3 A (-10%; +10%) PDO3 12 V / 3 A (-10%; +10%) 12 V / 3 A (-10%; +10%) PDO4 15 V / 3 A (-10%; +10%) - PDO5 20 V / 2.25 A (-10%; +8%) - GPIO0 Sel_PDO2 Sel_PDO2 GPIO1 Sel_PDO3 Sel_PDO3 GPIO2 Sel_PDO4 Sel_PDO2 GPIO3 Sel_PDO5 Sel_PDO3 GPIO4 V_TRANS_UP VBUS_EN_SRC_N Discharge time: transition to PDO 240 ms 240 ms Discharge time: transition to 0 V 168 ms 168 ms page 15/41 STUSB4700 I²C interface 5 I²C interface 5.1 Read and write operations The I²C interface is used to configure, control and read the status of the device. It is compatible with the Philips I²C Bus® (version 2.1). The I²C is a slave serial interface based on two signals: • • SCL - serial clock line: input clock used to shift data SDA - serial data line: input/output bidirectional data transfers A filter rejects the potential spikes on the bus data line to preserve data integrity. The bidirectional data line supports transfers up to 400 Kbit/s (fast mode). The data are shifted to and from the chip on the SDA line, MSB first. The first bit must be high (START) followed by the 7-bit device address and the read/write control bit. Eigth 7-bit device addresses are available for the STUSB4700 thanks to the external programming of DevADDR0, DevADDR11 and/or DevADDR2 through VVAR_ADDR0, ADDR1 and ADDR2 pins respectively. It allows eight STUSB4700 devices to be connected on the same I2C bus. Two addresses are available by default, i.e. 0x28 or 0x29, depending on the setting of the VVAR_ADDR0 pin (ADDR1 and ADDR2 set to 0 by default). Table 14. Device address format Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 DevADDR6 DevADDR5 DevADDR4 DevADDR3 DevADDR2 DevADDR1 DevADDR0 R/W 0 1 0 1 ADDR2 ADDR1 ADDR0 0/1 Table 15. Register address format Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 RegADDR7 RegADDR6 RegADDR5 RegADDR4 RegADDR3 RegADDR2 RegADDR1 RegADDR0 Table 16. Register data format Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 DATA7 DATA6 DATA5 DATA4 DATA3 DATA2 DATA1 DATA0 Figure 3. Read operation DS11977 - Rev 7 page 16/41 STUSB4700 Timing specifications Figure 4. Write operation 5.2 Timing specifications The device uses a standard slave I²C channel at speed up to 400 kHz. Table 17. I2C timing parameters - VDD = 5 V DS11977 - Rev 7 Symbol Parameter Min. Typ. Max. Unit Fscl SCL clock frequency 0 - 400 kHz thd,sta Hold time (repeated) START condition 0.6 - - µs tlow LOW period of the SCL clock 1.3 - - µs thigh HIGH period of the SCL clock 0.6 - - µs tsu,dat Setup time for repeated START condition 0.6 - - µs thd,dat Data hold time 0.04 - 0.9 µs tsu,dat Data setup time 100 - - µs tr Rise time of both SDA and SCL signals 20 + 0.1 Cb - 300 ns tf Fall time of both SDA and SCL signals 20 + 0.1 Cb - 300 ns tsu,sto Setup time for STOP condition 0.6 - - µs tbuf Bus free time between a STOP and START condition 1.3 - - µs Cb Capacitive load for each bus line - - 400 pF page 17/41 STUSB4700 Timing specifications Figure 5. I²C timing diagram DS11977 - Rev 7 page 18/41 STUSB4700 I²C register map 6 I²C register map Table 18. Register access legend Access code Expanded name Description RO Read only Register can be read only R/W Read/write Register can be read or written RC Read and clear Register can be read and is cleared after it is read Table 19. STUSB4700 register map overview Address Register name Access 00h to 0Ah Reserved RO Do not use 0Bh ALERT_STATUS RC Alert register linked to transition registers 0Ch ALERT_STATUS_MASK_CTRL R/W Allows the interrupt mask on the ALERT_STATUS register to be changed 0Dh CC_CONNECTION_STATUS_TRANS RC Alerts about transition in CC_CONNECTION_STATUS register 0Eh CC_CONNECTION_STATUS RO Gives status on CC connection 0Fh MONITORING_STATUS_TRANS RC Alerts about transition in MONITORING_STATUS register 10h MONITORING_STATUS RO Gives status on VBUS voltage monitoring 11h CC_CONNECTION_STATUS RO Gives status on CC connection 12h HW_FAULT_STATUS_TRANS RC Alerts about transition in HW_FAULT_STATUS register 13h HW_FAULT_STATUS RO Gives status on hardware faults 14h to 17h Reserved RO Do not use 18h CC_CAPABILITY_CTRL R/W Allows CC capabilities to be changed 19h to 22h Reserved RO Do not use 23h RESET_CTRL R/W Controls the device reset by software 24h Reserved RO Do not use 25h VBUS_DISCHARGE_TIME_CTRL R/W Allows the VBUS discharge time parameters to be changed 26h VBUS_DISCHARGE_STATUS RO Gives status on VBUS discharge path activation 27h VBUS_ENABLE_STATUS RO Gives status on VBUS power path activation 28h to 2Dh Reserved RO Do not use 2Eh VBUS_MONITORING_CTRL R/W Allows the monitoring conditions of VBUS voltage to be changed 2Fh to 70h Reserved RO Do not use 71h to 74h SRC_PDO1 R/W PDO1 capabilities configuration 75h to 78h SRC_PDO2 R/W PDO2 capabilities configuration 79h to 7Ch SRC_PDO3 R/W PDO3 capabilities configuration 7Dh to 80h SRC_PDO4 R/W PDO4 capabilities configuration 81h to 84h SRC_PDO5 R/W PDO5 capabilities configuration 85h to 90h Reserved RO Do not use 91h to 94h SRC_RDO RO PDO request status DS11977 - Rev 7 Description page 19/41 STUSB4700 I²C register map Table 20. Register access legend Access code Expanded name RO Read only R/W Read / Write RC Read and clear DS11977 - Rev 7 Description Register can be read only Register can be read or written Register can be read and is cleared after read page 20/41 STUSB4700 Typical use cases 7 Typical use cases 7.1 Power supply – buck topology Figure 6. Power supply - buck topology Power Control C21 100nF T2 STL6P3LLH6 HC C24 100pF + R9 10k R8 820 T3 STL6P3LLH6 Vbus 1µF A1 A2 A3 A4 A5 TC-DP A6 TC-DM A7 A8 A9 A10 A11 A12 R11 2k2 C2 1µF GND 16 GPIO4 15 GPIO3 R3 4k7 14 GPIO2 11 GPIO1 12 GPIO0 R4 4k87 R5 8k66 R6 33k 9 ALERT# SCL 7 SCL SDA 8 SDA 6 Reset 13 Addr0 R7 100k GND 23 21 22 24 VDD R2 13k GND VSYS Vsrc 1µF C1 GND R1 200k FB C3 VCONN 3 GND VReg_2V7 Power plane GND J1 C4 10µF R10 10k Small signal VReg_1V2 FB 220 µF 2 4 T1 STR2P3LLH6 Vsrc 68µH 10 µF FB L21 C35 PG SW 8 C25 220nF EN2 /EN1 SW D21 STPS5L25B C23 5 3 Vin GND C22 10 µF C32 10µF 7 6 Vin Boot 1 U2 ST1S14PHR U1 STUSB4700 B12 B11 B10 B9 Vbus Vbus B8 CC1 Sbu2 B7 TC-DM D+1 D-2 B6 TC-DP D-1 D+2 B5 Sbu1 CC2 B4 Vbus USB 3.1 Vbus TYPE C Tx-2 B3 Rx-2 B2 Tx+2 Rx+2 B1 GND GND GND GND Tx+1 Rx+1 Tx-1 Rx-1 VBus_DISCH 19 VBus_EN_SRC 20 VBus_Sense 18 GND A_B_Side 17 Autonomous USB PD controller with integrated discharge path TC-DM CC1GND 1 R12 TC-DP 100 CC1 2 CC1 CC2 4 CC2 CC2GND 5 GND GND ExpPAD 10 0 GND GND GND The STUSB4700 offers the possibility to have up to 5 PDOs. Vsrc Figure 7. Power supply - buck topology extract FB R1 200k 16 R2 13k 15 14 R3 4k7 11 12 R4 4k87 9 SCL R5 8k66 R6 33k GND SDA 7 8 6 R7 100k 13 GPIO4 GPIO3 GPIO2 GPIO1 GPIO0 ALERT# SCL SDA Reset Addr0 GND In the above example, the Vsafe5V is generated by R1 and the full ladder R2+R3+R4+R5+R6. When a power delivery negotiation results in a PD contract that is not 5 V (PDO2, PDO3, PDO4 and PDO5), GPIO0, GPIO1, GPIO2 and GPIO3 are asserted (active low), respectively. This shorts R6, R5, R4 and R3 according to the following table. DS11977 - Rev 7 page 21/41 STUSB4700 Power supply – flyback topology Table 21. Resistor value VOUT PDO 5 20 4 15 3 12 2 9 1 5 Calculation Resistor value (ohm) R1 200 k R2 = R1 ∙ V 1.22 OUT − 1.22 13 k R3 = R1 ∙ V 1.22 − R2 OUT − 1.22 4.7 k R4 = R1 ∙ V 1.22 − R2 − R3 OUT − 1.22 4.87 k R5 = R1 ∙ V 1.22 − R2 − R3 − R4 OUT − 1.22 8.66 k R6 = R1 ∙ V 1.22 − R2 − R3 − R4 − R5 OUT − 1.22 33 k To implement a different VBUS output voltage for every PDO, the Resistor matrix needs to be calculated using the following formula: R VBUS = 1.22  ∙ R +  R +  R1 +  R +  R 2 3 4 5 6 7.2 (1) Power supply – flyback topology Figure 8. Flyback topology J1 R24 0.15 C24 1.5nF T1 STS5P3LLH6 D21 5 Tr20 C25 1000pF R25 R26 22k 360k VDD T21 BC847C R30 + C26 22 µF R27 D23 D24 20k 15V R28 4.7 BAV103 + C27 22 µF 1k R29 U22A SFH617A-2 12k R31 1k C29 220pF U22B SFH617A-2 C3 µF 1 C1 µF 1 C2 µF 1 R1 100k 23 21 C28 33nF D25 TLVH431AIL3T R32 30k R9 10k 16 GPIO4 15 GPIO3 R3 8k87 14 GPIO2 11 GPIO1 R4 2k49 R5 4k42 R6 16k2 6 Reset 13 Addr0 R7 100k VBus_DISCH 19 VBus_EN_SRC 20 VBus_Sense 18 A_B_Side 17 CC1GND 1 CC1 2 CC1 4 CC2 CC2 Autonomous USB PD CC2GND 5 controller with Integrated discharge path GND 10 Vbus + C4 10 µF A1 GND B12 GND A2 Tx+1 B11 Rx+1 A3 Tx-1 Rx-1 B10 A4 Vbus B9 Vbus Vbus A5 CC1 B8 Sbu2 A6 D+1 B7 D -2 A7 D-1 B6 D+2 A8 Sbu1 B5 CC2 Vbus A9 Vbus B4 Vbus Vbus A10 Rx-2 USB 3.1Tx-2 B3 A11 Rx+2 TYPE CTx+2 B2 A12 GND B1 GND U1 STUSB4700 22 24 12 GPIO0 9 ALERT# SCL 7 SCL SDA 8 SDA R10 10k R11 2k2 Vbus_DISCH D22 1N4148WS R8 1k5 + C23 680 µF Vbus_EN_SRC 4.7 B 4 R22 33 VDD R23 STTH1R06A T2 STS10P3LLH6 A 1 8 sense 1 STCH02 VDD GD 7 current control 5 2 NC HV GND ZCD + - 3 FB 2.5V 6 U21 2 R21 220 D20 100nF 4 C21 2.2nF R20 100k C22 VSYS VDD VCONN 3 68µF VReg_1V2 + C20 VReg_2V7 - U20 STF10LN80K5 + ~ T20 ~ 3 ExpPAD 0 GND DS11977 - Rev 7 page 22/41 STUSB4700 Power supply – flyback topology In the above example, only 4 power profiles are used: 5 V, 9 V, 12 V and 15 V. Figure 9. Flyback topology extract R27 1k U22A SFH617A-2 R31 C28 1k 33nF R29 12k R1 100k 16 D25 TLVH431AIL3T R3 8k87 15 R4 2k49 11 R5 4k42 9 R6 16k2 14 12 SCL 7 SDA 8 6 13 GPIO4 GPIO3 GPIO2 GPIO1 GPIO0 ALERT# SCL SDA Reset Addr0 R7 100k The Vsafe5V is generated by R1 and the full ladder R3+R4+R5+ R6.When a power delivery negotiation results in a PD contract that is not 5 V (PDO2, PDO3, PDO4), GPIO0, GPIO1 and GPIO2 are asserted (active low), respectively. This shorts R6, R5, R4 according to the following table. Table 22. Resistor value PDO VOUT Calculation R1 4 15 3 12 2 9 1 5 R3 = R1 ∙ V 1.24 OUT − 1.24 R4 = R1 ∙ V 1.24 − R3 OUT − 1.24 R5 = R1 ∙ V 1.24 − R3 − R4 OUT − 1.24 R6 = R1 ∙ V 1.24 − R3 − R4 − R5 OUT − 1.24 Resistor value (Ω) 100 k 8.87 k 2.49 k 4.42 k 16.2 k To implement a different VBUS output voltage for every PDO, the Resistor matrix needs to be calculated using the following formula: R VBUS = 1.24  ∙ R +  R +1 R +  R 3 4 5 6 DS11977 - Rev 7 (2) page 23/41 STUSB4700 Electrical characteristics 8 Electrical characteristics 8.1 Absolute maximum ratings All voltages are referenced to GND. Table 23. Absolute maximum ratings Symbol Parameter Value Unit VDD Supply voltage on VDD pin 28 V VSYS Supply voltage on VSYS pin 6 V High voltage on CC pins 22 V High voltage on VBUS pins 28 V -0.3 to 6 V 6 V -55 to 150 °C 145 °C VCC1 VCC2 VVBUS_EN_SRC VVBUS_SENSE VSCL VSDA VALERT# VRESET Operating voltage on I/O pins VA_B_SIDE VGPIO[4 :0] VCONN TSTG TJ ESD DS11977 - Rev 7 VCONN voltage Storage temperature Maximum junction temperature HBM 4 CDM 1.5 kV page 24/41 STUSB4700 Operating conditions 8.2 Operating conditions Table 24. Operating conditions Symbol Parameter Value Unit VDD Supply voltage on VDD pin 4.1 to 22 V VSYS Supply voltage on VSYS pin 3.0 to 5.5 V CC pins (1) -0.3 to 5.5 V High voltage pins 0 to 22 V Operating voltage on I/O pins 0 to 4.5 V VCC1, VCC2 VVBUS_EN_SRC VVBUS_DISCH VVBUS_SENSE VSCL VSDA VALERT# VRESET VA_B_SIDE VGPIO[4 :4] VCONN VCONN voltage 2.7 to 5.5 V ICONN VCONN rated current (default = 0.35 A) 0.1 to 0.6 A Operating temperature -40 to 105 °C TA 1. Transient voltage on CC1 and CC2 pins are allowed to go down to -0.3 during BMC communication from connected devices. DS11977 - Rev 7 page 25/41 STUSB4700 Electrical and timing characteristics 8.3 Electrical and timing characteristics Unless otherwise specified: VDD = 5 V, TA = +25 °C, all voltages are referenced to GND. Table 25. Electrical characteristics Symbol Parameter Conditions Min. Typ. Max. Unit Device idle as source (not connected, no communication) IIDD(SRC) Current consumption VSYS @ 3.3 V – 158 – µA VDD @ 5.0 V – 188 – µA -20% 80 +20% µA -8% 180 +8% µA -8% 330 +8% µA CC1 and CC2 pins IP-USB IP-1.5 CC current sources CC pin voltage VCC = -0.3 to 2.6 V -40° < TA < +105° IP-3.0 VCCO CC open pin voltage CC unconnected, VDD=3.0 to 5.5 V 2.75 – – V RINCC CC input impedance Terminations off 200 – – kΩ VTH0.2 Detection threshold 1 Max. Ra detection by source at IP = IP -USB 0.15 0.2 0.25 V VTH0.4 Detection threshold 2 Max. Ra detection by source at IP = IP-1.5 0.35 0.4 0.45 V VTH0.8 Detection threshold 3 Max. Ra detection by source at IP = IP-3.0 0.75 0.8 0.85 V VTH1.6 Detection threshold 4 Max. Rd detection by source at IP = IP-USB and IP = IP-1.5 1.5 1.6 1.65 V 2.45 2.6 2.75 V 0.25 0.5 0.975 Ω 85 100 125 300 350 400 550 600 650 5.9 6 6.1 Low UVLO threshold 2.6 2.65 2.7 High UVLO threshold (default) 4.6 4.65 4.8 VTH2.6 Detection threshold 5 Max. Rd detection by source at IP-3.0, max. CC voltage for connected sink VCONN pin and power switches RVCONN IOCP VCONN power path resistance Overcurrent protection VOVP Overvoltage protection on CC output pins VUVP Undervoltage protection on VCONN input pin IVCONN = 0.2 A -40 °C < TA < +105 °C Programmable current limit threshold (from 100 mA to 600 mA by step of 50 mA) mA V V VDD pin monitoring VDDOVLO Overvoltage lockout OVLO threshold detection enabled, VDD pin supplied 5.8 6 6.2 V VDDUVLO Undervoltage lockout UVLO threshold detection enabled, VDD pin supplied 3.8 3.9 4.0 V DS11977 - Rev 7 page 26/41 STUSB4700 Electrical and timing characteristics Symbol Parameter Conditions Min. Typ. Max. Unit VBUS_SENSE pin monitoring and driving VTHUSB VBUS presence threshold (UVLO) VSYS=3.0 to 5.5 V 3.8 3.9 4 V VTH0V VBUS safe 0V threshold (vSafe0V) VSYS=3.0 to 5.5 V 0.5 0.6 0.7 V RDISUSB VBUS discharge resistor 600 700 800 Ω TDISUSB0V VBUS discharge time to 0 V Coefficient TDISPAR0V programmable by NVM, default TDISPAR0V = 2, TDISUSB0V = 168 ms 70 *TDISPAR0V 84 *TDISPAR0V 100 *TDISPAR0V ms TDISUSBPDO VBUS transition discharge time to new PDO Coefficient TDISPARPDO programmable by NVM, default TDISPARPDO = 12, TDISUSBPDO = 288 ms 20 *TDISPARPDO 24 *TDISPARPDO 28 *TDISPARPDO ms – VBUS +5% +VSHUSBH – V – VBUS -5% -VSHUSBL – V 1.2 – – V – – 0.35 V Ioh = 3 mA – – 0.4 V Ioh = 3 mA – – 0.4 V Coefficient VSHUSBH programmable by NVM from 1% to 15% of VBUS by step of 1%, default VMONUSBH VBUS monitoring high voltage limit VMONUSBH = VBUS+12% (PDO1) VMONUSBH = VBUS+10% (PDO2, PDO3, PDO4) VMONUSBH = VBUS+8% (PDO5) VMONUSBL VBUS monitoring low voltage limit Coefficient VSHUSBL programmable by NVM from 1% to 15% of VBUS by step of 1%, default VMONUSBL = VBUS-10% (all PDOs) Digital input/output (SCL, SDA, ALERT#, A_B_SIDE, RESET) VIH High level input voltage VIL Low level input voltage VOL Low level output voltage 20 V open-drain outputs (VBUS_EN_SRC) VOL DS11977 - Rev 7 Low level output voltage page 27/41 STUSB4700 Package information 9 Package information In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com. ECOPACK is an ST trademark. DS11977 - Rev 7 page 28/41 STUSB4700 QFN24 EP 4x4 mm package information 9.1 QFN24 EP 4x4 mm package information Figure 10. QFN24 EP 4x4 mm package outline DS11977 - Rev 7 page 29/41 STUSB4700 QFN24 EP 4x4 mm package information Table 26. QFN24 EP 4x4 mm package mechanical data mm Symbol Min. Typ. Max. A 0.80 0.90 1.00 A1 0.00 0.02 0.05 A3 0.20 Ref. b 0.18 0.25 0.30 D 3.90 4.00 4.10 D2 2.55 2.70 2.80 E 3.90 4.00 4.10 E2 2.55 2.70 2.80 e 0.50 k 0.20 - - L 0.30 0.40 0.50 Table 27. Tolerance of form and position Symbol mm aaa 0.05 bbb 0.10 ccc 0.10 ddd 0.05 eee 0.08 Figure 11. QFN24 EP 4x4 mm recommended footprint DS11977 - Rev 7 page 30/41 STUSB4700 QFN24 EP 4x4 mm wettable flank package information 9.2 QFN24 EP 4x4 mm wettable flank package information Figure 12. QFN24 EP 4x4 mm wettable flank package outline Table 28. QFN24 EP 4x4 mm wettable flank mechanical data Symbol mm Min. Typ. Max. A 0.80 0.85 090 A1 0.00 0.05 A2 0.65 A3 0.203 REF B 0.20 0.25 0.30 D 3.90 4.00 4.10 E 3.90 4.00 4.10 D2 2.40 2.50 2.60 E2 2.40 2.50 2.60 e L DS11977 - Rev 7 0.50 BSC 0.30 0.40 0.50 page 31/41 STUSB4700 Packing information 9.3 Packing information Figure 13. Reel information Table 29. Tape dimensions DS11977 - Rev 7 Package Pitch Carrier width Reel QFN 4x4 - 24L 8 mm 12 mm 13" page 32/41 STUSB4700 Thermal information 10 Thermal information Table 30. Thermal information Symbol Parameter Value RθJA Junction-to-ambient thermal resistance 37 RθJC Junction-to-case thermal resistance 5 DS11977 - Rev 7 Unit °C/W page 33/41 STUSB4700 Terms and abbreviations 11 Terms and abbreviations Table 31. List of terms and abbreviations Term Accessory modes Audio adapter accessory mode. It is defined by the presence of Ra/Ra on the CC1/CC2 pins. Debug accessory mode. It is defined by the presence of Rd/Rd on CC1/CC2 pins in source power role or Rp/Rp on CC1/CC2 pins in sink power role. DFP Downstream facing port, associated with the flow of data in a USB connection. Typically, the ports on a host or the ports on a hub to which devices are connected. In its initial state, the DFP sources VBUS and VCONN and supports data. DRP Dual-role port. A port that can operate as either a source or a sink. The port role may be changed dynamically. Sink Port asserting Rd on the CC pins and consuming power from the VBUS; most commonly a device. Source Port asserting Rp on the CC pins and providing power over the VBUS; usually a host or hub DFP. UFP DS11977 - Rev 7 Description Upstream facing port, specifically associated with the flow of data in a USB connection. The port on a device or a hub that connects to a host or the DFP of a hub. In its initial state, the UFP sinks the VBUS and supports data. page 34/41 STUSB4700 Ordering information 12 Ordering information Table 32. Ordering information DS11977 - Rev 7 Order code AEC-Q100 Package Marking STUSB4700QTR No QFN24 EP 4x4 mm 4700 STUSB4700YQTR Yes QFN24 EP 4x4 mm Wettable flanks 4700Y Temperature range -40 °C to 105 °C page 35/41 STUSB4700 Revision history Table 33. Document revision history Date Version 24-Jan-2017 1 Initial release. 2 Updated comments columns in Table 7: "GPIO1 (pin #11) configuration" and Table 8: "GPIO2 (pin #14) – GPIO3 (pin #15) – GPIO4 (pin #16) configuration", and ESD parameter description in Table 18: "Absolute maximum rating". 22-Mar-2017 Changes In Table 19: "Operating conditions " replaced VVBUS_EN_SNK with VVBUS_DISCH. Replaced Figure 6: "Power supply - buck topology" with a new figure. Minor changes throughout the document. On cover page: - updated title description - updated feature regarding protections - added feature regarding Automotive grade availability 06-Dec-2017 3 - updated feature regarding Certification test ID - updated Table 1: "Device summary table" Updated Section 7.1 Power supply – buck topology Updated Section 7.2 Power supply – flyback topology Added Section 9.2 QFN24 EP 4x4 mm wettable flank package information DS11977 - Rev 7 12-Jun-2018 4 Minor text changes 16-Oct-2019 5 06-Apr-2021 6 Updated Section 9.1 QFN24 EP 4x4 mm package information. 11-Nov-2022 7 Updated Section 9.2 QFN24 EP 4x4 mm wettable flank package information Updated Table 13. Factory NVM setting. Updated Figure 6. Power supply - buck topology and Figure 8. Flyback topology. page 36/41 STUSB4700 Contents Contents 1 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 2 Inputs/outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 3 2.1 Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2.2 Pin list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2.3 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2.3.1 CC1 / CC2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2.3.2 RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2.3.3 I²C interface pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2.3.4 A_B_SIDE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2.3.5 VBUS_SENSE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2.3.6 VBUS_EN_SRC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2.3.7 VSYS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2.3.8 VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.3.9 GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.3.10 VVAR_ADDR0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.3.11 VREG_2V7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.3.12 VREG_1V2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.3.13 VBUS_DISCH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.3.14 VCONN. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.3.15 GPIO [4:0]. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Block descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3.1 CC interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3.2 BMC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3.3 Protocol layer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3.4 Policy engine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3.5 Device policy manager . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3.6 VBUS power path control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3.6.1 VBUS monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3.6.2 VBUS discharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3.6.3 VBUS power path assertion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3.7 High voltage protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3.8 Hardware fault management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3.9 Accessory mode detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 DS11977 - Rev 7 3.9.1 Audio accessory mode detection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3.9.2 Debug accessory mode detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 page 37/41 STUSB4700 Contents 4 5 User-defined start-up configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 4.1 Parameter overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 4.2 PDO – voltage configuration in NVM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4.3 PDO – current configuration in NVM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4.4 Monitoring configuration in NVM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4.5 Factory settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 I²C interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 5.1 Read and write operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 5.2 Timing specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 6 I²C register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 7 Typical use cases. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 8 9 7.1 Power supply – buck topology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 7.2 Power supply – flyback topology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 8.1 Absolute maximum ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 8.2 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 8.3 Electrical and timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Package information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 9.1 QFN24 EP 4x4 mm package information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 9.2 QFN24 EP 4x4 mm wettable flank package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 9.3 Packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 10 Thermal information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 11 Terms and abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 12 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 DS11977 - Rev 7 page 38/41 STUSB4700 List of tables List of tables Table 1. Table 2. Pin function list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Legend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. I2C interface pin list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . USB data mux select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GPIO0 (pin #12) configuration . . . . . . . . . . . . . . . . . . . . . . . . . . GPIO1 (pin #11) configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . GPIO2 (pin #14) – GPIO3 (pin #15) – GPIO4 (pin #16) configuration Conditions for VBUS power path assertion . . . . . . . . . . . . . . . . . . The orientation detection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PDO configurations in NVM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . PDO NVM voltage configuration . . . . . . . . . . . . . . . . . . . . . . . . . PDO NVM current configuration . . . . . . . . . . . . . . . . . . . . . . . . . . Factory NVM setting. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Device address format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Register address format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Register data format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 . 6 . 8 . 8 . 8 10 12 13 14 14 15 16 16 16 Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Table 24. Table 25. Table 26. Table 27. Table 28. Table 29. Table 30. Table 31. Table 32. Table 33. I2C timing parameters - VDD = 5 V. . . . . . . . . . . . Register access legend . . . . . . . . . . . . . . . . . . . STUSB4700 register map overview . . . . . . . . . . . Register access legend . . . . . . . . . . . . . . . . . . . Resistor value . . . . . . . . . . . . . . . . . . . . . . . . . . Resistor value . . . . . . . . . . . . . . . . . . . . . . . . . . Absolute maximum ratings . . . . . . . . . . . . . . . Operating conditions . . . . . . . . . . . . . . . . . . . . . Electrical characteristics . . . . . . . . . . . . . . . . . . . QFN24 EP 4x4 mm package mechanical data . . . . Tolerance of form and position . . . . . . . . . . . . . . . QFN24 EP 4x4 mm wettable flank mechanical data Tape dimensions . . . . . . . . . . . . . . . . . . . . . . . . Thermal information . . . . . . . . . . . . . . . . . . . . . . List of terms and abbreviations . . . . . . . . . . . . . . Ordering information. . . . . . . . . . . . . . . . . . . . . . Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 19 19 20 22 23 24 25 26 30 30 31 32 33 34 35 36 DS11977 - Rev 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . page 39/41 STUSB4700 List of figures List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. DS11977 - Rev 7 Functional block diagram . . . . . . . . . . . . . . . . . . Pin connections (top view) . . . . . . . . . . . . . . . . . Read operation. . . . . . . . . . . . . . . . . . . . . . . . . Write operation . . . . . . . . . . . . . . . . . . . . . . . . . I²C timing diagram. . . . . . . . . . . . . . . . . . . . . . . Power supply - buck topology . . . . . . . . . . . . . . . Power supply - buck topology extract. . . . . . . . . . Flyback topology. . . . . . . . . . . . . . . . . . . . . . . . Flyback topology extract . . . . . . . . . . . . . . . . . . QFN24 EP 4x4 mm package outline . . . . . . . . . . QFN24 EP 4x4 mm recommended footprint . . . . . QFN24 EP 4x4 mm wettable flank package outline Reel information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 . 3 16 17 18 21 21 22 23 29 30 31 32 page 40/41 STUSB4700 IMPORTANT NOTICE – READ CAREFULLY STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgment. Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of purchasers’ products. No license, express or implied, to any intellectual property right is granted by ST herein. Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. ST and the ST logo are trademarks of ST. For additional information about ST trademarks, refer to www.st.com/trademarks. All other product or service names are the property of their respective owners. Information in this document supersedes and replaces information previously supplied in any prior versions of this document. © 2022 STMicroelectronics – All rights reserved DS11977 - Rev 7 page 41/41