STUSB4710
Stand-alone USB PD controller (with short-to-VBUS protection)
Features
Product status link
STUSB4710
•
•
•
•
USB power delivery (PD) controller
Type-C attach and cable orientation detection
Single role: provider
Full hardware solution - no software
•
•
•
•
I2C interface (optional connection to MCU)
Support all USB PD profiles: up to 5 power data objects (PDO)
Configurable start-up profiles
Integrated VBUS voltage monitoring
•
Internal and/or external VBUS discharge path
•
Short -to-VBUS protections on CC pins (22 V) and VBUS pins (28 V)
•
Wide power supply input:
–
VDD = [4.1 V; 22 V]
•
•
Temperature range: -40 °C up to 105 °C
Fully compatible with:
–
USB Type-C™ rev 1.2
–
USB PD rev 2.0
Certification test ID: 1000125 (QFN24)
•
Applications
•
•
•
•
•
AC adapters and power supplies for: computer, consumer or portable
consumer applications
Smart plugs and wall adapters
Power hubs and docking stations
Displays
Any Type-C source device
Description
The STUSB4710 is a new family of USB power delivery controllers communicating
over Type-C™ configuration channel pins (CC) to negotiate a given amount of power
to be sourced to an inquiring consumer device.
The STUSB4710 addresses provider/DFP devices such as notebooks, tablets and
AC adapters. The device can handle any connections to a UFP or DRP without any
MCU attachment support, from the device attachment to power negotiation, including
VBUS discharge and protections.
DS12090 - Rev 8 - December 2022
For further information contact your local STMicroelectronics sales office.
www.st.com
STUSB4710
Functional description
1
Functional description
The STUSB4710 is an autonomous USB power delivery controller optimized as a provider. It offers an open-drain
GPIO interface to make direct interconnection with a power regulation stage.
The STUSB4710 offers the benefits of a full hardware USB PD stack allowing robust and safe USB PD
negotiation in line with USB PD standard. The STUSB4710 is ideal for provider applications in which digital
or software intelligence is limited or missing.
The STUSB4710 main functions are:
•
•
•
Detect the connection between two USB ports (attach detection)
Establish a valid host to the device connection
Discover and configure VBUS: Type-C low, medium or high current mode
•
•
•
•
Resolve cable orientation
Negotiate a USB power delivery contract with a PD capable device
Configure the power source accordingly
Monitor VBUS, manage transitions, handle protections and ensure user and device safety
Additionally, the STUSB4710 offers 5 customizable power data objects (PDOs), 5 general purpose I/Os, an
integrated discharge path, and is natively robust to high voltage peaks.
Figure 1. Functional block diagram
VDD
VREG_2V7
Internal
supply
VBUS status
voltage
monitoring
VREG_1V2
VBUS_SENSE
Discharge
path
VBUS_EN_SRC
VBUS_DISCH
SCL
SDA
Port C
controller
I²C
slave
CC
line
access
port status
ADDR0
CC1
CC2
Control
SEL_PDO[5..2]
POR &
reset
generator
Policy
Engine
Protocol
Layer
Physical
Layer
BMC
driver
GND
DS12090 - Rev 8
page 2/31
STUSB4710
Inputs/outputs
2
Inputs/outputs
2.1
Pinout
Figure 2. STUSB4710AQTR pin connections (top view)
VREG_1V2
VBUS_EN_SRC
VBUS_DISCH
NC
NC
CC1
24
VREG_2V7
VDD
NC
23
22
21
20
19
1
18
2
17
3
EP
NC
15
SEL_PDO5
14
SEL_PDO4
4
NC
5
6
13
10
11
ADDR0
12
SEL_PDO2
SEL_PDO3
GND
9
NC
SCL
8
SDA
7
NC
16
CC2
NC
VBUS_SENSE
Figure 3. STUSB4710AQ1TR pin connections (top view)
VREG_2V7
VREG_1V2
VBUS_EN_SRC
VBUS_DISCH
15
14
13
VDD
1
12
VBUS_SENSE
CC1
2
11
SEL_PDO5
CC2
3
10
SEL_PDO4
SCL
4
9
5
6
7
8
SDA
GND
SEL_PDO3
SEL_PDO2
DS12090 - Rev 8
16
ADDR0
page 3/31
STUSB4710
Pin list
2.2
Pin list
Table 1. Pin function list
Name
Type
Description
CC1
20 V analog IO
Configuration channel 1
Type-C receptacle A5
CC2
20 V analog IO
Configuration channel 2
Type-C receptacle B5
SCL
DI
I²C clock
Connection
To I²C master – ext. pull-up
I2C
SDA
DI/OD
data input/output – active low opendrain
GND
Power
Ground
SEL_PDO3
OD
PD03 select flag
SEL_PDO2
OD
PD02 select flag
ADDR0
Analog
I2C address 0 bit
SEL_PDO4
OD
PD04 select flag
SEL_PDO5
OD
PD05 select flag
VBUS_SENSE
20 V AI
VBUS voltage monitoring and discharge
path
VBUS_DISCH
Output
External discharge control signal
VBUS_EN_SRC
20 V OD
VREG_1V2
Analog
1.2 V regulator output
1 µF typ. decoupling capacitor
VREG_2V7
Analog
2.7 V regulator output
1 µF typ. decoupling capacitor
VDD
20 V power
Main power supply (USB power line)
From VBUS (system side)
EP
Exposed pad
Exposed pad is connected to ground
To ground
VBUS source power path enable – active
low open-drain
To I²C master – ext. pull-up
From VBUS
To switch or power system – ext.
pull-up
Table 2. Legend
DS12090 - Rev 8
Type
Description
D
Digital
A
Analog
O
Output pad
I
Input pad
IO
Bidirectional pad
OD
Open drain output
PD
Pull-down
PU
Pull-up
PWR
Power supply
GND
Ground
page 4/31
STUSB4710
Pin description
2.3
Pin description
2.3.1
CC1 / CC2
CC1 and CC2 are the configuration channel pins used for connection and attachment detection, plug orientation
determination and system configuration management across USB Type-C cable. CC1/CC2 are HiZ during reset.
2.3.2
I²C interface pins
Table 3. I²C interface pin list
Name
2.3.3
Description
SCL
I²C clock – needs external pull-up
SDA
I²C data – needs external pull-up
VBUS_SENSE
This input pin is used to sense VBUS presence, monitor VBUS voltage and discharge VBUS on USB Type-C
receptacle side.
2.3.4
VBUS_EN_SRC
In source power role, this pin allows the outgoing VBUS power to be enabled when the connection to a sink is
established and VBUS is in the valid operating range. The open-drain output allows a PMOS transistor to be driven
directly. The logic value of the pin is also advertised in a dedicated I2C register bit.
2.3.5
VDD
VDD is the main power supply for applications powered by VBUS.
This pin can be used to sense the voltage level of the main power supply providing VBUS. It allows UVLO and
OVLO voltage thresholds to be considered independently on VDD pin as additional conditions to enable the VBUS
power path through VBUS_EN_SRC pin.
2.3.6
GND
Ground.
2.3.7
ADDR0
At start-up, this pin is latched to set I²C device address 0 bit.
2.3.8
VREG2V7
This pin is used for external decoupling of 2.7 V internal regulator only .
Recommended decoupling capacitor: 1 µF typ. (0.5 µF min.; 10 µF max.).
This pin must not be used to supply any external component.
2.3.9
VBUS_DISCH
Control signal for external VBUS_DISCH path.
2.3.10
SEL_PDO [5:2]
These 4 output signals are asserted (active low) respectively when PDO2, PDO3, PDO4 and PDO5 are selected
by the attached sink. These signals are used to pilot the power management unit.
DS12090 - Rev 8
page 5/31
STUSB4710
Block descriptions
3
Block descriptions
3.1
CC interface
The STUSB4710 controls the connection to the configuration channel (CC) pins, CC1 and CC2, through two main
blocks, the CC line interface block and the CC control logic block.
The CC lines interface block is used to:
•
•
•
Configure the termination mode on the CC pins relative to the power mode supported, i.e. pull-up for
source power role
Monitor the CC pin voltage values relative to the attachment detection thresholds
Protect the CC pins against over voltage
The CC control logic block is used to:
•
•
•
•
•
•
•
Execute the Type-C FSM relative to the Type-C power mode supported
Determine the electrical state for each CC pins relative to the detected thresholds
Evaluate the conditions relative to the CC pin states and VBUS voltage value to transition from one state to
another in the Type-C FSM
Detect and establish a valid source-to-sink connection
Determine the attached mode: source, accessory
Determine cable orientation to allow external routing of the USB super speed data
Manage VBUS power capability: USB default, Type-C medium or Type-C high current mode
•
Handle hardware faults
The CC control logic block implements the Type-C FSM’s corresponding to source power role with accessory
support.
3.2
BMC
This block is the physical link between USB PD protocol layer and CC pin. In TX mode, it converts the data into
bi-phase mark coding (BMC), and drives the CC line to correct voltages. In RX mode, it recovers BMC data from
the CC line, and converts to baseband signaling for the protocol layer.
3.3
Protocol layer
The protocol layer has the responsibility to manage the messages from/to the physical layer. It automatically
manages the protocol receive timeouts, the message counter, the retry counter and the GoodCRC messages.
It communicates with the internal policy engine.
3.4
Policy engine
The policy engine implements the power negotiation with the connected device according to its source role, it
implements the state machine that controls protocol layer forming and scheduling the messages.
The policy engine uses the protocol layer to send/receive messages.
The policy engine interprets the device policy manager’s input in order to implement policy for port and directs the
protocol layer to send appropriate messages.
3.5
Device policy manager
The device policy manager manages the power resources.
DS12090 - Rev 8
page 6/31
STUSB4710
VBUS power path control
3.6
VBUS power path control
3.6.1
VBUS monitoring
The VBUS monitoring block supervises (from the VBUS_SENSE input pin) the VBUS voltage on the USB Type-C
receptacle side.
This block is used to check that VBUS is within a valid voltage range:
•
•
To establish a valid source-to-sink connection according to USB Type-C standard specification
To enable safely the VBUS power path through VBUS_EN_SRC pin
It allows detection of unexpected VBUS voltage conditions such as undervoltage or overvoltage relative to the valid
VBUS voltage range. When such conditions occur, the STUSB4710 reacts as follows:
•
At attachment, it prevents the source-to-sink connection and the VBUS power path assertion
•
After attachment, it deactivates the source-to-sink connection and disables the VBUS power path. The
device goes into error recovery state.
The VBUS voltage value is automatically adjusted at attachment and at each PDO transition. The monitoring is
then disabled during T_PDO_transition (default 280 ms changed through NVM programming). Additionally, if a
transition occurs to a lower voltage, the discharge path is activated during this time.
The valid VBUS voltage range is defined from the VBUS nominal voltage by a high threshold voltage and a low
threshold voltage whose minimal values are respectively VBUS+5% and VBUS-5%. The nominal threshold limits
can be shifted by a fraction of VBUS from +1% to +15% for the high threshold voltage and from -1% to -15% for
the low threshold voltage. This means the threshold limits can vary from VBUS+5% to VBUS+20% for the high limit
and from VBUS-5% to VBUS-20% for the low limit.
The threshold limits are preset by default in the NVM with different shift coefficients (see Section 8.3 Electrical
and timing characteristics). The threshold limits can be changed independently through NVM programming
(see Section 8.3 Electrical and timing characteristics) and also by software during attachment through the I2C
interface (see Section 6 I²C register map).
3.6.2
VBUS discharge
The monitoring block handles also the internal VBUS discharge path connected to the VBUS_SENSE input pin.
The discharge path is activated at detachment, or when the device goes into the error recovery state (see
Section 3.8 Hardware fault management).
The VBUS discharge path is enabled by default in the NVM and can be disabled through NVM programming only
(see Section 4 User-defined startup configuration). Discharge time duration (T_PDO_transition and T_Transition
to 0 V) are also preset by default in the NVM (see Section 8.3 Electrical and timing characteristics). The
discharge time duration can be changed through NVM programming (see Section 4 User-defined startup
configuration) and also by software through the I2C interface (see Section 6 I²C register map).
DS12090 - Rev 8
page 7/31
STUSB4710
High voltage protection
3.6.3
VBUS power path assertion
The STUSB4710 can control the assertion of the VBUS power path on USB Type-C port, directly or indirectly,
through VBUS_EN_SRC pin.
The following table summarizes the configurations and the conditions that determine the logic value of
VBUS_EN_SRC pin during system operation.
Table 4. Conditions for VBUS power path assertion
Electrical
value
Pin
Operation conditions
Attached state
VDD monitoring
Attached.SRC
UnorientedDebug
VBUS_EN_SRC
0
Accessory.SRC
OrientedDebug
Accessory.SRC
VBUS monitoring
Comment
VBUS within valid voltage
range
VDD > UVLO if
VDD_UVLO enabled
and/or VDD < OVLO if
VDD_OVLO enabled
if VBUS _VALID_RANGE
enabled
or VBUS > UVLO if
The signal is asserted
only if all the valid
operation conditions
are met.
VBUS _VALID_RANGE
disabled
VBUS is out of valid voltage
range
HiZ
Any other state
VDD < UVLO if
VDD_UVLO enabled
and/or VDD > OVLO if
VDD_OVLO enabled
if
VBUS _VALID_RANGE
enabled
or VBUS < UVLO if
The signal is deasserted when at
least one non-valid
operation condition is
met.
VBUS _VALID_RANGE
disabled
Note:
Activation of the UVLO and OVLO threshold detections can be done through NVM programming (see
Section 4 User-defined startup configuration) and also by software through the I2C interface (see Section 6 I²C
register map). When the UVLO and/or OVLO threshold detection is activated, the VBUS_EN_SRC pin is
asserted only if the device is attached and the valid threshold conditions on VDD are met. Once the
VBUS_EN_SRC pin is asserted, the VBUS monitoring is done on VBUS_SENSE pin instead of the VDD pin.
3.7
High voltage protection
The STUSB4710 can be safely used in systems or connected to systems that handle high voltage on the VBUS
power path. The device integrates an internal circuitry on the CC pins that tolerates high voltage and ensures a
protection up to 22 V in case of unexpected short circuit with VBUS or in case of connection to a device supplying
high voltage on VBUS.
DS12090 - Rev 8
page 8/31
STUSB4710
Hardware fault management
3.8
Hardware fault management
The STUSB4710 handles hardware fault conditions related to the device itself and the VBUS power path during
system operation.
When such conditions occur, the circuit goes into a transient error recovery state named ErrorRecovery in
the Type-C FSM. When entering in this state, the device de-asserts the VBUS power path by disabling the
VBUS_EN_SRC pin, and it removes the terminations from the CC pins during several tens of milliseconds. Then,
it transitions to the unattached source state.
The STUSB4710 goes into error recovery state when at least one condition listed below is met:
•
•
•
•
If an overtemperature is detected, the “THERMAL_FAULT”flag is asserted.
If an internal pull-up voltage on CC pins is below UVLO threshold, the “VPU_VALID” flag is asserted.
If an overvoltage is detected on the CC pins, the “VPU_OVP_FAULT” flag is asserted.
If the VBUS voltage is out of the valid voltage range during attachment, the “VBUS_VALID” flag is asserted.
•
If an undervoltage is detected on the VDD pin during attachment when UVLO detection is enabled, the
“VDD_UVLO_DISABLE” flag is asserted.
If an overvoltage is detected on the VDD pin during attachment when OVLO detection is enabled, the
“VDD_OVLO_DISABLE” flag is asserted.
•
The I2C register bits mentioned above in quotes give either the state of the hardware fault when it occurs or the
setting condition to detect the hardware fault.
3.9
Accessory mode detection
The STUSB4710 supports the detection of audio accessory mode and debug accessory mode as defined in the
USB Type-C standard specification source power role with accessory support.
3.9.1
Audio accessory mode detection
The STUSB4710 detects an audio accessory device when both the CC1 and CC2 pins are pulled down to
ground by a Ra resistor from the connected device. The audio accessory detection is advertised through the
CC_ATTACHED_MODE bits of the I2C register CC_CONNECTION_STATUS.
3.9.2
Debug accessory mode detection
The STUSB4710 detects a connection to a debug and test system (DTS) when it operates either in sink power
role or source power role. The debug accessory detection is advertised by the DEBUG1 and DEBUG2 pins as
well as through the CC_ATTACHED_MODE bits of the I2C register CC_CONNECTION_STATUS.
In source power role, a debug accessory device is detected when both the CC1 and CC2 pins are pulled down
to ground by a Rd resistor from the connected device. The orientation detection is performed in two steps
as described in the table below. The DEBUG2 pin is asserted to advertise the DTS detection. The orientation
detection is advertised through the TYPEC_FSM_STATE bits of the I2C register CC_OPERATION_STATUS.
DS12090 - Rev 8
page 9/31
STUSB4710
User-defined startup configuration
4
User-defined startup configuration
4.1
Parameter overview
The STUSB4710 has a set of user-defined parameters that can be customized by NVM re-programming and/or
by software through I2C interface. It allows changing the preset configuration of USB Type-C and PD interface
and to define a new configuration to meet specific customer requirements addressing various applications, use
cases or specific implementations.
The NVM re-programming overrides the initial default setting to define a new default setting that is used at
power-up or after a reset. The default value is copied at power-up, or after a reset, from the embedded NVM into
dedicated I2C register bits. The NVM re-programming is possible few times with a customer password.
Table 5. PDO configurations in NVM
Feature
PDO1
PDO2
PDO3
PDO4
PDO5
Parameter
Value
Default
Voltage
5V
5V
Current
Configurable – defined by PDO1_I [3:0]
3A
Voltage
Configurable – defined by PDO2_V [1:0]
9V
Current
Configurable – defined by PDO2_I [3:0]
3A
Voltage
Configurable – defined by PDO3_V [1:0]
12 V
Current
Configurable – defined by PDO3_I [3:0]
3A
Voltage
Configurable – defined by PDO4_V [1:0]
15 V
Current
Configurable – defined by PDO4_I [3:0]
3A
Voltage
Configurable – defined by PDO5_V [1:0]
20 V
Current
Configurable – defined by PDO5_I [3:0]
2.25 A
When a default value is changed during system boot by software, the new settings apply as long as the
STUSB4710 is being run and until it is changed again. But after power-off and power-up, or after a hardware
reset, the STUSB4710 takes back default values defined in the NVM.
4.2
PDO – voltage configuration in NVM
PDO2_V [1:0], PDO3_V [1:0], PDO4_V [1:0] and PDO5_V [1:0] can be configured with the following values:
Table 6. PDO NVM voltage configuration
Value
Configuration
2b00
9V
2b01
15 V
2b10
PDO_FLEX_V1
2b11
PDO_FLEX_V2
PDO_FLEX_V1 and PDO_FLEX_V2 are defined in a specific 10-bit register, value being expressed in 50 mV
units.
For instance:
•
•
DS12090 - Rev 8
PDO_FLEX_V1 = 10b0100100010 → 14.5 V
PDO_FLEX_V2 = 10b0110000110 → 19.5 V
page 10/31
STUSB4710
PDO – current configuration in NVM
4.3
PDO – current configuration in NVM
PDO1_I [3:0], PDO2_I [3:0], PDO3_I [3:0], PDO4_I [3:0] and PDO5_I [3:0] can be configured with the following
fixed values:
Table 7. PDO NVM current configuration
Value
Configuration
4b0000
PDO_FLEX_I
4b0001
1.50 A
4b0010
1.75 A
4b0011
2.00 A
4b0100
2.25 A
4b0101
2.50 A
4b0110
2.75 A
4b0111
3.00 A
4b1000
3.25 A
4b1001
3.50 A
4b1010
3.75 A
4b1011
4.00 A
4b1100
4.25 A
4b1101
4.50 A
4b1110
4.75 A
4b1111
5.00 A
PDO_FLEX_I is defined in a specific 10-bit register, value being expressed in 10 mA units. For instance:
•
4.4
Monitoring configuration in NVM
•
•
•
•
4.5
PDO_FLEX_I = 10b0011100001 → 2.25 A
T_PDO_Transition can be configured from 20 to 300 ms by increments of 20 ms (0 is not recommended).
Default value is 240 ms.
T_Transition_to_0V can be configured from 84 to 1260 ms by increments of 84 ms (0 is not
recommended). Default value is 168 ms.
Vshift_High can be configured from (5 to 20%). Default value ranges from 8% to 12%.
Vshift _Low can be configured from (5 to 20%). Default value is 10% for all PDO.
Discharge configuration in NVM
Both internal and external discharge paths are enabled by default. VBUS_DISCH control pin is configured to drive
a PMOS by default (active low).
DS12090 - Rev 8
page 11/31
STUSB4710
I²C interface
5
I²C interface
5.1
Read and write operations
The I²C interface is used to configure, control and read the status of the device. It is compatible with the Philips
I²C Bus® (version 2.1). The I²C is a slave serial interface based on two signals:
•
•
SCL - serial clock line: input clock used to shift data
SDA - serial data line: input/output bidirectional data transfers
A filter rejects the potential spikes on the bus data line to preserve data integrity.
The bidirectional data line support transfers up to 400 Kbit/s (fast mode). The data are shifted to and from the chip
on the SDA line, MSB first.
The first bit must be high (START) followed by the 7-bit device address and the read/write control bit.
Two 7-bit device addresses are available for the STUSB4710 thanks to external programming of DevADDR0,
through ADDR0, pin setting. It allows two STUSB4710 devices to be connected on the same I2C bus.
ADDR is not available for all configurations.
The device address format:
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
DevADDR6
DevADDR5
DevADDR4
DevADDR3
DevADDR2
DevADDR1
DevADDR0
R/W
0
1
0
1
0
0
ADDR0
0/1
The register address format:
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
RegADDR7
RegADDR6
RegADDR5
RegADDR4
RegADDR3
RegADDR2
RegADDR1
RegADDR0
The register data format:
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
DATA7
DATA6
DATA5
DATA4
DATA3
DATA2
DATA1
DATA0
Figure 4. Read operation
DS12090 - Rev 8
page 12/31
STUSB4710
Timing specifications
Figure 5. Write operation
5.2
Timing specifications
The device uses a standard slave I²C channel at speed up to 400 kHz.
Table 8. I2C timing parameters - VDD = 5 V
DS12090 - Rev 8
Symbol
Parameter
Min.
Typ.
Max.
Unit
Fscl
SCL clock frequency
0
-
400
kHz
thd,sta
Hold time (repeated) START condition
0.6
-
-
µs
tlow
LOW period of the SCL clock
1.3
-
-
µs
thigh
HIGH period of the SCL clock
0.6
-
-
µs
tsu,dat
Setup time for repeated START condition
0.6
-
-
µs
thd,dat
Data hold time
0.04
-
0.9
µs
tsu,dat
Data setup time
100
-
-
µs
tr
Rise time of both SDA and SCL signals
20 + 0.1 Cb
-
300
ns
tf
Fall time of both SDA and SCL signals
20 + 0.1 Cb
-
300
ns
tsu,sto
Setup time for STOP condition
0.6
-
-
µs
tbuf
Bus free time between a STOP and START condition
1.3
-
-
µs
Cb
Capacitive load for each bus line
-
-
400
pF
page 13/31
STUSB4710
Timing specifications
Figure 6. I²C timing diagram
DS12090 - Rev 8
page 14/31
STUSB4710
I²C register map
6
I²C register map
Table 9. STUSB4710 register map overview
Address
Register name
Access
Description
00h
to
Reserved
RO
Do not use
0Bh
ALERT_STATUS
RC
Alert register linked to transition registers
0Ch
ALERT_STATUS_MASK_CTRL
R/W
Interrupt mask on ALERT_STATUS register
0Dh
CC_CONNECTION_STATUS_TRANS
RC
Alerts on transition in CC_CONNECTION_STATUS register
0Eh
CC_CONNECTION_STATUS
RO
CC connection status
0Fh
MONITORING_STATUS_TRANS
RC
Alerts on transition in MONITORING_STATUS register
10h
MONITORING_STATUS
RO
Gives status on VBUS voltage monitoring
11h
Reserved
RO
Do not use
12h
HW_FAULT_STATUS_TRANS
RC
Alerts on transition in HW_FAULT_STATUS register
13h
HW_FAULT_STATUS
RO
Hardware faults status
Reserved
RO
Do not use
CC_CAPABILITY_CTRL
R/W
Allows the CC capabilities to be changed
Reserved
RO
Do not use
23h
RESET_CTRL
R/W
Controls the device reset by software
24h
Reserved
RO
Do not use
25h
VBUS_DISCHARGE_TIME_CTRL
R/W
Parameters defining VBUS discharge time
26h
VBUS_DISCHARGE_CTRL
R/W
Controls the VBUS discharge path
27h
VBUS_ENABLE_STATUS
RO
VBUS power path activation status
2Eh
VBUS_MONITORING_CTRL
R/W
Allows the monitoring conditions of VBUS voltage to be changed
Reserved
RO
Do not use
71h
SRC_PDO1
R/W
PDO1 capabilities configuration
75h
SRC_PDO2
R/W
PDO2 capabilities configuration
79h
SRC_PDO3
R/W
PDO3 capabilities configuration
7Dh
SRC_PDO4
R/W
PDO4 capabilities configuration
81h
SRC_PDO5
R/W
PDO5 capabilities configuration
91h
SRC_RDO
RO
PDO request status
0Ah
14h
to
17h
18h
19h
to
22h
19h
to
1Eh
DS12090 - Rev 8
page 15/31
STUSB4710
I²C register map
Table 10. Register access legend
Access code
Expanded name
RO
Read only
R/W
Read / write
RC
Read and clear
DS12090 - Rev 8
Description
Register can be read only
Register can be read or written
Register can be read and is cleared after read
page 16/31
STUSB4710
Typical use cases
7
Typical use cases
7.1
Power supply – buck topology
Figure 7. Power supply - buck topology
Power
Control
SW
FB 4
FB
L21
T2
T3
STL6P3LLH6 STL6P3LLH6
HC
Vsrc
GND
GND
R1
200k
R2
13k
15 SEL_PDO5
14 SEL_PDO4
R3
4k7
R5
8k66
R6
33k
SCL
7 SCL
SDA
8 SDA
R7
100k
13 Addr0
GND
R9
10k
R8
820
23 21
GND
10
GND
J1
A1 GND
GND B12
A2 Tx+1
Rx+1 B11
A3 Tx-1
Rx-1 B10
A4 Vbus
Vbus B9
A5 CC1
Sbu2 B8
TC-DP A6 D+1
D-2 B7 TC-DM
TC-DM A7 D-1
D+2 B6 TC-DP
A8 Sbu1
CC2 B5
A9 Vbus USB 3.1 Vbus B4
A10 Rx-2 TYPEC Tx-2 B3
A11 Rx+2
Tx+2 B2
A12 GND
GND B1
R11
2k2
U1
STUSB4710
24
Vbus
C4
10µF
R10
10k
GND
VBUS_DISCH 19
VBus_EN_SRC 20
VBus_Sense 18
11 SEL_PDO3
12 SEL_PDO2 Autonomous USB PD controller
with integrated discharge path
R4
4k87
GND
1µF
1µF
1µF
VDD
C3
C1
C2
Power plane
GND
VReg_1V2
Small signal
VReg_2V7
+
C3510 µF
C24 100pF
T1
STR2P3LLH6
68µH
C25220 µF
220nF
SW 8
PG 2
D21
STPS5L25B
C3210 µF
C2210 µF
C23
5 EN2
3 /EN1
6 GND
Vin
Boot 1
C21 100nF
U2
ST1S14PHR
7 Vin
GND
CC1 2
CC2 4
CC1
TC-DM
R12
TC-DP
100
CC2
ExpPAD
0
GND
The STUSB4710 offers the possibility to have up to 5 PDOs using (GPIO0 to GPIO3).
For example PDO1:5V 3A (no GPIO grounded), PDO2:9V 3A (GPIO0 to GND), PDO3:12V 3A (GPIO1 to GND),
PDO4:15 volt (GPIO2 to GND), PDO5: 20 volt GPIO3 to GND).
Table 11. Resistor value
PDO VOUT
DS12090 - Rev 8
-
-
5
20
4
15
3
12
2
9
1
5
Computation
Resistor value (Ω)
R1
200 k
R ∙ 1.22
R2 = V 1 − 1.22
OUT
R ∙ 1.22
R3 = V 1 − 1.22 − R2
OUT
R ∙ 1.22
R4 = V 1 − 1.22 − R2 − R3
OUT
R ∙ 1.22
R5 = V 1 − 1.22 − R3 − R4
OUT
R ∙ 1.22
R6 = V 1 − 1.22 − R2 − R3 − R4 − R5
OUT
(1)
13 k
(2)
4k7
(3)
4k87
(4)
8k66
(5)
33 k
page 17/31
STUSB4710
Power supply – flyback topology
7.2
Power supply – flyback topology
The STUSB4710 offers the possibility to have up to 5 PDOs using GPIO0 to GPIO3.
For example PDO1 ( 5 V; 3 A) (no Sel_PDO grounded), PDO2 (9 V; 3 A) (GPIO0 to GND), PDO3 (15 V; 3 A)
(GPIO1 to GND).
Figure 8. Flyback topology
J1
A1 GND
A2 Tx+1
3
U20
C22
8
1
HV
GD
1
R23 STTH1R06A
7
B
D22
1N4148WS
R24
0.15
A3 Tx-1
A4 Vbus
Vbus
R22
33
R8
1k5
+ C23
680µF
C24
1.5nF
4
4.7
sense
GND
FB
NC
A
STCH02
VDD
CURRENT
CONTROL
6
ZCD
+
-
3
2
2.5V
5
U21
2
R21
220 D20
100nF
4
T?
STS10P3LLH6
C21
2.2nF
R20
100k
VDD
R9
10k
R10
10k
T1
STS5P3LLH6
+
R11
2k2
D21
5
Tr20
C25
A5 CC1
A6 D+1
C4
10µF
A7 D-1
A8 Sbu1
Vbus
Vbus_EN_SRC
C20
68µF
Vbus_DISCH
+
STF10LN80K5
+
-
T20
~
~
GND
Rx+1
Rx-1
Vbus
Sbu2
D-2
D+2
CC2
B12
B11
B10
B9
B6
B5
A9 Vbus
B4
USB 3.1 Vbus
A10 Rx-2 TYPE C Tx-2 B3
A11 Rx+2
B2
Tx+2
A12 GND
GND
B1
1000pF
R25
VDD
D23
R30
+
C26
22µF
D24 20k
15V
BAV103 4.7
+
C27
22µF
1k
R28
U22A
SFH617A-2
R31
C28
1k
33nF
R29
12k
D25
TLVH431AIL3T
R32
30k
C29
220pF
U22B
SFH617A-2
1µF
C1
1µF
C2
1µF
R1
100k
23
21
VReg_2V7
T21
BC847C
C3
15
R3
8k87
14
11
R4
2k49
12
R5
4k42
U1
STUSB4710
24
VDD
R27
VReg_1V2
360k
R26
22k
VBUS_DISCH
VBus_EN_SRC
SEL_PDO5
VBus_Sense
SEL_PDO2
8
R6
16k2
13
20
Autonomous USB PD controller
with integrated discharge path
CC1
7
19
18
SEL_PDO4
SEL_PDO3
SCL
CC2
2
CC1
4
CC2
SDA
Addr0
R7
100k
GND
10
ExpPAD
0
Table 12. Resistor value
PDO VOUT
DS12090 - Rev 8
-
-
4
15
3
12
2
9
1
5
Resistor value
Computation
(Ω)
R1
R ∙ 1.24
R3 = V 1 − 1.24
OUT
R ∙ 1.24
R4 = V 1 − 1.24 − R3
OUT
R ∙ 1.24
R5 = V 1 − 1.24 − R3 − R4
OUT
R ∙ 1.24
R6 = V 1 − 1.24 − R3 − R4 − R5
OUT
100 k
(6)
8k87
(7)
2k49
(8)
4k42
(9)
16k2
Vbus
B8
B7
page 18/31
Vbus
STUSB4710
Electrical characteristics
8
Electrical characteristics
8.1
Absolute maximum ratings
All voltages are referenced to GND.
Table 13. Absolute maximum ratings
Symbol
Parameter
Value
Unit
VDD
Supply voltage
28
V
VCC1, VCC2
High voltage on CC pins
22
V
High voltage on VBUS pins
28
V
VSCL, VSDA, VSEL_PDO[5:2]
Operating voltage on I/O pins
-0.3 to 6
V
TSTG
Storage temperature
-55 to 150
°C
TJ
Maximum junction temperature
145
°C
HBM
4
CDM
1.5
VVBUS_EN_SRC
VVBUS_SENSE
VVBUS_DISCH
ESD
8.2
kV
Operating conditions
Table 14. Operating conditions
Symbol
Parameter
Value
Unit
VDD
Supply voltage
4.1 to 22
V
-0.3 to 5.5
V
High voltage pins
0 to 22
V
VSCL, VSDA, VSEL_PDO[5:2]
Operating voltage on I/O pins
0 to 4.5
V
TA
Operating temperature
-40 to 105
°C
VCC1, VCC2
CC pins
(1)
VVBUS_SENSE
VVBUS_EN_SRC
VVBUS_DISCH
1. Transient voltage on CC1 and CC2 pins are allowed to go down to -0.3 during BMC communication from connected
devices.
DS12090 - Rev 8
page 19/31
STUSB4710
Electrical and timing characteristics
8.3
Electrical and timing characteristics
Unless otherwise specified: VDD = 5 V, TA = +25 °C, all voltages are referenced to GND.
Table 15. Electrical characteristics
Symbol
IDD(SRC)
Parameter
Min.
Typ.
Max.
Unit
188
–
µA
–
53
–
µA
CC pin voltage
-20%
80
+20%
µA
VCC = -0.3 to 2.6 V
-8%
180
+8%
µA
-40° < TA < +105°
-8%
330
+8%
µA
2.75
–
–
V
-10%
5.1
+10%
kΩ
–
–
1.2
V
–
–
2
V
200
–
–
kΩ
0.15
0.2
0.25
V
Device Idle as SOURCE (not connected, no communication)
Current
consumption V @ 5.0 V
–
DD
Standby
ISTDBY
Test conditions
Device standby (not connected, low power)
current
VDD @ 5.0 V
consumption
CC1 and CC2 pins
IP-USB
IP-1.5
CC current
sources
IP-3.0
VCCO
Rd
CC open pin
voltage
CC pulldown
resistors
CC pin
VCCDB-1.5 voltage in
VCCDB-3.0 dead battery
condition
RINCC
CC input
impedance
VTH0.2
Detection
threshold 1
CC unconnected,
VDD=3.0 to 5.5 V
-40° < TA < +105°
External IP=180 µA applied into CC
External IP=330 µA applied into CC
(VDD = 0, dead battery function enabled)
Pull-up and pull-down resistors off
Max. Ra detection by DFP at IP = IP -USB,
min. IP_USB detection by UFP on Rd,
min. CC voltage for connected UFP
VTH0.4
Detection
threshold 2
Max Ra detection by DFP at IP = IP-1.5
0.35
0.4
0.45
V
VTH0.66
Detection
threshold 3
Min IP_1.5 detection by UFP on Rd
0.61
0.66
0.7
V
VTH0.8
Detection
threshold 4
Max. Ra detection by DFP at IP = IP-3.0
0.75
0.8
0.85
V
VTH1.23
Detection
threshold 5
Min. IP_3.0 detection by UFP on Rd
1.16
1.23
1.31
V
VTH1.6
Detection
threshold 6
Max Rd detection by DFP at IP = IP-USB and
IP = IP-1.5
1.5
1.6
1.65
V
VTH2.6
Detection
threshold 7
Max. Rd detection by DFP at IP-3.0, max.
CC voltage for connected UFP
2.45
2.6
2.75
V
3.8
3.9
4
V
0.5
0.6
0.7
0.8
0.9
1
1.1
1.2
1.3
VBUS monitoring and driving
VTHUSB
VTH0V
VBUS
presence
threshold
VBUS safe
Programmable threshold (from 0.6 to 1.8 V)
0V threshold
Default VTHOV = 0.6 V
(vSafe0V)
DS12090 - Rev 8
V
page 20/31
STUSB4710
Electrical and timing characteristics
Symbol
Min.
Typ.
Max.
Unit
VBUS safe
Programmable threshold (from 0.6 to 1.8 V)
0V threshold
Default VTHOV = 0.6 V
(vSafe0V)
1.7
1.8
1.9
V
RDISUSB
VBUS
discharge
resistor
600
700
800
Ω
TDISUSB
VBUS
discharge
time to 0 V
70 *TDISPARAM
84 *TDISPARAM
100 *TDISPARAM
ms
TDISUSB
VBUS
discharge
time to PDO
20 *TDISPARAM
24 *TDISPARAM
28 *TDISPARAM
ms
–
VBUS +10%
–
V
–
VBUS -10%
–
V
VTH0V
Parameter
VBUS
VMONUSB monitoring
high voltage
H
threshold
VBUS
VMONUSB monitoring
low voltage
L
threshold
Test conditions
Default TDISUSB= 840 ms. The coefficient
TDISPARAM is programmable by NVM
Default TDISUSB= 200 ms
The coefficient TDISPARAM is programmable
by NVM
VBUS = nominal target value
Default VMONUSBH = VBUS +10%
The threshold limit is programmable by
NVM from VBUS +5% to VBUS +20%
VBUS = nominal target value
Default VMONUSBL= VBUS -10%
The threshold limit is programmable by
NVM from VBUS -20% to VBUS -5%
Digital input/output (SCL, SDA)
VIH
High level
input voltage
1.2
–
–
V
VIL
Low level
input voltage
–
–
0.35
V
VOL
Low level
output
voltage
–
–
0.4
V
–
–
0.4
V
Ioh = 3 mA
20 V open-drain outputs (VBUS_EN_SRC)
VOL
Low level
output
voltage
DS12090 - Rev 8
Ioh = 3 mA
page 21/31
STUSB4710
Package information
9
Package information
In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK packages,
depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product
status are available at: www.st.com. ECOPACK is an ST trademark.
9.1
QFN24 EP 4x4 mm package information
Figure 9. QFN24 EP 4x4 mm package outline
DS12090 - Rev 8
page 22/31
STUSB4710
QFN24 EP 4x4 mm package information
Table 16. QFN24 EP 4x4 mm package mechanical data
mm
Symbol
Min.
Typ.
Max.
A
0.80
0.90
1.00
A1
0.00
0.02
0.05
A3
0.20 Ref.
b
0.18
0.25
0.30
D
3.90
4.00
4.10
D2
2.55
2.70
2.80
E
3.90
4.00
4.10
E2
2.55
2.70
2.80
e
0.50
k
0.20
-
-
L
0.30
0.40
0.50
Table 17. Tolerance of form and position
Symbol
mm
aaa
0.05
bbb
0.10
ccc
0.10
ddd
0.05
eee
0.08
Figure 10. QFN24 EP 4x4 mm recommended footprint
DS12090 - Rev 8
page 23/31
STUSB4710
QFN 16 (3x3 mm), pitch 0.50 package information
9.2
QFN 16 (3x3 mm), pitch 0.50 package information
Figure 11. QFN 16 (3x3 mm) package outline
Note:
DS12090 - Rev 8
•
•
Nxb means N pads with b width
NxL means N pads with L length
page 24/31
STUSB4710
QFN 16 (3x3 mm), pitch 0.50 package information
Table 18. QFN 16 (3x3 mm) mechanical data
Symbol
DS12090 - Rev 8
1.
2.
3.
Min.
Typ.
Max.
A
0.5
0.65
A1
0
0.05
b
0.18
0.25
D
3.00 bsc
E
3.00 bsc
e
0.50
L
Note:
mm
0.40
0.50
0.30
0.60
aaa
0.15
bbb
0.10
ccc
0.10
ddd
0.05
eee
0.08
n
16
nD
4
nE
4
N is the total number of terminals
nD and nE refer to the number of terminals on D and E side respectively
Dimensions b applies to metallized terminal and is measured between 0.15 mm and 0.30 mm from the
terminal tip. If the terminal has the optional radius on the other end of the terminal, the dimension b
should not be measured on that radius area
page 25/31
STUSB4710
Thermal information
9.3
Thermal information
Table 19. Thermal information
Package
Symbol
Parameter
Value
RθJA
Junction-to-ambient
thermal resistance
37
RθJC
Junction-to-case thermal
resistance
5
RθJA
Junction-to-ambient
thermal resistance
78
RθJC
Junction-to-case thermal
resistance
30
QFN24 EP
QFN16
DS12090 - Rev 8
Unit
°C/W
page 26/31
STUSB4710
Packing information
9.4
Packing information
Figure 12. Reel information
Table 20. Tape dimensions
DS12090 - Rev 8
Package
Pitch
Carrier width
Reel
QFN 4x4 - 24L
8 mm
12 mm
13"
page 27/31
STUSB4710
Terms and abbreviations
10
Terms and abbreviations
Table 21. List of terms and abbreviations
Term
Accessory
modes
Audio adapter accessory mode. It is defined by the presence of Ra/Ra on the CC1/CC2 pins.
Debug accessory mode. It is defined by the presence of Rd/Rd on CC1/CC2 pins in source power role or
Rp/Rp on CC1/CC2 pins in sink power role.
DFP
Downstream facing port, associated with the flow of data in a USB connection. Typically, the ports on a host
or the ports on a hub to which devices are connected. In its initial state, the DFP sources VBUS and VCONN
and supports data.
DRP
Dual-role port. A port that can operate as either a source or a sink. The port role may be changed
dynamically.
Sink
Port asserting Rd on the CC pins and consuming power from the VBUS; most commonly a device.
Source
Port asserting Rp on the CC pins and providing power over the VBUS; usually a host or hub DFP.
UFP
DS12090 - Rev 8
Description
Upstream facing port, specifically associated with the flow of data in a USB connection. The port on a device
or a hub that connects to a host or the DFP of a hub. In its initial state, the UFP sinks the VBUS and supports
data.
page 28/31
STUSB4710
Ordering information
11
Ordering information
Table 22. Ordering information
Order code
Description
Package
Marking
STUSB4710AQ1TR
Autonomous USB PD
controller (provider)
QFN16 (3x3 mm)
471A
QFN24 EP (4x4 mm)
4710A
STUSB4710AQTR
DS12090 - Rev 8
page 29/31
STUSB4710
Revision history
Table 23. Document revision history
Date
Version
Changes
05-Apr-2017
1
Initial release.
12-Jul-2017
2
Updated Features, Table 2: "Pin functions list", Section 2.3.10: "SEL_PDO
[5:2]", Section 4.4: "Monitoring configuration in NVM", Section 4.5:
"Discharge configuration in NVM", Section 5.1: "Read and write
operations", Table 15: "Operating conditions ", Table 20: "Thermal
information", and Section 7.2: "Power supply – flyback topology".
23-Aug-2017
3
Updated Table 1: "Device summary table"
13-Nov-2017
4
24-Mar-2021
5
Updated QFN16 (3x3x0.55) package information and Section 9.1 QFN24
EP 4x4 mm package information.
22-Jul-2021
6
Updated the title of figure 2 and figure 3.
20-Oct-2022
7
Updated Section 9.2 QFN 16 (3x3 mm), pitch 0.50 package information.
15-Dec-2022
8
Updated Section 3.9.2 Debug accessory mode detection.
Updated the features and the device summary table in cover page.
Minor text changes throughout the document.
Added Section 11 Ordering information.
DS12090 - Rev 8
page 30/31
STUSB4710
IMPORTANT NOTICE – READ CAREFULLY
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products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST
products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgment.
Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of
purchasers’ products.
No license, express or implied, to any intellectual property right is granted by ST herein.
Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product.
ST and the ST logo are trademarks of ST. For additional information about ST trademarks, refer to www.st.com/trademarks. All other product or service names
are the property of their respective owners.
Information in this document supersedes and replaces information previously supplied in any prior versions of this document.
© 2022 STMicroelectronics – All rights reserved
DS12090 - Rev 8
page 31/31
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