STV0674-100TQFP

® STV0674 Tri-mode CMOS digital camera co-processor Description The STV0674 is a flexible, scalable digital camera co-processor for use with the range of CMOS imaging sensor products from STMicroelectronics. The same chipset can be used for a wide range of digital imaging products with unique features and price/performance points. The STV0674 is designed for use with CIF (352x288) or VGA (640x480) ST CMOS image sensors and provides full exposure control, color processing and mode control for these sensors. The STV0674 can be used to implement any of the following products: Low cost USB Webcam Camera - a two-chip solution providing up to 30 frames per second VGA simultaneous video and audio capture. Dual-Mode Camera - USB webcam and CIF or VGA digital still camera in a single product. Tri-Mode Camera - USB webcam and digital still camera with the addition of a ‘camcorder’ mode to allow simultaneous video and audio capture directly to external memory for later upload to the PC. Features s VGA or CIF CMOS sensor support s Hardware color processing and JPEG compression of image data s Still image capture s Tethered video operation over USB q Simultaneous video and audio capture USB for PC and MacOS (in development) SDRAM for lower cost, (8 or 16 bit) FLASH for non volatile storage (Data + Code) Smartmedia Card for removable data storage EEPROM for code storage s USB q s Flexible external memory options q q q q s Record simultaneous video and audio direct to memory while untethered s Drivers for PC operating systems Win98, WinME, Win2K and WIn XP. Application Block Diagram STMicroelectonics CMOS Sensor 5 STV0674 100TQFP USB Cable to Host PC Video Processor Video Compression USB Interface Hardware Enabled Firmware enabled User Interface Buttons/ Switches Image Array NAND FLASH SDRAM + x16 or x8 BOOT EE-PROM OEM Flashgun Module LCD Driver Chip Microphone Micro Processor Audio Interface GPIO SOCKET Audio Playback POWER AMP SmartMedia Removable Flash card Buzzer OR LCD Icon Display OR LCD Driver Chip Memory LCD Image Display July 2003 ADCS 7269750C 1/35 STV0674 Table of Contents Chapter 1 1.1 1.2 1.3 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 Webcam Mode ..................................................................................................................... 5 Dual-Mode (Webcam plus Digital Still Camera) ................................................................... 5 Tri-Mode (Webcam plus Digital Still Camera plus Digital Movie/Audio Recorder) ............... 5 Chapter 2 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 STV0674 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 Sensor interface ................................................................................................................... 6 Video processor ................................................................................................................... 6 Video compressor ................................................................................................................ 6 Microcontroller ...................................................................................................................... 7 Memory interfaces ................................................................................................................ 7 Audio record ......................................................................................................................... 8 Audio playback ..................................................................................................................... 8 USB PC interface ................................................................................................................. 8 Power requirements ............................................................................................................. 8 Chapter 3 3.1 3.2 STV0674 Application Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 Webcam with audio .............................................................................................................. 9 Tri-mode camera ................................................................................................................ 10 Chapter 4 4.1 4.2 4.3 4.4 4.5 4.6 4.7 4.8 4.9 Detailed Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 Absolute maximum ratings ................................................................................................. 11 DC characteristics .............................................................................................................. 11 SDRAM interface ............................................................................................................... 13 NAND flash interface .......................................................................................................... 15 USB interface ..................................................................................................................... 20 Audio .................................................................................................................................. 21 SFP AC parameters ........................................................................................................... 22 Sensor interface ................................................................................................................. 22 Device current consumption in run and suspend modes ................................................... 23 Chapter 5 5.1 Pinout and Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 Device pinout ..................................................................................................................... 24 2/35 STV0674 5.2 5.3 5.4 Pin description .................................................................................................................... 26 Package outline and mechanical data ............................................................................... 31 External circuits .................................................................................................................. 32 Chapter 6 6.1 6.2 Evaluation Kit and Reference Design Manuals . . . . . . . . . . . . . . . . . . . . . . . . .33 Evaluation kit ...................................................................................................................... 33 Reference design manuals ................................................................................................ 33 Chapter 7 Ordering Details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 3/35 STV0674 Revision History Revision A B Date 03/10/2001 16/08/2002 Initial release Changes Expansion of AC /DC specifications section 7 Added Figures 11 and 14, “Signals identified by functional group” Detail added to Table 10, pull down on SFP 19 required Detail added to Table 10, pull down on SFP 14 required C 17/04/2003 26/05/2003 Deletion of any reference to 64TQFP package. DC charascteristics - Changed value for I/O high power current: 2 mA instead of 5.7 mA previously. 4/35 STV0674 Overview 1 Overview The STV0674 can be used to implement 3 different low-cost CMOS camera products as detailed here below. 1.1 Webcam Mode STV0674 allows a two-chip solution to provide a USB webcam, which can acquire and display images on the host system at frame rates of up to 30fps VGA. The addition of an external microphone allows simultaneous audio acquisition. Custom drivers require an additional low cost EEPROM which allows USB parameters such as Vendor ID /Product ID to be customised. 1.2 Dual-Mode (Webcam plus Digital Still Camera) While retaining all the features of the webcam, the addition of external storage memory allows the functionality of a digital still camera. On-chip JPEG compression permits high-density picture storage. 16Mbit to 128Mbit of SDRAM (8 or 16 bit) and/or 32Mbit to 1Gbit NAND flash memory are supported by the device. Also supported are the popular Smart Media Cards (SMC) to extend nonvolatile storage capability. The wide range of memory support allows the camera builder to tailor the system cost to suit their target market. A continuous image acquisition mode allows untethered (no host connection) video clips to be taken. As an example, with 15:1 compression ratio and 128Mbit memory over two minutes (QVGA @10fps) worth of video can be stored and up-loaded for display on the host. Full Direct Show driver support for Windows 98SE, ME, Windows 2000, Win XP is available. MacOS is currently in development. 1.3 Tri-Mode (Webcam plus Digital Still Camera plus Digital Movie/Audio Recorder) Again, retaining the features of the dual mode camera, the inclusion of audio record and playback circuitry adds another dimension to the product. An in-system microphone allows audio to be recorded and played back either via a speaker on the camera or via the host sound system. Audio can either be recorded simultaneously with video (camcorder) or independently of image acquisition (dictaphone). Audio data can also be downloaded from the host and played back on the camera when events take place. This allows any sampled soundbites to be played back on cameras, as opposed to the normal beeps from traditional cameras, which offers many possibilities for language customisation or licensed “character” cameras. As well as the memory and audio options already described, the GPIO and firmware emulation make it possible to support other custom peripherals such as icon or area displays. Other custom peripherals such as icon or area displays can be support via uncommitted general purpose I/O under firmware control. ST Microelectronics provides a software development kit (SDK) allowing OEMs to create custom PC applications, and an OEM pack to modify drivers to their specific requirements. 5/35 STV0674 Functional Description STV0674 2 STV0674 Functional Description The STV0674 uses a combination of hardware functions and firmware to implement the required features. While the following features are selected and controlled via firmware their operation is carried out by dedicated hardware core. All dedicated hardware functions use fixed pin numbers which are detailed in Section 5.2. 2.1 Sensor interface The sensor interface is compatible with ST Microelectronics CIF and VGA sensors. This interface consists of a 5-wire sensor data output with additional sync signals, clocking, and I2C interface for configuration. All sensor communications, exposure/gain control, color processing, white balance control, and clocking are handled automatically by STV0674. 2.2 Video processor The video processor (VP) provides formatted YCbCr 4:2:2-sampled digital video at frame rates up to 30 frames per second to the video compressor (VC) module or internal video FIFO. The VP also interfaces directly to the image sensors. The interface to the sensor incorporates: q q a 5-wire data bus SDATA[4:0] that receives both video data and embedded timing references. a 2-wire serial interface SSDA,SSCL that controls the sensor and the sensor register configuration. the sensor clock SCLK. full colour restoration at each pixel site from Bayer-patterned input data defect correction matrixing/gain on each colour channel for colour purity auto white balance, exposure and gain control peaking for image clarity gamma correction colour space conversion (including hue and saturation control) from raw RGB to YCbCr[4:2:2]. q The video processing engine performs the following functions on incoming data q q q q q q q 2.3 Video compressor The video compression engine performs 3 main functions: q Up scaling of input YCbCr 4:2:2 video stream from the VP (typically to scale from QVGA to CIF image formats), Compression and encoding of YCbCr stream into Motion-JPEG (M-JPEG) format, FIFO monitoring. q q The data stream from the VP can be up to VGA size. The scaler in VC can downsize this image. Once scaled, the video stream is then converted into M-JPEG format. M-JPEG treats video as a series of JPEG still images. The conversion is released via a sequential DCT (Discrete Cosine Transform) with Huffman encoding. After transfer through the digiport or over USB, the M-JPEG stream can be decoded in the host. 6/35 STV0674 STV0674 Functional Description The VC module varies the compression ratio to match the scene and selected frame rate, to the FIFO fill state. The VC module is capable of compression ratios of up to 100:1. Thumbnails can also be generated within the VC for potential display on an image LCD. The final stage of the VC block manages the data transfer rate from the local VC FIFO store to the memory or USB core. The VC can perform this management automatically, by employing long-term (frame-level) and short-term (block-level) compression management. 2.4 Microcontroller The STV0674 has an embedded high-performance 8052 8-bit microcontroller with 32 Kbytes of ROM and 32 Kbytes of SRAM available for program memory. The device functionality provided by default program ROM is generally sufficient to address all needs of a USB-tethered camera. In STV0674, code can be executed from the local SRAM as well as default ROM. The default ROM provides basic functions such as USB control, memory control, VP setup, systems installation, and the transfer of application specific code into the local SRAM. In non-tethered applications, the SRAM can be loaded from off-chip EEPROM via I2C or from an external flash device. If required in tethered applications, the SRAM can be loaded from the host PC via the USB. The ROM bootloader will load the application specific firmware code from one of the following sources, in order of priority: 1 2 3 EEPROM. NAND FLASH. PC host (in the case of a webcam). 2.5 2.5.1 Memory interfaces NAND FLASH memory/SmartMedia card interface The NAND FLASH module for the STV0674 provides a dedicated interface to an external 32 Mbit to 1 Gbit NAND FLASH chip, and/or 4 Mbyte to 128 Mbyte SmartMedia card. NAND flash devices can contain a number of bit errors, and the core may deteriorate over time. Both occurrences are handled automatically by STV0674. A camera using NAND flash for image storage has the advantage that it can be powered off (e.g. auto power off, or for changing batteries) without losing images. No serial EEPROM is required as the application specific programme code can be stored in NAND flash memory. Note: 1 Support for SMC is for 3V3 cards. 5V cards are not supported. 2 Standard digital camera file formats (e.g. DOS file format, SSFDC) are not supported on SMC cards at this time. 2.5.2 SDRAM interface The STV0674 can use SDRAM for image storage and is designed to operate with PC66 or better compliant devices and supports 16Mbit, 64Mbit and 128Mbit parts in both the x16 SDRAM or x8 DRAM word widths. It is recommended that any SDRAM used have low self refresh Idd. 7/35 STV0674 Functional Description 2.5.3 EEPROM interface STV0674 The STV0674 supports up to 512Kbit EEPROM to hold application specific firmware code. Also, in the case of a tethered only web cam, lower density EEPROMs (down to 1Kbit) can be used to store information regarding custom USB Product ID, Vendor ID and power consumption. 2.6 Audio record The audio record block consists of a 16bit delta-sigma ADC using sampling frequencies of 8 kHz, 11.025 kHz, 16 kHz, 22.05 kHz, 32 kHz, 44.1 kHz and 48 kHz, with either differential or single ended inputs. The sampled output can be 8 or 16 bit. 2.7 Audio playback Audio playback is achieved by an internal Pulse Width Modulator with sample rates of 8kHz, 11.025kHz, 16kHz, 22.05kHz, 32kHz or 44.1kHz, connected to either an external amplifier chip and loudspeaker/ headphone socket or to a simple piezo buzzer. 2.8 USB PC interface The STV0674 includes a USB version 1.1 compliant Universal Serial Bus interface which requires the minimum of additional hardware. The interface key features are listed here below. q q q q q q q q q Compliant with USB protocol revision 1.1 USB audio class compliant USB protocol handling USB device state handling Clock and data recovery from USB Bit stripping and bit stuffing functions CRC5 checking, CRC16 generation and checking Serial to parallel conversion Twin bulk end points (in/out) USB drivers are supplied by ST. For USB timing information, please refer to the USB specification version 1.1. 2.9 Power requirements STV0674 requires a 3V3 supply for I/O and a 1V8 supply for the core. 8/35 STV0674 STV0674 Application Examples 3 STV0674 Application Examples The initial STV0674 released by ST Microelectronics is supplied with generic firmware application code to realise one of the following camera types. 3.1 3.1.1 Webcam with audio Overview This camera uses the minimum of external components and has no user interface, batteries or memory for image storage. It is used as a tethered video capture camera over USB, with simultaneous audio and video. It is controlled entirely through PC drivers. The application specific firmware is downloaded from the PC. Note: A custom USB PID/VID can be configured by the use of an EEPROM, if required. 3.1.2 Application diagram Figure 1: Application diagram when using STV0674 as webcam with audio lens + IR filter CMOS Sensor CIF or VGA image array video processor STV0674 video compression USB interface USB Cable to host PC Audio pre-amp microphone audio interface micro processor external memory interface EEPROM embedded memory (not for image store) 9/35 STV0674 Application Examples STV0674 3.2 3.2.1 Tri-mode camera Overview Applications with the tri-mode camera based on STV0674 range from low-cost cameras containing an icon LCD status display, microphone/speaker and small SDRAM chip (for example 16Mbit), to an enhanced feature set camera containing a graphical image LCD display for image review, flashgun, audio record/playback, NAND flash on the PCB and a SmartMedia flash memory socket. 3.2.2 Application diagram Figure 2: Application diagram when using STV0674 as tri-mode camera Lens + IR Filter CMOS Sensor CIF or VGA STV0674 100TQFP USB Cable to Host PC Memory User Interface Buttons/ Switches QUALITY PICTURES SECONDS MBYTES HIGH MED LOW NAND FLASH Image Array Microphone Flash Enable/ Trigger 5 Video Processor Video Compression USB Interface LCD Driver Chip SDRAM + BOOT EEx16 or x8 -PROM Audio Interface Micro Processor External Memory Interface EEPROM only required if no NAND Flash OEM Flashgun Module LCD Status Icon Display OR LCD Driver Chip 23 PICS Audio Playback POWER AMP Buzzer OR Embedded Memory (not for image store) LCD Interface Buttons Interface SOCKET SmartMedia Removable Flash card 640x480 LCD Image Display 10/35 STV0674 Detailed Specifications 4 4.1 Detailed Specifications Absolute maximum ratings Description Operating Temperature Storage Temperature Range 0 to 70a -50 to 150 Unit oC oC a. Refer to the sensor datasheet to determine operating temperature range of complete application 4.2 DC characteristics Table 1: DC characteristics Parameter VDDC VDDI VDDP VDDA Description Primary power supply (core) 3.3V power supply for on-chip USB transceiver and IO Analog supply to the PLL Analog supply to the audio front end core suspend current I/O suspend current Min 1.55 3.0 1.60 3.0 Typ. 1.8 3.3 1.8 3.3 6 31.5 0 1.5 12.5 0.9 0.5 1.5 50.4 2 0.5 5.1 Max 1.95 3.6 2.0 3.6 Units V V V V µA µA µA µA mA mA mA µA mA mA mA mA Notes Note 4 Isuspend PLL suspend current Audio suspend current Core low power current I/O low power current Ilowpower PLL low power current Audio low power current Core high power current I/O high power current Ihighpower PLL high power current Audio high power current VILU VIHU VIHUZ VDI USB differential pad D+/D- input low USB differential pad D+/D- input high (driven) USB differential pad D+/D- input high (floating) USB differential pad D+/D- input sensitivity 2.0 2.7 0.2 3.6 Note 5 Note 6 Note 6 Note 6 Note 6 Note 6 Note 6 Note 6 Note 6 0.8 V V V V Note 1 11/35 Detailed Specifications Table 1: DC characteristics Parameter VCM VOLU VOHU VOHU VCRS Zdrv VIl VIH VHYS VIl VIH Vhyst VT+ VTVT VOH VOL STV0674 Description USB differential pad D+/D- common mode voltage USB differential pad D+/D- output low voltage USB differential pad D+/D- output high voltage USB differential pad D+/D- output high voltage USB differential pad D+/D- output signal cross over voltage Driver output resistance CMOS input low voltage (XTAL_IN) CMOS input high voltage (XTAL_IN) Hysteresis (XTAL_IN) CMOS input low voltage (TC pad) CMOS input high voltage (TC pad) Schmitt trigger hysteresis CMOS schmitt input low to high threshold voltage (TC pad) CMOS schmitt input high to low threshold voltage (TC pad) Threshold point (TC pad) Output high voltage (TC pad) Output low voltage (TC pad) Min 0.8 0.0 2.8 2.8 1.3 28 Typ. Max 2.5 0.3 3.6 3.6 2.0 44 0.631 Units V V V V V Notes Note 2 Ω V V 1.123 0.492 0.35VDD 0.65VD D 0.4 2.15 1.05 1.65 2.4 0.4 V V V V V V V V V Note 3 Note 3 Note 3 Note 3 Note 3 Note 3 Note: 1 VDI = |(D+) - (D-)| 2 VCM includes VDI range. 3 These figures apply to sfp, sensor_clk, sensor_scl, sensor_sda, test_mode and sensor_db. They do not apply to the XTAL_IN pad, these are specified separately. 4 In normal operation the actual device operating voltage is the worst case figure of the PLL and Core supplies, or 1.60V to 1.95V. 5 Below measurable limits. 6 See Section 4.9 12/35 STV0674 Detailed Specifications 4.3 SDRAM interface Read/write timing diagrams for external synchronous DRAM Figure 3: SDRAM read timing tCK DCLK CKE tCMS tCMH Command ACTIVE tCL tCH READ NOP PRECHARGE NOP A0-9,BA ROW COLUMN A10 ROW tAS tAH tCMS tAC tOH tCMH DQM DQ tRCD CAS Latency tRC tRAS tRP DOUT M DOUT M + 1 DOUT M + 2 DOUT M + 3 DQ sample DQ sample DQ sample DQ sample 13/35 Detailed Specifications Figure 4: SDRAM write timing STV0674 tCK DCLK CKE tCMS Command tCMH tCL tCH ACTIVE WRITE NOP PRECHARGE NOP A0-9,BA ROW COLUMN A10 ROW tAS tAH tCMS tDS tDH tCMH DQM DQ tRCD DIN M DIN M + 1 DIN M + 2 DIN M + 3 tRC tRAS tRP Table 2: SDRAM timing Symbol tCK tCH tCL tAC tOH tCMS tCMH tAS 0 20.27 20.02 20.67 20.11 20.11 Min Typ. 41.67 20.83 20.83 Max Units ns Symbol tDS tDH tRCD tRAS tRC tRP tRRD tAH Min 20.12 21.82 1 2 4 2 2 19.79 Typ. Max Units ns ns tCK tCK tCK tCK tCK ns 21.55 21.55 24.76 tCK tCK ns ns ns ns ns Note: 1 The SDRAM interface is designed to operate with SDRAM devices which are compliant with the Intel SDRAM Specification Revision 1.7 November 1999. Speed grades 66, 100 and 133MHz are compatible. 2 Above timing assumes 20pF load per pad. 14/35 STV0674 Detailed Specifications 4.4 4.4.1 NAND flash interface Command latch cycle for NAND flash interface Figure 5: Command latch cycle CLE tCLS CE_n tWP WE_n tALS ALE tDS IO[7:0] tDH tALH tCLH Command 4.4.2 Address Latch Cycle for NAND Flash Interface Figure 6: Address latch cycle CLE tCLS CE_n tWP WE_n tALH ALE tDS tDH IO[0:7] A0-A7 A9-A16 A17-A21 tWH tWC 15/35 Detailed Specifications 4.4.3 Input data latch cycles for NAND Flash interface Figure 7: Input data latch cycle STV0674 CLE CE_n tALS ALE tWP WE_n tDS tDH IO[0:7] DIN0 DIN1 DIN511 tWH tWC tCLH 4.4.4 Sequential output cycle after read for NAND Flash interface Figure 8: Sequential output cycle after read tRC CE_n tRP RE_n tREA IO[0:7] tRR RB_n Dout Dout Dout tREH 16/35 STV0674 4.4.5 Status read cycle for NAND flash interface Figure 9: Status read cycle Detailed Specifications CLE tCLS CE_n tWP WE_n tWHR tCLH tCLS RE_n tDS IO[0:7] 70h tDH tRSTO Status 4.4.6 Read operation for NAND flash interface Figure 10: Read operation CLE CE_n WE_n tWB ALE RE_n tR tRR IO[0:7] RB_n 00H A0-7 A9-16 A17-21 Dout0 Dout1 Dout2 17/35 Detailed Specifications 4.4.7 Reset operation for NAND flash interface Figure 11: Reset operation STV0674 CLE CE_n WE_n IO[0:7] RB_n tRST FFh 18/35 STV0674 4.4.8 AC characteristics for operation Table 3: AC characteristics Symbol tCLS tCLH tWP tALS tALH tDS tDH tWC tWH tRR tRP tRC tREA tREH tWHR tR tWB tRST Detailed Specifications Parameter CLE set-up time CLE hold time WE-n pulse width ALE set-up time ALE hold time Data set-up time Data hold time Write cycle time WE_n high hold time Ready to RE_n low RE_n pulse width Read cycle time RE_n access time RE_n high hold time WE_n high to RE_n low Data transfer from cell to register WE_n high to busy Device resetting (Read) Min 61.36 83.2 83.2 82.64 82.44 82.65 61.85 145.09 61.89 80.99 83.2 187.2 Typical 62.4 Max Unit ns ns ns 83.2 83.2 83.2 62.4 145.6 62.4 83.2 ns ns ns ns ns ns ns ns ns 35 103.47 124.22 104 124.8 43.2 ns ns ns 25.015 41.6 215.28 5.015 µs ns µs Note: 1 All parameters relating to the CE_n signal are omitted as it is not enabled/disabled during execution of any NAND flash operation. 2 All timings are worst case. 3 Conforms to both Samsung and Toshiba specifications as outlined in datasheets 19/35 Detailed Specifications STV0674 4.5 4.5.1 USB interface AC electrical characteristics of USB transceiver All measurements are fully electrically compliant to Chapter 7 (Electrical requirements) of revision 2 of the USB specification for full-speed devices (V1.1). The transceiver has been tested with external impedance-matching series resistors (27 Ω +/-5%) between the pads and the USB cable. Table 4: AC characteristics of USB transceiver Parameter TRANSMIT /OUTPUT STAGE tlr tlf tlrfm SYSTEM Rpu Rpd USB differential pad Dp, Dn pullup Resistor USB differential pad Dp, Dn pulldown Resistor 1.425 14.25 1.575 15.75 kΩ kΩ fall time rise time rise and fall time matching 4.45 4.55 90 5.82 5.77 7.31 6.81 111 ns ns % Description Min Typ. Max Units 20/35 STV0674 Detailed Specifications 4.6 4.6.1 Audio Audio ADC electrical parameters Table 5: Audio/ADC electrical characteristics Symbol Fclk Dutymclk Fs Vbias Rbias RIN Cin Dyn In SNR* Offset Harma Parameter Clock frequency Clk duty cycle Sample frequency Bias reference voltage Vbias impedance Input impedance Input capacitance Input dynamic range Signal / Noise ratio Offset error Signal to peak harmonics Test conditions Min. Typ. 12 Max. Unit MHz 40 8 Vbias / Vcc = 3V Vbias IN+ / ININ+ / INADC Out Full scale IN+ / IN- Gain 0dB (AGC off) Sinewave @FS - 3dB Gain 0dB After automatic calibration Sinewave @FS - 3dB Gain 0dB Sinewave @FS - 3dB Gain 24dB 75 50 40 1.5 5 50 10 1.5 82 60 48 % kHz V kΩ kΩ pF Vpp dB 100 LSB dB dB LSBpp PSRR Power supply rejection Measured on ADC output with a 1kHz 100mVpp sinewave added to the 3.3V supply Gain 0dB ADC out 0.45 LFc HFc Low cut-off frequency High cut-off frequency 15 Hz Fs a. Input sine wave 1kHz, Fmclk 11.289 MHz, BW = 10Hz-20 kHz, A-weighting filters, output 16 bits RAW PCM 4.6.2 Audio anti-aliasing filter characteristics Table 6: Audio anti-aliasing filter characteristics Symbol Fpassband Ripplepass Fstopband Parameter Passband frequency Passband ripple 0->0.376Fs Stopband frequency Test conditions Fs is sampling frequency Min. 0.45 -0.25 Typ. Max. Unit Fs 0.25 0.6 dB Fs Fs is sampling frequency 21/35 Detailed Specifications STV0674 4.7 SFP AC parameters Each SFP is a TTL schmitt trigger bidirectional pad Buffer, 3v3 capable with 2mA drive capability and Slew-rate Control. The 3.3V IOs comply to the EIA/JEDEC standard JESD8-B. For sake of convenience the most important parameters for measurement have been extracted and presented below. Table 7: SFP AC parameters Symbol Slew_rise Description 0.3Vcc to 0.6Vcc, CL = 10pF, balanced RL = 1KR to Vdd with RL = 1KR to Vss 0.3Vcc to 0.6Vcc, CL = 10pF, balanced RL = 1KR to Vdd with RL = 1KR to Vss Min. 1.63 Typ. 1.83 Max. 1.97 Unit V/ns Slew_fall 2.05 2.32 2.62 V/ns 4.8 Sensor interface Figure 12: Sensor interface timing tCK sensor_clk tCL tCH sensor_db[4:0] tAC tDH tDS Table 8: Sensor interface timing Symbol tCK tCH tCL tDS tDH tAC Min. 0.1875 40.02 40.02 7.71 0 Typ. Max. 24 Unit MHz tCK tCK ns ns 32.39 ns Note: 1 The above timings assume that the sensor_clk load is 20pF. 2 The sensor data setup and hold times are requirements of the STV0674. 3 tAC represents the maximum allowed clock to data delay from STV0674 sensor_clk pad to the STV0674 sensor data pads. (i.e. STV0674 pad to sensor PCB delay + sensor clock to data delay + sensor data pad to STV0674 pad PCB delay). 22/35 STV0674 Detailed Specifications 4.9 Device current consumption in run and suspend modes The STV0674 power consumption has been estimated based on a webcam configuration. In this way, the analysis can specifically consider the device’s intrinsic power consumption rather than that associated with other system-level components. As STV0674 typically ends up in very low USB or battery powered applications, it is important device power consumption is measured in three different operating modes representing typical operating conditions in the real application. These three modes shall be referred to as low power mode, high power mode and suspend mode. Suspend mode is the is the lowest power mode of the device. For the core current, it can be effectively equated to ‘static’ power consumption. In this mode, all embedded clocks are stopped and all embedded logic blocks, macros, IP, etc. are reset into their low power modes. The XTAL oscillator pads (providing main clock source to entire STV0674) are also stopped. The name ‘Suspend’ mode historically comes from the device’s requirement to comply with USB ‘suspend’ mode where the total current drawn from the host PC by the USB peripheral is not allowed to exceed 500 µA. In low power mode, the embedded VP and VC module clocks are disabled and held in reset. The VP and VC are the two most power-hungry modules in the STV0674. A limited number of modules are enabled in this mode to allow USB enumeration, system-level self-configuration or camera userinterface functions. Such modules include the embedded microcontroller, USB core, memory subsystems and SFP core. In high power mode. The VP and VC module clocks is enabled and are brought out of reset. This is more typical of the real device application in that video data is being generated and processed. In measured cases the VP and VC are set up to their fastest (worst-case power) modes of operation processing VGA source data from the sensor at full 30 frames-per-second. Note: The baseline device power model presented here can be extended to cover other system-level configurations. In such cases the core IDD will remain as measured here (30fps/VGA) but the i/o IDD is more likely to vary depending for example on which memory type (sdram/nand) is being used. The power associated with each pin can be calculated based on its frequency (MHz), capacitive (C) and resistive (R) loading. 23/35 Pinout and Pin Description STV0674 5 5.1 Pinout and Pin Description Device pinout Figure 13: STV0674 pinout in 100TQFP 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 SFP30 SFP31 SFP2 SFP3 VDDC_2 VSS_2 SFP10 VDDI_2 VSS_3 SFP4 SFP5 SFP33 SFP32 SFP11 SFP12 SFP6 SFP7 SFP8 SFP34 SFP35 SFP36 SFP37 SFP38 SFP1 SFP9 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 SFP29 SFP28 SFP27 SFP26 SFP25 SFP0 VSS_1 VDDI_1 SCLK SDATA4 SDATA3 SDATA2 SDATA1 SDATA0 SSDA SSCL VDDA AP CBS AN VSSA SFP60 SFP59 SFP58 SFP57 VDDC_1 VDDI_4 SFP54 XTALO VSS_7 VSS_6 SFP24 SFP56 SFP55 SFP53 SFP52 SFP23 SFP22 SFP21 SFP51 SFP50 SFP49 SFP48 SFP39 SFP40 SFP41 SFP42 SFP43 SFP13 SFP14 VDDC_3 VSS_4 SFP15 SFP16 SFP17 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 STV0674-100TQFP (14x14) SFP18 SFP19 VDDI_3 DP/RXD DN VSS_5 RESET SFP20 WAKEUP SFP44 SFP45 SFP46 SFP47 VDDP VSSP 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 24/35 XTALI TM0 TM2 TM1 VC STV0674 Pinout and Pin Description Figure 14: Signals identified by functional group STV0674 VDDC VDDI VDDP VDDA 7 3 4 Power inputs Core I/O PLL Audio Grounds Common PLL Audio Audio PLL and clock XTLI XTLO VC VSS VSSP VSSA AP AN CBS 3 Test TM RESET SCLK SSDA SSCL SDATA 5 Interrupt/control Sensor interface WAKEUP DP DN USB interface Special Function Pins 61 SFP 25/35 Pinout and Pin Description STV0674 5.2 Pin description Table 9: 100TQFP pin description Pin CLOCKS AND RESETS 40, 41 57 XTLI, XTLO RESET OSC IS Crystal oscillator pad pair, see Figure 16 Reset input (Schmitt input level, active low) Pin name Type Description POWER SUPPLIES 31, 94, 68 8, 82, 61, 42 7, 93, 81, 67, 58, 43, 32 VDDC_1, VDDC_2, VDDC_3 VDDI_1, VDDI_2,VDDI_3, VDDI4 VSS_1, VSS_2, VSS_3, VSS_4, VSS_5, VSS_6, VSS_7 PWR PWR GND Core power supply - 1V8 I/O power supply - 3v3 Common ground. PLL POWER AND FILTER PINS 37 38 35 VDDP VSSP VC PWR GND ANA Master and audio PLL supplies - 1V8 Master and audio PLL supplies - 0V Audio PLL filter, see Figure 17 AUDIO FRONT-END (ADC) POWER 17 21 VDDA VSSA PWR GND Audio front end supply - 3v3 Audio front-end supply - 0v SENSOR INTERFACE 9 10, 11, 12, 13, 14 15 16 SCLK SDATA[4:0] O I Camera clock (2mA CMOS) 5-bit sensor video data SSDA SSCL I/O O Sensor I2C data (Schmitt input level) Sensor I2C clock USB INTERFACES 60 59 DP DN I/O I/O USB differential D+ USB differential D- TEST PINS 39, 36, 34 TM[2:0] I Test mode pins - Must be pulled high USER BUTTON INPUTS/WAKEUP 55 WAKEUP I Could be used as “wake-up” button on SDRAM camera while untethered. 26/35 STV0674 Table 9: 100TQFP pin description Pin Pin name Type Pinout and Pin Description Description AUDIO FRONT-END INPUT, AND BIAS PINS 18 20 19 AP AN CBS ANA ANA ANA VIN+ VINVBIAS, see Figure 17 SPECIAL FUNCTION PINS 87, 88, 89, 90, 91, 92, 95,6 66, 69, 70, 80, 83, 84, 85,86 44, 45, 46, 56, 62, 63, 64, 65 99, 100, 1, 2, 3, 4, 5, 33 75, 76, 77, 78,79, 96, 97, 98 51, 52, 53, 54, 71, 72, 73, 74 27, 28, 29, 30, 47, 48, 49, 50 22, 23, 24, 25, 26, SFP[7:0] SFP Special function pin operation is firmware specific. Special function pin operation is firmware specific. Special function pin operation is firmware specific. Special function pin operation is firmware specific. Special function pin operation is firmware specific. Special function pin operation is firmware specific. Special function pin operation is firmware specific Special function pin operation is firmware specific. SFP[15:8] SFP SFP[23:16] SFP SFP[31:24] SFP[39:32] SFP SFP SFP[47:40] SFP SFP[55:48] SFP SFP[60:56] SFP 27/35 Pinout and Pin Description Table 10: Hardware specific - Special function pins SPECIAL FUNCTION PINSa Pin 6 95 92 91 90 89 88 87 86 85 84 83 80 70 69 66 65 64 63 62 56 46 45 44 33 5 4 3 2 1 100 99 STV0674 Pin Name SFP[0] SFP[1] SFP[2] SFP[3] SFP[4] SFP[5] SFP[6] SFP[7] SFP[8] SFP[9] SFP[10] SFP[11] SFP[12] SFP[13] SFP[14] SFP[15] SFP[16] SFP[17] SFP[18] SFP[19] SFP[20] SFP[21] SFP[22] SFP[23] SFP[24] SFP[25] SFP[26] SFP[27] SFP[28] SFP[29] SFP[30] SFP[31] SDRAM x8 SDRAM x16 FLASH Other PWM0/ TQFP_SEL Description Audio Playback output b GPIO GPIO CS_NAND NAND/SMC detectc GPIO GPIO GPIO GPIO GPIO SHUTTER GPIOd GPIO GPIO GPIO GPIO POWER_ON Output reserved for power latchinge GPIO CS_SMC Chip select for SMCf GPIO GPIO GPIO GPIO GPIO DQ1 DQ3 DQ5 DQ7 DQ8 DQ10 DQ12 DQ14 DQML IO0 IO1 IO2 IO3 IO4 IO5 IO6 GPIO /SDRAMx16 GPIO /SDRAMx16 GPIO /NAND FLASH /SDRAMx16 GPIO /NAND FLASH /SDRAMx16 GPIO /NAND FLASH /SDRAMx16 GPIO /NAND FLASH /SDRAMx16 GPIO /NAND FLASH /SDRAMx16 GPIO /NAND FLASH /SDRAMx16 GPIO /NAND FLASH /SDRAMx16 28/35 STV0674 Pinout and Pin Description Table 10: Hardware specific - Special function pins SPECIAL FUNCTION PINSa Pin 98 97 96 79 78 77 76 Pin Name SFP[32] SFP[33] SFP[34] SFP[35] SFP[36] SFP[37] SFP[38] SDRAM x8 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 SDRAM x16 DQ0 DQ2 DQ4 DQ6 DQ9 DQ11 DQ13 FLASH IO7 Other Description GPIO /NAND FLASH /SDRAMx16 / SDRAMx8 GPIO /SDRAMx16 /SDRAMx8 GPIO /SDRAMx16 /SDRAMx8 WE ALE CLE RB GPIO /NAND FLASH /SDRAMx16 / SDRAMx8 GPIO /NAND FLASH /SDRAMx16 / SDRAMx8 GPIO /NAND FLASH /SDRAMx16 / SDRAMx8 GPIO /NAND FLASH /SDRAMx16 / SDRAMx8 (open drain)g 75 74 73 72 71 54 53 52 51 50 49 48 47 30 29 28 27 26 25 24 23 22 SFP[39] SFP[40] SFP[41] SFP[42] SFP[43] SFP[44] SFP[45] SFP[46] SFP[47] SFP[48] SFP[49] SFP[50] SFP[51] SFP[52] SFP[53] SFP[54] SFP[55] SFP[56] SFP[57] SFP[58] SFP[59] SFP[60] DQ7 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 CLK CKE DQM RAS CAS WE CS DQ15 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 CLK CKE DQMH RAS CAS WE CS RE GPIO /NAND FLASH /SDRAMx16 / SDRAMx8 GPIO /SDRAMx16 /SDRAMx8 GPIO /SDRAMx16 /SDRAMx8 GPIO /SDRAMx16 /SDRAMx8 GPIO /SDRAMx16 /SDRAMx8 GPIO /SDRAMx16 /SDRAMx8 GPIO /SDRAMx16 /SDRAMx8 GPIO /SDRAMx16 /SDRAMx8 GPIO /SDRAMx16 /SDRAMx8 GPIO /SDRAMx16 /SDRAMx8 GPIO /SDRAMx16 /SDRAMx8 GPIO /SDRAMx16 /SDRAMx8 GPIO /SDRAMx16 /SDRAMx8 GPIO /SDRAMx16 /SDRAMx8 GPIO /SDRAMx16 /SDRAMx8 GPIO /SDRAMx16 /SDRAMx8 GPIO /SDRAMx16 /SDRAMx8 GPIO /SDRAMx16 /SDRAMx8 GPIO /SDRAMx16 /SDRAMx8 GPIO /SDRAMx16 /SDRAMx8 GPIO /SDRAMx16 /SDRAMx8 SDRAM detect and Chip Select for SDRAMh 29/35 Pinout and Pin Description STV0674 a. SFP 0-22 default to inputs on reset and in low power states. SFP 0-22 should therefore not be left floating and must be configured by external circuit. See Section 5.2.1 for state of SFP 23-60 b. Pull Up required. See Section 5.2.1. c. SFP 3> Pull Up if NAND or SMC present /Down if not, See Section 5.2.1. d. SFP 9> Pull down required if pin not used, must be held low at power on. e. SFP 14> Pull down required for power latching otherwise pull up required. f. SFP 16> Pull Up required, if SMC present. (SFP 3 must also be pulled up) g. SFP 38> Pull resistor required if NAND present, value 10kΩ. h. SFP 60> Pull Up if SDRAM present /Down if not, See Section 5.2.1 5.2.1 Power on/ low power default pin states The initial state of SFP pins varies depending on the power on state of the NAND flash / SMC detect pin, SDRAM detect pin and package detect pin. The default pin states are detailed in Table 11. Table 11: Power-on/low-power default pin states Pin state at power on TQFP_SEL CS_NAND CS_SDRAM Flash Port SFP 25-32, 35-39 Initial state Non-Flash SDRAM SFP 23, 24, 33, 34, 40-60 Reserved Ouput Output Input Input Output Input Input Input Input GPIO SFP0 0 1 1 1 SFP3 X 1 X 0 SFP60 X 0 1 0 SFP0-22 30/35 STV0674 Pinout and Pin Description 5.3 Package outline and mechanical data Figure 15: 100TQFP package outline and mechanical data mm MIN. A A1 A2 B C D D1 D3 e E E1 E3 L L1 K 0.45 0.05 1.35 0.17 0.09 16.00 14.00 12.00 0.50 16.00 14.00 12.00 0.60 1.00 0.75 0.018 1.40 0.22 TYP. MAX. 1.60 0.15 1.45 0.27 0.20 0.002 0.053 0.007 0.003 0.630 0.551 0.472 0.019 0.630 0.551 0.472 0.024 0.0393 3.5°(min.), 7°(max.) 0.030 0.055 0.009 MIN. inch TYP. MAX. 0.063 0.006 0.057 0.011 0.008 DIM. OUTLINE AND MECHANICAL DATA ® TQFP100 D D1 D3 A A2 A1 75 76 51 50 0.076mm .003 inch Seating Plane e E3 E1 E B PIN 1 IDENTIFICATION 100 1 25 26 K TQFP100M C L L1 October 1997 0086901 31/35 Pinout and Pin Description STV0674 5.4 5.4.1 External circuits Crystal oscillator There are 2 crystal oscillator pins XTAL_IN, XTAL_OUT, as shown in Figure 16. The oscillator cell architecture is a single stage oscillator with an inverter working as an amplifier. The oscillator stage is biased by an internal resistor (>1MΩ). It also requires an external PI network consisting of a crystal and two capacitors. Note: The clock accuracy of the oscillator circuit must be within the USB compliance data signaling rate tolerance of 12.000Mb/s ± 0.25%. Figure 16: Oscillator support circuit XTALI XTALO Crystal 15pF 15pF 5.4.2 Audio Figure 17: Audio PLL filter and CBS VC CBS 10K 680 pF 10nF + - 10µF If the record audio section of the STV0674 is not required, AP, CBS, VC and AN can be left unconnected. VDDA must however be connected to a 3V3 supply. 5.4.3 Recommended power supply decoupling A 0.1µF bypass capacitor located as close as possible to the chip package connecting between all VDD pins and GND and at least one bulk decoupling capacitor on each of the supply rails VDDA, VDDC, VDDI and VDDP. 32/35 STV0674 Evaluation Kit and Reference Design Manuals 6 6.1 Evaluation Kit and Reference Design Manuals Evaluation kit STMicroelectronics recommends the use of their evaluation kit (EVK) for initial evaluation and design-in. The kit contains all the hardware functionality required to implement a webcam, dual mode and tri mode camera and is populated with SDRAM, NAND FLASH as well as a Smartmedia connector. The EVK content is the following: q q q q STV0674 Evaluation board with both CIF and VGA sensor plug-in USB cable PC software User manual 6.2 Reference design manuals The STMicroelectronics STV0674 reference design manuals include complete schematics, BOM and design recommendations. For products based on the STV0674, STMicroelectronics recommends that all designers refer to the reference design manuals before starting a new design. Please contact STMicroelectronics for more details. 33/35 Ordering Details STV0674 7 Ordering Details Table 12 : Ordering details Part number Device STV0674T100 Digital video co-processor (100TQFP package) Description Evaluation Kit (EVK) STV-674/100T-E01 100TQFP STV0674 + CIF and VGA sensors Technical support Technical support information, such as datasheets, software downloads, etc. can be found at http://www.st.com under “Imaging Products”. 34/35 STV0674 Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics © 2003 STMicroelectronics - All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - China - Finland - France - Germany - Hong Kong - India - Italy - Japan Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - U.S.A. www.st.com 35/35