STV0684

STV0684 Digital Camera Processor PRODUCT PREVIEW Features ■ Supports the VC6700 CMOS sensor (UXGA, 1600 x 1200 pixels) from STMicroelectronics ■ High quality video processor ● ● ● ● ● ● ● ■ Versatile mass storage interface ● Support Compact-flash, Nand-on-board, Smartmedia, Secure Digital and Multi-Media USB audio and video class compliant USB mass storage class compliant, Bulk only transfer protocol ■ USB 2.0 full speed device ● ● RAM based firmware Pixel defect correction NORA (Noise Reduction Algorithm Anti-vignetting algorithm Advanced statistics processor Two general purpose scalers Dual video interface for concurrent viewfinder and movie capture Instruction, data cache and embedded memory for fast code execution Embedded ROM bootloader for code storage in cost effective NAND flash memory Code executed in SDRAM, no code-size limitation ■ JPEG and MJPEG CODEC Description The STV0684 processor is targeted for use in CMOS digital still cameras. ST supplies complete camera reference designs which include sensor, co-processor, firmware and software drivers. The STV0684 uses a small BGA package (12 mm x 12 mm) ideal for the design of very small digital cameras. The STV0684 incorporates ST’s unique and highly performing video processor algorithms including newly improved and patented algorithms (e.g. NORA and Anti-vignetting). The CMOS sensors from STMicroelectronics use pinned photodiodes manufactured in a high performance process resulting in improved low light performance, reducing the gap with CCD sensors. ■ ST20 32-bit core ● ● ● ■ AVI (Audio Video Interleave) clips directly recorded into the mass storage media ● ● Long clip length Low power consumption Applications ● ● ● ■ Flexible TFT, D-TFD digital interface for preview (while recording) and review ● Digital still cameras Solid state video camera recorders Embedded cameras Direct support for Casio, Epson and AU optronics displays Flexible digital interface designed to support future digital panels ● Ordering Information Part Number STV0684 ■ PAL and NTSC encoder with on-chip digital to analog converter ● Temperature [0; +70 ] °C Package BGA196 TV display of pictures and movie clips ■ On-chip 16-bit Sigma-Delta analog to digital converter for audio record ■ Audio digital to analog converter for audio playback Rev. 1 March 2005 This is preliminary information on a new product now in development. Details are subject to change without notice. 1/49 STV0684 Technical Specifications Resolution Sample rate Power supply Power requirements Package UXGA - VC6700V048 up to 48 M sample/s (MSPS) 3.3V and 1.8V mA typical BGA196, 12x12 mm System Overview Figure 1: STV0684 system overview VP SCALER 1 SCALER 2 CODEC ST20 CORE USB Interface Audio Interface STV0684 Boot HW ECC NAND interface TV interface LCD controller DRAM Interface NAND SDRAM 2/49 STV0684 Table of Contents Chapter 1 Chapter 2 Chapter 3 3.1 3.2 3.3 3.4 3.5 3.6 3.6.1 3.6.2 Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 Video processor (VP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 ST20-C103 core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 SFP module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 USB interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Memory interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Audio interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Audio record . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Audio playback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.7 3.8 3.9 3.10 3.10.1 3.10.2 3.10.3 TV interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 LCD controller - Display interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 JPEG CODEC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Other interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 I2C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Comparator for low battery detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Chapter 4 4.1 4.2 4.3 4.4 4.5 4.5.1 4.5.2 4.5.3 4.5.4 4.5.5 4.5.6 4.5.7 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 DC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 AC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 SFP AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Audio ADC electrical parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 AC electrical characteristics of USB transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 SDRAM timing description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 I2C timing description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 SPI timing description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 NAND timing description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 3/49 STV0684 4.5.8 4.5.9 4.5.10 4.5.11 4.5.12 AC characteristics for NAND flash operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Compact flash timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 TFT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 TV . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Sensor interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 4.6 4.7 4.7.1 4.7.2 4.7.3 ESD handling characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 External circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Crystal oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Audio . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Recommended power supply decoupling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Chapter 5 5.1 5.2 Package Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45 STV0684 pin assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 STV0684 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 4/49 STV0684 Functional Block Diagram 1 Functional Block Diagram Figure 2: STV0684 functional block diagram DMA FIFO DMA RAM I2C CF SPI FLASH ILC sdram (external) sensor VP JPEG ENCODE T1 VDFIF JPEG DECODE T2 ST20 core Boot ROM LCDC LCD Dot selector TVC TV DMA DMA FIFO RAM Audio fifo PWM fifo USBIFO ISO ISO BLKOUT BLKIN ADC AUDIO AUDIO usb NAND CF I2C SPI 5/49 Signal Description STV0684 2 Signal Description Figure 3: Signals identified by functional group STV0684 VDDC VDDI VDDP VDDA VDDAP TV_VDDA 5 10 Power Inputs: Core I/O Master PLL Audio Audio PLL TV Grounds: Common Master PLL Audio Audio PLL TV Low Battery SCLK SPCLK SSDA SSCL 133 Special Function Pins (SFP) HSYNC VSYNC SDATA[9:0] Graphics display CF/ NAND/ SMC Audio output/ PIEZO Sensor interface 10 17 Graphics display E-Warp debug 4 E-Warp debugger ST Micro connect Debug SDRAM 2 ST Micro connect Sensor interface ST Micro connect Debug 5 TV Interface Interrupt/ Control USB Interface PLL and Clock: Audio XTLI XTLO VC AP AN CBS RESET WAKEUP DP DN USB_DET CVBS TV_REXT TV_GNDA_REXT VREF LOW_BATT ST Micro connect VSS VSSP VSSA VSSAP TV_VSSA 15 38 SDRAM 28 CF/NAND/SMC interface SPI PWM output Other 5 SPI 20 User interface/Power Management 6/49 STV0684 Table 1: STV0684 signal description1 Pin name Location Type SFP number Signal Description Description Power supplies: total 38 pins VDDI1 VDDI2 VDDI3 VDDI4 VDDI5 VDDI6 VDDI7 VDDI8 VDDI9 VDDI10 VDDC1 VDDC2 VDDC3 VDDC4 VDDC5 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VDDP VSSP TV_VDDA L12 G13 F10 F7 F4 K3 N3 P5 N6 K8 G8 C7 F2 M5 M11 L13 H8 F14 E13 B7 A7 F6 G6 K4 P2 P4 M6 M7 P8 N11 D8 E8 A12 S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S VDD IO Supply 3.3V VDD IO Supply 3.3V VDD IO Supply 3.3V VDD IO Supply 3.3V VDD IO Supply 3.3V VDD IO Supply 3.3V VDD IO Supply 3.3V VDD IO Supply 3.3V VDD IO Supply 3.3V VDD IO Supply 3.3V VDD CORE supply 1.8V VDD CORE supply 1.8V VDD CORE supply 1.8V VDD CORE supply 1.8V VDD CORE supply 1.8V GROUND GROUND GROUND GROUND GROUND GROUND GROUND GROUND GROUND GROUND GROUND GROUND GROUND GROUND GROUND PLL core supply 3.3V PLL core GND TV core supply 3.3V 7/49 Signal Description Table 1: STV0684 signal description1 Pin name TV_VSSA VDDA VSSA VDDAP VSSAP STV0684 Location B12 C10 B11 B14 C13 Type S S S S S SFP number TV core GND Description Audio analog power supply 3.3V Audio analog ground Audio PLL supply 1.8V Audio PLL ground Sensor interface: total 16 pins of which 12 are SFPs SDATA0 SDATA1 SDATA2 SDATA3 SDATA4 SDATA5 SDATA6 SDATA7 SDATA8 SDATA9 HSYNC VSYNC SCLK SPCLK SSDA SSCL N8 M9 J8 L9 P9 N9 K9 P10 L10 N10 M10 P11 N12 P14 P12 P13 I I I I I I I I I I I I O I I/O I/O SFP80 SFP81 SFP82 SFP83 SFP84 SPF85 SFP86 SFP87 SFP88 SFP89 SFP90 SFP91 Sensor interface Bit0 Sensor interface Bit1 Sensor interface Bit2 Sensor interface Bit3 Sensor interface Bit4 Sensor interface Bit5 Sensor interface Bit6 Sensor interface Bit7 Sensor interface Bit8 Sensor interface Bit9 Horizontal synchronization Vertical Synchronization Clock supplied to the sensor Data qualifying clock from the sensor I2C Data line I2C clock line SDRAM interface: total 38 pins all of which are SFPs DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 L14 N13 J9 N14 J10 M12 K13 L11 K10 J11 M13 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O SFP101 SFP92 SFP102 SFP93 SFP103 SFP94 SFP104 SFP95 SFP96 SFP105 SFP97 SDRAM SDRAM SDRAM SDRAM SDRAM SDRAM SDRAM SDRAM SDRAM SDRAM SDRAM 8/49 STV0684 Table 1: STV0684 signal description1 Pin name DQ11 DQ12 DQ13 DQ14 DQ15 DQML A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 BA0 BA1 CLK CKE DQMH RAS CAS WE Signal Description Location J12 M14 J13 K11 K14 K12 H10 J14 H11 H12 H9 H14 H13 G10 G14 G11 G12 G9 F13 E14 F12 F11 D14 E12 D13 E11 D12 Type I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O SFP number SFP106 SFP98 SFP107 SFP99 SFP108 SFP100 SFP109 SFP110 SFP111 SFP112 SFP113 SFP114 SFP115 SFP116 SFP117 SFP118 SFP119 SFP120 SFP121 SFP122 SFP123 SFP124 SFP125 SFP126 SFP127 SFP128 SFP129 SDRAM SDRAM SDRAM SDRAM SDRAM SDRAM SDRAM SDRAM SDRAM SDRAM SDRAM SDRAM SDRAM SDRAM SDRAM SDRAM SDRAM SDRAM SDRAM SDRAM SDRAM SDRAM SDRAM SDRAM SDRAM SDRAM SDRAM Description 9/49 Signal Description Table 1: STV0684 signal description1 Pin name Location Type SFP number Description STV0684 Graphics LCD interface: total 18 pins of which all are SFPs L_LP L_RES L_XINH L_XSCL L_FRYP L_FRYS L_DY / PNL_CLK L_YSCL / HSYNC L_YSCLD / VSYNC L_DOUT0 L_DOUT1 L_DOUT2 L_DOUT3 L_DOUT4 L_DOUT5 L_FRX / Data6 L_GCP / Data7 BACKLIGHT TV interface: total 3 pins CVBS TV_REXT TV_GNDA_REXT C12 B13 A13 ANA ANA ANA CVBS out TV Reference voltage TV Reference voltage L5 M4 N4 P3 N5 L6 K6 J6 P6 H7 P7 K7 J7 L7 N7 M8 L8 B6 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O SFP63 SFP64 SFP65 SFP66 SFP67 SFP68 SFP69 SFP70 SFP71 SFP72 SFP73 SFP74 SFP75 SFP76 SFP77 SFP78 SFP79 SFP13 LCD interface LCD interface LCD interface LCD interface LCD interface LCD interface LCD interface LCD interface LCD interface LCD interface LCD interface LCD interface LCD interface LCD interface LCD interface LCD interface LCD interface LCD interface / GPIO SPI (used for MMC, SD): total 5 pins all of which are SFPs SPI_MISO SPI_MOSI SPI_SLK SPI_SS SPI CS B10 F9 D9 B9 E9 I/O I/O I/O I/O I/O SFP1 SFP2 SFP3 SFP4 SFP5 Master In Slave Out Master Out Slave In SPI clock SPI slave/host selection SPI Chip select 10/49 STV0684 Table 1: STV0684 signal description1 Pin name Location Type SFP number Signal Description Description Audio interface: total 6 pins of which 2 are sfps CBS AP AN VC PWM OUT ENABLE C11 A11 D10 C14 E10 C6 ANA ANA ANA ANA I/O I/O SFP0 SFP17 Audio Vbias Audio ADC Differential input Audio ADC differential input Audio PLL filter DAC: Pulse Width Modulator output ENABLE external audio amplifier NAND (Smartmedia) & Compact-flash interface: total 29 pins all of which are SFPs IO0 IO1 IO2 IO3 IO4 IO5 IO6 IO7 NAND CS WE ALE OE CLE RDY RB WAIT RE REG CS CARD EN WRIT_PROT CARD DET1 CARD_DET CARD DET2 CFA0 CFA1 CFA2 CFA3 CFA4 CFA5 CFA6 CFA7 K2 L1 L2 L3 M1 M2 N1 N2 I/O I/O I/O I/O I/O I/O I/O I/O SFP52 SFP53 SFP54 SFP55 SFP56 SFP57 SFP58 SFP59 CF A00 CF A01 CF A02 CF A03 CF AO4 CF A05 CF A06 CF A07 K5 I/O SFP51 SMC CD - CF CD1 E4 E3 D1 E2 E1 F5 F3 G3 F1 G7 G2 J1 J4 J2 J5 K1 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O SFP35 SFP36 SFP37 SFP38 SFP39 SFP40 SFP41 SFP42 SFP43 SFP44 SFP45 SFP46 SFP47 SFP48 SFP49 SFP50 SMC D0 - CF D00 SMC D1 - CF D01 SMC D2 - CF D02 SMC D3 - CF D03 SMC D4 - CF D04 SMC D5 - CF DO5 SMC D6 - CF DO6 SMC D7 - CF DO7 Nand Chip select SMC WE - CF WE SMC ALE - CF OE SMC CLE - CF READY SMC R/-B - CF WAIT SMC RE - CF REG SMC CS - CF CE1 SMC WP - CF WP 11/49 Signal Description Table 1: STV0684 signal description1 Pin name CFA8 CFA9 CFA10 STV0684 Location M3 P1 L4 Type I/O I/O I/O SFP number SFP60 SFP61 SFP62 CF A08 CF AO9 CF A10 Description User Interface - (Application specific SFP): total 16 pins all of which are SFPs MODE UP MODE DOWN SELECT CANCEL SHUTTER LED0 LED1 FLASH RDY FLASH TRIGGER POWER OFF POWER DOWN SNAP SHUTTER_CNTL1 SHUTTER_CNTL2 SHUTTER_CNTL3 SUSPEND F8 A10 C9 A9 D7 A5 B5 B8 E5 E7 A6 B4 D5 A4 C5 E6 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O SFP6 SFP7 SFP8 SFP9 SFP12 SFP18 SFP19 SFP10 SFP20 SFP11 SFP14 SFP24 SFP21 SFP22 SFP23 SFP15 see firmware manual see firmware manual see firmware manual see firmware manual see firmware manual see firmware manual see firmware manual see firmware manual see firmware manual see firmware manual see firmware manual Sensor interface mechanical shutter interface mechanical shutter interface mechanical shutter interface Sensor suspend pin General Purpose Input/Output: total 11 pins all of which are SFPs GPIO0 GPIO1 GPIO2 GPIO3 GPIO4 GPIO5 GPIO6 GPIO7 GPIO8 GPIO9 GPIO10 B3 A2 C3 B2 A1 B1 C2 D3 C4 A3 D4 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O SFP28 SFP29 SFP30 SFP31 SFP32 SFP33 SFP34 SFP130 SFP25 SFP26 SFP27 General purpose IO General purpose IO General purpose IO / JTAG TRIG EWARP General purpose IO / JTAG TDI EWARP General purpose IO / JTAG TDO EWARP General purpose IO / JTAG TMS EWARP General purpose IO / JTAG TCK EWARP General purpose IO General purpose IO General purpose IO General purpose IO 12/49 STV0684 Table 1: STV0684 signal description1 Pin name Location Type SFP number Signal Description Description USB interface: total 4 pins of which 1 is a SFP DP DN DETECT USB TX_EN G4 G5 G1 D6 I/O I/O I/O I/O SFP16 USB DATAP USB DATAN High when USB VCC present Battery level detector: total 2 pins LOW_BATT VREF A14 D11 ANA ANA Battery level input Reference for the battery voltage CLOCK, Reset, system signals: total 4 pins Xtal in Xtal out RESET WAKE_UP C8 A8 C1 D2 ANA ANA I I/O 27 Mhz Crystal input 27 MHz Crystal Output RESET INPUT Debug and test interface: total 7 pins of which 2 are SFPs UP_TRIGI UP_TRIGO UP_TDI UP_TDO UP_TMS UP_TCK UP_RST H5 H4 H1 H2 J3 H6 H3 I/O I/O I O I I I SFP131 SFP132 ST20 microconnect debug interface ST20 microconnect debug interface ST20 microconnect debug interface ST20 microconnect debug interface ST20 microconnect debug interface ST20 microconnect debug interface ST20 microconnect debug interface 1. This is preliminary information that may be subject to change 13/49 Functional Description STV0684 3 3.1 Functional Description Video processor (VP) The VP is the result of STMicroelectronics extensive know-how and hard work around the colour science for CMOS sensor. The VP block fulfills many functions related to colour reconstruction from a bayer filter, colour matrixing and sharpening, real-time and programmable defect pixel correction, AGC, AWB, Anti flicker and Gamma correction, scaling from the sensor to the required video and LCD panel resolution. This new video processor benefits from STMicroelectronics latest algorithms development such as the patented Noise Reduction Algorithm and anti-vignetting that ensures the highest quality standard. The VP combines hardware and firmware. The main block controller is powered by a 8051 E WARP microcontroller, with RAM based firmware for the highest level of flexibility. Feature list System features ● ● ● ● ● ● RAM based firmware Dual video interface for simultaneous ViewFinder and movie capture Bayer or YCbCr input from supported memory 48Mpixel/s capable processing pipe Flashgun and shutter support RGB/YUV 4:2:2 output formats Image reconstruction functions ● ● ● ● ● ● ● ● ● ● ● ● x2, x2.5 Horizontal downscaling Colour Channel Gains and Offsets Anti-vignetting Defect correction NoRA - Active Noise Reduction Demosaic (bayer->rgb conv) YUV matrix (rgb -> YUV) Image crop General purpose RGB downscaler RGB matrix Peaking Gamma correction Statistics processor ● ● 4 Accumulators - programmable on the fly Programmable zones 14/49 STV0684 Image control functions (Tasks handled by the EWARP processor) ● ● ● ● ● ● ● ● ● Functional Description Sensor detection, initialisation and configuration VP mode management: stills, streaming etc. Automatic Exposure Control, Automatic White balance Flicker correction Dampening/Promotion Tasks Scaler Management Dark Calibration Flashgun control Shutter control 3.2 ST20-C103 core The ST20 core is the heart of the STV0684 system-on-chip. The processor can execute its code from either the 64KB of private SRAM or directly from the external SDRAM. Instruction/Data cache ensure a fast code execution. A boot loader residing in a ROM of the device provides capability to boot the system by copying the application firmware image from Non Volatile Memory (SPI Flash or Standard NAND Flash) to the program SRAM or SDRAM memory. This mechanism ensures the lowest system cost by storing the application firmware on a cheap mass storage memory and thus avoiding the extra cost of a NOR type memory. The boot loader also provides the useful possibility to upgrade the Application Firmware and therefore program cameras on the factory line. The ST20-C103 core includes the following: ● ● ● ● ● ST20C1 processor running at 48 MHz frequency diagnostic control unit DCU3 (4 compare, 4 capture, trace) for debug and code development PWM4 timer, INTC2 interrupt controller (16 inputs) 64K local RAM (SRAM) 4K D-cache & 4K I-cache instruction and data caches memory arbiter 15/49 Functional Description Core architecture and block diagram Figure 4: ST20DC3 architecture and block diagram STV0684 ST20-C103 ICache node SDRAM controller ST20-C103 DCache Boot ROM Peripheral 1 reg_dec_1 Peripheral 2 reg_dec_0 Peripheral 10 Peripheral 11 reg_dec_2 ST20-C103 peripheral port Peripheral 10 ST20-C103 Interconnect ST Bus Type 2 domain ST Bus Type 1 domain Peripheral 20 3.3 SFP module The SFP module is based on reconfigurable device pins combined with some local logic to maximize in-system flexibility of the device in any given application An SFP can be configured either to be driven as a GPIO or by the local logic block within the STV0684 (detailed in Figure 3). The functionality and configuration of each SFP is determined and managed under control of the ST20. Control registers local to each module are mapped into the processors address space, this leaves the processor to support more demanding, computational intensive tasks. 16/49 STV0684 Functional Description 3.4 USB interface The USB interface fulfills the three following functions: ● The first function is to download from the camera to the PC all the various objects stored on the mass storage media. The STV0684 uses mass storage class, Bulk Only Transfer to ensure seamless connection with most of the Operating System on the market, including PC and Mac platforms. The second function is to stream concurrent audio and video through isochronous endpoints. Once again, the STV0684 follow established and newly developed standards to ensure the lowest burden of driver development. The STV0684 is USB Audio class and USB video class Compliant. The third function allows the download of the system program code, necessary to run the application, to either serial Flash or NAND flash soldered on the main camera PCB. This function is extremely convenient when programming the cameras on the manufacturing lines and is not open to final users. ● ● Features ● ● ● ● ● ● USB 2.0 Compliant (Full speed device) Full speed (12 Mbps) signalling bit rate USB Audio Class Compliant USB Video Class Compliant USB Mass Storage Compliant, Bulk only Transfer protocol Simultaneously accessible endpoints: ➢ Isochronous endpoint (IN) for video ➢ Isochronous endpoint (IN) for audio ➢ Bulk endpoint (IN) for download ➢ Bulk endpoint (OUT) for download ➢ Interrupt endpoint (IN) ➢ Control pipe 17/49 Functional Description STV0684 3.5 Memory interface Description The memory control Block provides dedicated support for embedded SRAM, external SDRAM, NAND, Smartmedia and Compact Flash (via SFP pins). Embedded SRAM ● ● Full-speed random read/write access from the ST20 to embedded SRAM Full-speed embedded SRAM address generation for real-time data writes from the compression engine, the Video Processor block, SPI, the audio block and the USB module Full-speed embedded SRAM address generation for data reads to the DMA out FIFO ● Selection of the source/destination modules is managed by firmware. External SDRAM ● ● ST20 memory mapped accesses to external SDRAM Full-speed embedded SDRAM address generation for real-time data writes from VDFIF (for VC and VP modules) or DMA out FIFO Full-speed external SDRAM address generation/control to DMA out FIFO, TV FIFO, LCD FIFO or VP FIFO’s Operation with PC100 (or better e.g. PC133) and JEDEC Standard No. 21-C compliant devices and supports 64MB, 128MB, 256MB and 512MB parts with a 16-bit bus width ● ● Mass storage media support ● ● ● Compact-flash support SmartMedia Card support NAND flash memory with a 512B+16 page organization, ECC done by hardware, 32Mbit to 1Gbit devices Support for Multi-Media card and Secure Digital with the SPI interface ● 18/49 STV0684 Functional Description 3.6 Audio interface The STV0684 includes every step of the processing chain required to record, compress, decompress and playback audio. The STV0684 features a high quality 16 bit sigma delta analog to digital converter including automatic level control and noise gating, as well as volume control. It also features an ADPCM CODEC to maximize the length of audio and AVI clips on a given mass storage media. Finally, the product features a digital to analog converter (PWM followed by RC filters) to directly address a speaker or buzzer for audio playback. 3.6.1 Audio record The audio record block consists two main blocks the analogue front end and a 16bit delta-sigma ADC. The front end includes the functions of automatic level control and noise gate, and volume control, the ADC uses sampling frequencies of 8kHz, 11.025kHz, 16kHz, 22.05kHz, 32kHz, 44.1kHz and 48kHz, with either differential or single ended inputs. The sampled output can be 8 or 16 bit. The output of the ACD is then available to the ADPCM module giving an audio compression ratio of 4 to 1. 3.6.2 Audio playback Audio playback is achieved by an internal Pulse Width Modulator with a sample rates of 8kHz, 11.025kHz, 16kHz, 22.05kHz, 32kHz or 44.1kHz, connected to either an external amplifier chip and loudspeaker/ head phone socket, or to a simple piezo buzzer. 3.7 TV interface The TV block is composed of a digital encoder that supports PAL and NTSC and a video digital to analog converter (DAC). This interface supports still and video encoding for display on a TV set. Features ● ● ● ● Supports PAL/NTSC analog TV standards Interlaced input data, YCrCb 4:2:2 format 16bits x 16words FIFO for buffering incoming display data Interrupt generation 19/49 Functional Description STV0684 3.8 LCD controller - Display interface The STV0684 LCD controller has been specifically designed to ensure the two following important characteristics: ● Support of low cost panels with a direct interface to digital LCD panels removing the need for an external timing controller IC Flexibility with a high-level of programmability on all the signals shapes, polarities and frequencies ● The display interface fully supports LCD panel dot selection modes such as Delta, Delta Transverse, Delta Longitudinal and Mosaic and many more by incorporating a dot selector which converts 3dot/pixel input RGB frame data, to 1dot/pixel RGB data. Basic functionality of the system includes still picture review, viewfinder mode as well as viewfinder mode while recording a video clip. Features ● ● ● ● ● ● ● ● ● ● Support Thin Film Transistor (TFT) color displays 64 or 256 grey level, 256k(18bit)or 16.7Million(24bit) color TFT support 6 bit or 8 bit display interfaces 16-deep, 16bit deep FIFO for buffering incoming display data Resolution programmable up to 1024x1024 pixels Programmable timing for different display panels Support CASIO, EPSON, and AU optronics panels Horizontal, Vertical Sync and Pixel clock signals Supports little-endian data formats Interrupt generation 20/49 STV0684 Functional Description 3.9 JPEG CODEC Description The STV0684 features a compression and a decompression engine that is used for both Still pictures and video clips. The hardware CODEC ensures a fast reaction time of the system to encode and decode data. This is particularly important to minimize the shutter to shutter time and the ability to rapidly display images on a local display or the TV set. Compression engine The compression engine uses Baseline Sequential JPEG techniques to compress a digital 656 video stream (at up to 12MPixels/s), down to bandwidth that can be transmitted over the USB interface or to a mass storage media, typically 500-900Kbytes/s. It outputs a JPEG data stream with the headers required by standard decoders. Decompression engine The JPEG decoder block reads the compressed data from the DMA fifo, parses the header and writes back decompressed data back to DMA fifo. This data is organized in 8x8 blocks of the different color components. This data can be converted to raster scan format to be read by the display controller for display on a LCD or TV. 21/49 Functional Description STV0684 3.10 Other interfaces 3.10.1 SPI The SPI interface is a generic serial interface that can be used to perform the following functions: ● ● Support for Multi-media and Secure Digital Cards Support for serial flash where code can be located Full duplex, three-wire synchronous transfers Single, master/slave operation selectable either through firmware or hardware Programmable clock polarity and phase End of transfer interrupt flag Write collision flag Busy flag indication The SPI supports: ● ● ● ● ● ● 3.10.2 I2C The STV0684 features a hardware I2C master interface and supports the following features: ● ● ● ● ● ● ● I2C protocol Standard I2C mode (100 Khz)/Fast I2C mode (400 Khz) Single master mode Transmitter/Receiver performance 7/10 bit addressing DMA mode data transfer Clock stretching 3.10.3 Comparator for low battery detection The comparator circuit was designed to compare the battery voltage (after an external resistor divider) with an external reference voltage and generate a low_batt (high when battery voltage is lower than the present threshold) signal for the CPU core. 22/49 STV0684 Electrical Characteristics 4 4.1 Electrical Characteristics Absolute maximum ratings Table 2: Absolute maximum ratings Symbol VDDC VDDI VDDP VDDA VDDAP VTV_VDDA Supply voltage (core) Supply voltage (IO) Supply voltage (PLL) Supply voltage (Audio) Supply voltage (Audio_PLL) Supply voltage (TV) Current on any signal pin TSTO TOP TLEAD Storage temperature Operating temperature Lead temperature (soldering, 10 s) Parameter Value 2.5 4.0 4.0 4.0 2.5 2.5 2 -50 to 150 0 to 70 +260 Unit V V V V V V mA °C °C °C Caution: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 23/49 Electrical Characteristics STV0684 4.2 Operating conditions Table 3: Operating conditions Symbol VDDC VDDI VDDP VDDA VDDAP VTV_VDDA TA Supply voltage (core) Supply voltage (IO) Supply voltage (PLL) Supply voltage (Audio) Supply voltage (Audio_PLL) Supply voltage (TV) Ambient temperature Parameter Typ. 1.8 3.3 3.3 3.3 1.8 3.3 25 Unit V V V V V V °C 4.3 Thermal data Table 4: Thermal data Symbol Rth(j-a) Parameter Junction-ambient thermal resistance - LFBGA196 (Note 1) Value 50 Unit °C/W Note: 1 Typical, measured with the component mounted on an evaluation PC board in free air. 24/49 STV0684 Electrical Characteristics 4.4 DC electrical characteristics Over operating conditions unless otherwise specified. Values from Table 5 and Table 6 are estimates. Table 5: DC electrical characteristics Symbol VIl VIh Vhys VIL VIH VHYS VT+ VTVT VOL VOH IIL Parameter Input low voltage (XTAL_IN) Input high voltage (XTAL_IN) Hysteresis (XTAL_IN) Input low voltage (SFP pin)1 Input high voltage (SFP pin)1 Schmitt trigger hysteresis (SFP pin)1 Schmitt input low to high threshold voltage (SFP pin)1 Schmitt input high to low threshold voltage (SFP pin)1 Threshold point (SFP pin)1 Output low voltage(SFP pin) Output high voltage(SFP pin) Input leakage current Input pins I/O pins USB differential pad D+/D- input low USB differential pad D+/D- input high (driven) USB differential pad D+/D- input high (floating) USB differential pad D+/D- input sensitivity 2 USB differential pad D+/D- common mode voltage 3 USB differential pad D+/D- output low voltage USB differential pad D+/D- output high voltage USB differential pad D+/D- output signal cross over voltage Driver output resistance 0 2 0 Min Typ Max 0.631 VDDC Unit V V V 1.123 0.492 0.8 VDDI V V V 0.4 2.15 1.05 1.65 0.4 2.4 1 V V V V V µA VILU VIHU VIHUZ VTDI VCM VOLU VOHU VCRS Zdrv 0.8 2.0 2.7 0.2 0.8 0.0 2.8 1.3 28 2.5 0.3 3.6 2.0 44 3.6 V V V V V V V V Ω 1. These figures apply to SFP, SPCLK, SSCL, and SSDA, they do not apply to the XTAL_IN pad 2. VDI = |(D+)- (D-)| 3. Vcm includes VDI range 25/49 Electrical Characteristics Table 6: Power supply specifications Symbol VDDC VDDI VDDP VDDA VDDAP VTV_VDDA ISuspend STV0684 Parameter Supply voltage (core) Supply voltage (IO) Supply voltage (PLL) Supply voltage (Audio) Supply voltage (Audio_PLL) Supply voltage (TV) Core Suspend current IO Suspend current PLL Suspend current Audio Suspend current Audio_PLL Suspend current TV Suspend current Min 1.65 3.0 3.0 3.0 1.65 3.0 Typ 1.8 3.3 3.3 3.3 1.8 3.3 0.2 1.166 1 1 1 1 54.3 6.3 3.8 5.9 12 1 130 17.8 7.74 5.3 0.23 11.63 Max 1.95 3.6 3.6 3.6 1.95 3.6 Unit V V V V V V mA mA µA µA µA µA mA mA mA µA µA µA mA mA mA mA mA mA ILow power Core Low power Current IO Low power Current PLL Low power Current Audio Low power Current Audio_PLL Low power Current TV Low power Current IHighpower Core High power Current IO High power Current PLL High power Current Audio High power Current Audio_PLL High power Current TV High power Current 26/49 STV0684 Electrical Characteristics 4.5 4.5.1 AC electrical characteristics SFP AC parameters Each SFP is a TTL schmitt trigger bidirectional pad Buffer, 3v3 capable with 2mA drive capability and Slew-rate Control. The 3.3V IOs comply to the EIA/JEDEC standard JESD8-B. 4.5.2 Audio ADC electrical parameters Table 7: Audio/ADC electrical characteristics Symbol Fclk Dutymclk Fs Vbias Rbias RIN Cin Dyn In SNR* Offset Harm1 Parameter Clock frequency Clk duty cycle Sample frequency Bias reference voltage Vbias impedance Input impedance Input capacitance Input dynamic range Signal / Noise ratio Offset error Signal to peak harmonics Test conditions Min. Typ. 12 Max. Unit MHz 40 8 Vbias / VDDA = 3V Vbias IN+ / ININ+ / INADC Out Full scale IN+ / IN- Gain 0dB (AGC off) Sinewave @FS - 3dB Gain 0dB After automatic calibration Sinewave @FS - 3dB Gain 0dB Sinewave @FS - 3dB Gain 24dB 75 50 1.5 5 50 10 1.5 82 60 48 % kHz V kΩ kΩ pF Vpp dB 100 LSB dB dB 1. Input sine wave 1kHz, Fmclk 11.289 MHz, BW = 10Hz-20 kHz, A-weighting filters, output 16 bits RAW PCM 27/49 Electrical Characteristics 4.5.3 AC electrical characteristics of USB transceiver STV0684 All measurements are fully electrically compliant to Chapter 7 (Electrical requirements) of revision 2 of the USB specification for full-speed devices (V1.1). The transceiver has been tested with external impedance-matching series resistors (27 Ω +/-5%) between the pads and the USB cable. The operation of the USB transceiver is guaranteed through design and application testing. Table 8: AC characteristics of USB transceiver Symbol Transmit /Output stage tlr tlf tlrfm System Rpu Rpd USB differential pad Dp, Dn pullup Resistor USB differential pad Dp, Dn pulldown Resistor 1.425 14.25 1.575 15.75 kΩ kΩ Fall time Rise time Rise and fall time matching 4.45 4.55 90 5.82 5.77 7.31 6.81 111 ns ns % Description Min. Typ. Max Unit 28/49 STV0684 4.5.4 SDRAM timing description Electrical Characteristics 4.5.4.1 Read/Write timing diagrams for external synchronous DRAM Figure 5: SDRAM read timing tCK DCLK CKE tCMS tCMH Command (RAS, CAS, WE) A0-9, BA, A11-12 A10 ACTIVE READ NOP PRECHARGE NOP tCL tCH ROW COLUMN ROW tAS tAH tCMS tAC tOH tCMH DQM DQ tRCD CAS Latency tRC tRAS tRP DOUT M DOUT M + 1 DOUT M + 2 DOUT M + 3 DQ sample DQ sample DQ sample DQ sample Figure 6: SDRAM write timing tCK DCLK CKE tCMS tCMH Command (RAS, CAS, WE) A0-9, A11-12 A10 ACTIVE WRITE NOP PRECHARGE NOP tCL tCH ROW COLUMN ROW tAS tAH tCMS tDS tDH tCMH DQM DQ tRCD DIN M DIN M + 1 DIN M + 2 DIN M + 3 tRC tRAS SDRAM Write Timing tRP 29/49 Electrical Characteristics Table 9: SDRAM timing Symbol tCK tCH tCL tAC tOH tCMS tCMH tAS tDS tDH tRCD tRAS tRC tRP tRRD1 tah 0 20.3 20 20.7 20.1 21.8 1 2 4 2 2 19.8 tCK/2 - (tCK*0.0345) tCK/2 - (tCK*0.0345) Min 41.67 tCK/2 tCK/2 tCK/2 + (tCK*0.0345) tCK/2 + (tCK*0.0345) 24.8 Typ Max STV0684 Units ns ns ns ns ns ns ns ns ns ns tCK tCK tCK tCK tCK ns 1. tRRD = Row active to row active delay Note: 1 The SDRAM interface is designed to operate with SDRAM devices which are compliant with the Intel SDRAM Specification Revision 1.7 November 1999. Speed grades 66, 100 and 133MHz are compatible. 2 Above timing assumes 20pF load per pad. 30/49 STV0684 I2C timing description Figure 7: START and STOP conditions Electrical Characteristics 4.5.5 START SDA STOP tSU;STA tHD;STA tSU;STO SCL Figure 8: SDA Data valid tLOW SCL tHIGH tHD;DAT tSU;DAT SDA Data valid Data allowed to change Data valid Data allowed to change Table 10: I2C timing Spec STD mode Symbol Parameter Min f SCL tLOW tHIGH tHD;STA tSU;STA tSTU;STO tHD;DAT tSU;DAT tBUF SCL clock frequency Low period of SCL High period of SCL Hold time for a repeated start Setup time for repeated start Setup time for a stop Data hold time Data setup time Bus free time between stop and start 10 4.8 4.8 4.8 4.8 4.8 350 2.4 4.8 FAST mode Unit Min 10 1.4 0.9 1.4 0.9 0.9 350 045 1.4 Max 100 - Max 400 kHz µs µs µs µs µs ns µs µs 31/49 Electrical Characteristics Figure 9: Message format STV0684 S SR 7 BIT DEVICE ADD R/w A 8 BIT DATA A (A) P SCL MSB LSB MSB LSB 1 SDA 2 3 8 9 1 2 7 8 9 4.5.6 SPI timing description It is able to support master and slave mode. The timing given is needed for slave mode and in master mode is able to provide tR, tF = 5ns with output load 30pF Figure 10: SPI timing diagram tDSU tDH SPI_SLK SPI_SLK tSCK SPI_MISO SPI_MOSI tV SPI_SLK SPI_SLK tCS tCHSH SPI_SS tCSS SPI_SS Table 11: SPI timing table Symbol fSCK tDSU tDH Parameter SCK frequency= 1/tSCK Data in Setup time Data in Hold time Min Max 24 (master) 48 (slave) Units MHz ns ns 18(master) 5(slave) 0(master) 5(slave) 32/49 STV0684 Table 11: SPI timing table Symbol tCSS tCHSH tV tCS tidle Electrical Characteristics Parameter SS active Setup time, relative to SCK SS active hold time, relative to SCK Clock low to output valid Minimum SS high time Idle phase between byte transfer in transmit mode for resynchronisation Min 210(master/ slave) 50(master/ slave) Max Units ns ns 20 (master/slave) 120(slave) 120(slave) ns ns ns In slave mode for resynchronization purpose the need for idle phase between byte transfer is needed for the transmit mode. Figure 11: Idle phase timing in slave mode tidle sck 33/49 Electrical Characteristics 4.5.7 NAND timing description Figure 12: Command latch cycle for NAND flash interface STV0684 CLE CE_n tCLS tWP tCLH WE_n ALE tALS tALH tDS tDH IO[7:0] Command Figure 13: Address latch cycle for NAND flash interface CLE tCLS CE_n WE_n tALH ALE tDS tDH A0-A7 A9-A16 A17-A21 tWC tWP tWH IO[0:7] 34/49 STV0684 Figure 14: Input data latch cycles for NAND flash interface CLE tCLH CE_n tALS ALE tWP WE_n tDS tDH IO[0:7] DIN0 DIN1 DIN511 Electrical Characteristics tWC tWH Figure 15: Sequential output cycle after read for NAND flash interface tRC tRP RE_n tREA IO[0:7] tRR RB_n Dout Dout Dout CE_n tREH Figure 16: Status read cycle for NAND flash interface CLE tCLS CE_n tWP WE_n tWHR tCLH tCLS RE_n tDS IO[0:7] tDH 70h tRSTO Status 35/49 Electrical Characteristics Figure 17: Read operation for NAND flash interface STV0684 CLE CE_n WE_n ALE tR RE_n tRR IO[0:7] RB_n 00H A0-7 A9-16 A17-21 Dout0 Dout1 Dout2 tWB Figure 18: Reset operation for NAND flash interface CLE CE_n WE_n IO[0:7] RB_n tRST FFh 36/49 STV0684 4.5.8 AC characteristics for NAND flash operation Table 12: AC characteristics for NAND flash operation Symbol tCLS tCLH tWP tALS tALH tDS tDH tWC tWH tRR tRP tRC tREA tREH tWHR tR tWB tRST CLE Set-up time CLE Hold time WE-n Pulse Width ALE Set-up time ALE Hold time Data Set-up time Data Hold time Write Cycle time WE_n High Hold time Ready to RE_n Low RE_n Pulse Width Read Cycle time RE_n Access time RE_n High Hold time WE_n High to RE_n Low Data Transfer from Cell to Register WE_n High to Busy Device Resetting (Read) 103.5 124.2 Electrical Characteristics Parameter Min 61.4 83.2 83.2 82.6 82.4 82.6 61.8 145.1 61.9 81 83.2 187.2 Typical 62.4 Max Units ns ns ns 83.2 83.2 83.2 62.4 145.6 62.4 83 ns ns ns ns ns ns ns ns ns 35 104 124.8 43.2 ns ns ns 25.015 41.6 215.3 5.015 µs ns µs Note: 1 All parameters relating to the CE_n signal are omitted as it is not enabled/disabled during execution of any NAND flash operation i.e. it is permanently tied low. 2 All timings are worst case 3 Conforms to both Samsung and Toshiba specifications as outlined in datasheets. 4 The NAND flash timings detailed here are guaranteed by design. 5 The loading factor used for the characterization is equivalent to 40pF. 4.5.9 Compact flash timing There are two types of bus cycles and timing sequences that occur in the PCMCIA type interface, direct mapped I/O transfer and memory access. The STV0684 will only support the memory mapped mode. 37/49 Electrical Characteristics 4.5.9.1 Compact flash pin description STV0684 The following table lists the pins of the CF card which are connected to the STV0684.Output refers to pins that are driven by STV0684. Input is those pins that are driven by the CF Card. Table 13: Pin description Symbol CFA0 ~CFA10 CARD_DET CARD_DET2 CS CARD EN IO0~IO7 ALE OE CLE RDY RE REG RST RB WAIT WE Address Card Detect Card Enable. Data. Only 8 bits of the data bus D[7:0] are used. Output Enable Ready/Busy Register(Attribute) Memory Select Reset Wait Write Enable Input Output Pin Description Direction Output Input Output Input Output Input Output SFP used 52~62 50 49 35~42 45 46 48 note 1 47 44 1. The reset may come from the global reset of the system or be driven by a user definable SFP this function is application specific. 4.5.9.2 Compact flash timings The timings achieved for accessing the attribute and common memory are listed below.There are registers in the CF Controller of the STV0684 in which all these timings can be programmed in terms of number of clocks of 48MHz. All the timings below assume a 48MHz operating clock frequency. Table 14: CF attribute memory read timing Symbol tc(R) ta(A) ta(CE) ta(OE) tdis(CE) tdis(OE) tsu (A) ten(CE) ten(OE) tv(A) Read Cycle Time Address Access Time Card Enable Access Time Output Enable Access Time Output Disable Time from CE Output Disable Time from OE Address Setup Time Output Enable Time from CE Output Enable Time from OE Data Valid from Address Change 40 5 5 0 Parameter Min. 340 - Typ. Max. Units ns 300 300 300 100 100 ns ns ns ns ns ns ns ns ns 38/49 STV0684 Figure 19: Attribute memory read timing diagram Electrical Characteristics Table 15: Attribute memory write timing Symbol tc(W) tw(WE) tsu(A) trec(WE) WE tsu(D-WEH) th(D) Write Cycle Time Write Pulse Width Address Setup Time Write Recovery Time Data Setup Time for WE Data Hold Time Parameter Min. 280 200 40 40 160 40 Max. Units ns ns ns ns ns ns 39/49 Electrical Characteristics Figure 20: Attribute memory write timing diagram STV0684 Table 16: Common memory read timing Symbol ta(OE) tdis(OE) tsu(A) th(A) tsu(CE) th(CE) tv(WT-OE) tv(WT) tw(WT) Item Output Enable Access Time Output Disable Time from OE Address Setup Time Address Hold Time CE Setup before OE CE Hold following OE Wait Delay Falling from OE Data Setup for Wait Release Wait Width Time Min. Max. 140 100 Units ns ns ns ns ns ns 40 40 0 40 40 0 350 ns ns ns 40/49 STV0684 Figure 21: Common memory read timing diagram Electrical Characteristics Table 17: Common memory write timing Symbol tsu(D-WEH) th(D) tw(WE) tsu(A) tsu(CE) trec(WE) th(A) th(CE) tv(WT-WE) tv(WT) tw (WT) Data Setup before WE Data Hold following WE WE Pulse Width Address Setup Time CE Setup before WE Write Recovery Time Address Hold Time CE Hold following WE Wait Delay Falling from WE WE High from Wait Release Wait Width Time 0 350 Parameter Min. 80 40 200 40 0 40 40 20 Max. Units ns ns ns ns ns ns ns ns 40 ns ns ns 41/49 Electrical Characteristics 4.5.10 TFT Table 18: TFT timing Symbol PNL_CLK HSYNC1 VSYNC1 Panel clock Horizontal Sync Vertical sync STV0684 Parameter Min. 1.56 2 2 Max. 27 1822 1598 MHz Units PNL_CLK periods Horizontal sync periods 1. HSYNC & VSYNC are active low (default, but programmable) and the falling edge of both HS & VS are always synchronous. 4.5.11 TV TV timing description Table 19: TV timing description Symbol Resolution Recommended load impedance Analog output Dynamic current1 Output voltage1 Dynamic performance SNR, BW=10MHz, Fclk=80MHz THD, BW=10MHz, Fclk=80MHz 50 50 dB dB 6.64 8 9.36 1.6 mA V DC 175 Parameter Min. Typ. Max. 10 Unit Bits Ω Voltage reference V_REXT - TV_GNDA_REXT -7% 1.4 +7% V 1. The output current of 8mA = typ: TV_REXT - TV_GNDA_REXT =1.4V, RREF=10000 Ω TV External components An external 10000 ohm precision resistor typical 1% placed between the TV_REXT pin and GNDAS_REXT sets the full scale DAC current. 42/49 STV0684 4.5.12 Sensor interface Figure 22: Timing for sensor input TCLK TSETUP THOLD Electrical Characteristics SPCLK SDATA[9:0] SENSOR_VSYNC SENSOR_HSYNC TRMAX TSKEW Table 20: Timing for Sensor Input Symbol TCLK TSETUP THOLD TRMAX TSKEW SPCLK Data valid before clock rising Data hold time Max transition time (20% to 80%) Data / clock skew Clock duty cycle 45 Parameter Min 20 (50MHz) 1.5 TCLK/2 1 440 55 ns ps Max 1000 (1MHz) Unit ns ns 4.6 ESD handling characteristics Table 21: ESD handling characteristics Test ESD Machine Model ESD Human body 150 2 Criteria Unit V kV 43/49 Electrical Characteristics STV0684 4.7 4.7.1 External circuits Crystal oscillator There are 2 crystal oscillator pins XTAL_IN, XTAL_OUT, as shown in Figure 23. The Oscillator cell architecture is a single stage oscillator with an inverter working as an amplifier. The oscillator stage is biased by an internal resistor (>1MΩ). It also requires an external PI network consisting of a crystal and two capacitors. Note: The TV standards requests that the clock accuracy of the oscillator circuit must be 30ppm or less to achieve a 500Hz accuracy for 4.5MHz chroma. Figure 23: Oscillator support circuit XTALI XTALO Crystal 22pF 22pF 4.7.2 Audio Figure 24: Audio PLL filter and CBS VC CBS 10K 680pF 10nF + _ 10µF If the record audio section of the STV0684 is not required, AP, CBS, VC and AN can be left unconnected. Power must still be supplied to VDDA and VDDAP. 4.7.3 Recommended power supply decoupling A 0.1µF bypass capacitor located as close as possible to the chip package connecting between all VDD pins and GND and at least one bulk decoupling capacitor on each of the supply rails VDDA, VDDC, VDDI and VDDP. 44/49 STV0684 Package Information 5 5.1 Package Information STV0684 pin assignment Figure 25: STV0684 pin assignment 14 13 12 11 10 9 8 7 6 5 4 3 2 1 LOW_ TV_GNDA TV_VDDA AP _REXT BAT VDDAP TV_ REXT VSSA P TV_ VSSA CVBS VSSA SFP7 SFP9 XTALO VSS_6 SFP14 SFP18 SFP22 SFP26 SFP29 SFP32 A SFP1 SFP4 SFP10 VSS_5 SFP13 SFP19 SFP24 SFP28 SFP31 SFP33 B CBS VDDA SFP8 XTALI VDDC _2 SFP12 SFP17 SFP23 SFP25 SFP30 SFP34 RESET VC C SFP16 SFP21 SFP27 SFP130 WAKEUP SFP37 SFP125 SFP127 SFP129 VREF AN SFP3 VDDP D SFP122 VSS_4 SFP126 SFP128 SFP0 SFP5 VSSP SFP11 SFP15 SFP20 SFP35 SFP36 SFP38 SFP39 E VSS_3 SFP121 SFP123 SFP124 VDDI_3 SFP2 SFP6 VDDI_4 VSS_7 SFP40 VDDI_5 SFP41 VDDC_3 SFP43 F SFP117 VDDI_2 SFP119 SFP118 SFP116 SFP120 VDDC_1 SFP44 VSS_8 DN DP SFP42 SFP45 USB_ DETECT UP_ TDI SFP46 G SFP114 SFP115 SFP112 SFP111 SFP109 SFP113 VSS_2 SFP72 UP_ TCK SFP70 SFP132 SFP131 UP_ RST SFP49 SFP47 UP_ TMS UP_ TDO SFP48 H SFP110 SFP107 SFP106 SFP105 SFP103 SFP102 SFP82 SFP75 J SFP50 SFP108 SFP104 SFP100 SFP99 SFP96 SFP86 VDDI_ 10 SFP79 SFP74 SFP69 SFP51 VSS_9 VDDI_6 SFP52 K SFP76 SFP68 SFP63 SFP62 SFP55 SFP54 SFP53 SFP101 VSS_1 VDDI_1 SFP95 SFP88 SFP83 L SFP98 SFP97 SFP94 VDDC_5 SFP90 SFP81 SFP78 SFP13 SFP12 VDDC_4 SFP64 SFP60 SFP57 SFP56 M SFP93 SFP92 SCLK VSS_ 15 SFP91 SFP89 SFP85 SFP80 SFP77 VDDI_9 SFP67 SFP65 VDDI_7 SFP59 SFP58 N SFP87 SFP84 VSS_ 14 SFP73 SFP71 VDDI_8 VSS_ 11 SFP66 VSS_ 10 SFP61 SPCLK SSCL SSDA P 45/49 Package Information STV0684 5.2 STV0684 package mechanical data Dimensions (mm) Reference Min. A A1 A2 b D D1 E E1 e f ddd 0.720 0.650 11.850 0.450 11.850 1.210 0.270 1.120 0.500 12.000 10.400 12.000 10.400 0.800 0.800 0.880 0.950 0.120 12.150 0.550 12.150 Typ. Max. 1.700 Note: 1 The maximum mounted height is 1.57 mm based on a 0.37 mm ball pad diameter. Solder paste is 0.15 mm thick with 0.37 mm ball pad diameter. 2 LFBGA stands for Low Profile Fine Pitch Ball Grid Array. Low profile: The total profile height (Dim A) is measured from the seating plane to the top of the component. A = [1.21 to 1.70] mm FIne pitch: e