STV1602A

STV1602A SERIAL INTERFACE TRANSMISSION DECODER BUILT-IN AUTOMATIC EQUALIZER FOR UP TO 30dB ATTENUATION AT 135MHz (TYPICALLY 300m OF HIGH-GRADE COAXIAL CABLE), PLL CIRCUIT FOR RECLOCKING, AND SERIAL-PARALLEL CONVERSION CIRCUIT. THIS SERIAL TRANSMISSION DECODER REQUIRES ONLY FEW EXTERNAL COMPONENTS. OTHER RELATED IC’s INCLUDE : STV1601A, A SERIAL TRANSMISSION ENCODER (PARALLEL-TO-SERIAL CONVERSION) STV1389AQ COAXIAL CABLE DRIVER STRUCTURE Hybrid IC ORDER CODE : STV1602A APPLICATIONS SERIAL DATA TRANSMISSION DECODER 100 to 270 Mb/s APPLICATIONS EXAMPLES Serial data transmission of digital television signals 525-625 lines 4:2:2 component 270Mb/s (10-bit) 4*fsc PAL composite 177Mb/s (10-bit) 4*fsc NTSC Composite 143Mb/s (10-bit) FUNCTIONS Cable equalizer (maximum gain : 30dB at 135MHz) PLL for serial clock generation Reclocked repeater output (active loop through) Descrambler : modulo-2 multiplication by G(x) = (x9 + x4 + 1) (x + 1) Parallel-to-serial conversion Sync monitor output Eye pattern monitoring Input signal detector 27 26 QFS CX GND MON ADS DIX DIY DPR FV 28 29 30 31 32 33 34 35 36 37 ESI 1 2 GND 3 SY 4 SX 5 QSW 6 TN1 7 VEE 8 VEE 9 1601A-01.EPS . . . . . . . . . . . . . . . . PGA37 (Ceramic Package) PIN CONNECTIONS GND GND RSE EVR SYN PCK 18 17 16 15 14 13 12 11 10 AIX 25 24 23 AIY V EE 22 21 20 19 D0 D1 D2 D3 D4 D5 D6 D7 D8 DESCRIPTION ESO The STV1602A is a Hybrid IC decoder which converts serial data coming from a serial transmission line into parallel data. December 1992 D9 1/22 STV1602A PIN DESCRIPTION Pin Symbol No GND Equivalent Circuit Description I/O Standard Min. Typ. Max. Unit 3 SY 30Ω 3 VR3 30Ω 4 1602A-02.EPS 4 SX VEE 2kΩ 145Ω 2kΩ Reclocked serial data output in differential mode. SX and SY are disabled when TN1 is set High. In this case, SX is set High and SY is set Low H L O -1.6 -2.4 V V GND 5 QSW (GND) To be connected to GND 1kΩ I 36 5 10kΩ 36 FV 10kΩ V EE 1602A-03.EPS Adjustment of VCO Free running frequency : VEE level gives the lowest frequency. To adjust it, set TN1 High. I GND 1kΩ 1kΩ 1 1 ESO 2kΩ 2kΩ Output of phase comparator : must be connected to ESI with the shortest distance O -3.2 V 1602A-04.EPS V EE 2/22 1602A-01.TBL STV1602A PIN DESCRIPTION (continued) Pin Symbol No 9 to 18 D9 to D0 GND 600Ω 600Ω 300Ω Equivalent Circuit Description Parallel data output H L 21 9 I/O O Standard Min. Typ. Max. Unit -0.8 -1.6 O -0.8 -1.6 V V 19 PCK VR3 210Ω VEE 210Ω 1602A-05.EPS 18 Parallel clock output (rising edge at data center) H L V V 21 EVR Data output reference potential O -1.2 V GND 26 AIX 300Ω 26 10kΩ 25 4kΩ 3kΩ 4kΩ 10kΩ Equalizer differential input I -2.0 V 25 AIY VEE 1602A-06.EPS GND 2kΩ 28 NC 1kΩ To be left open I -4.6 V 29 28 29 CX 16kΩ 2k Ω 2kΩ 1602A-07.EPS VEE 3/22 1602A-02.TBL Equalizer detector output; Input signal : absent present O -2.4 -2.0 V V STV1602A PIN DESCRIPTION (continued) Pin Symbol No Equivalent Circuit Description I/O Standard Min. Typ. Max. Unit GND 1kΩ 31 31 MON V R3 500Ω Equalizer monitor output. Connect 75Ω resistor between MON-GND. Observe using a 50Ω input oscilloscope at the 75Ω coaxial cable. O 15 mV (pp) 500Ω V EE 500Ω GND 2kΩ 2kΩ 1602A-08.EPS 32 ? VR2 32 ADS V R3 1602A-09.EPS Serial data input selection High : Digital input DIX/DIY Low : Equalizer input AIX/AIY H L I -0.5 -5 V V 2kΩ VEE GND 500Ω 500Ω 33 DIX VR1 Serial data digital differential input I 33 34 34 DIY V R3 1602A-10.EPS Selected when ADS is High. H L -1.0 -1.6 V V 1602A-03.TBL 500Ω VEE 4/22 STV1602A PIN DESCRIPTION (continued) Pin Symbol No Equivalent Circuit Description I/O Standard Min. Typ. Max. Unit GND 37 37 ESI PLL error signal input : must be connected to ESO with the shortest distance i -3.2 V V EE GND 20kΩ 2kΩ 1602A-11.EPS 2kΩ 6 TN1 6 Serial data input activation High : Input disabled (VCO free running condition). Low : Input enabled. During switch-on phase, by temporarily hold High for quick start-up 1602A-12.EPS I -1.0 -4.0 V V 12kΩ VEE 4kΩ GND 4kΩ V CC 20 SYN 20 State changes at each TRS Sync word 3FFH 000H 000H H L O -1.0 -4.0 V V 2kΩ VEE 2kΩ 1602A-13.EPS 5/22 1602A-04.TBL STV1602A PIN DESCRIPTION (continued) Pin Symbol No GND 1kΩ 1kΩ Equivalent Circuit Description I/O Standard Min. Typ. Max. Unit 35 DPR 35 Serial data detection output. When there is an input signal at the input side selected through ADS, this pin goes High. At no signal, it goes Low. H L i.e. - present : High - absent : Low 1602A-14.EPS O -1.0 -4.0 V V 6kΩ V EE GND 2kΩ 10kΩ 22 RSE 22 Selects VCO frequency range H : High range 140 to 270MHz L : Low range 100 to 145MHz H L 1602A-15.EPS I -0.4 -4.0 V V 10kΩ 10kΩ V EE 7 23 8 2 24 27 30 VEE VEE GND -5V supply I/O buffer, PLL equalizer -5V Supply Logic part GND -5.2 -5.2 -5.0 -5.0 -4.8 -4.8 V V 1602A-05.TBL 6/22 STV1602A BLOCK DIAGRAM EVR 21 SYN 20 PCK 19 D0 18 D1 17 D2 16 D3 15 D4 14 D5 13 D6 12 D7 11 D8 10 D9 9 GND 2 GND 24 Parallel clock GND 27 TIMING GENERATOR 10-BIT LATCH 7 VE E GND 30 ECL OUT REFERENCE VOLTAGE SYNC DETECTOR 30-BIT SHIFT REGISTER 23 V E E X + X + 1 DESCRAMBLER 9 4 8 VE E AIX 26 AIY 25 QFS 28 CX 29 MON 31 AUTOMATIC CABLE EQUALIZER DATA DETECTOR NRZI TO NRZ 4 Reclocked serial data SX Serial clock 3 INPUT SELECT DATA RELAY SY EDGE DETECTOR PHASE DETECTOR VCO 22 RSE 33 34 32 ADS 6 TN1 35 DPR 36 FV 1 37 DIX DIY ESO ESI ABSOLUTE MAXIMUM RATINGS (TA = 25oC) Symbol VEE VIN IOUT Toper Tstg PD Supply Voltage Input Voltage Output Current Operating Temperature Storage Temperature Allowable Power Dissipation Parameter Value -6 VEE to 0 -30 0 to 65 -50 to 125 2.0 Unit V V mA o o C W RECOMMENDED OPERATING CONDITIONS VEE Toper Supply Voltage Operating Temperature -4.8 to -5.2 0 To 65 V oC 1602A-07.TBL Symbol Parameter Value Unit 7/22 1602A-06.TBL C 1602A-16.EPS STV1602A ELECTRICAL CHARACTERISTICS (VEE = -5V, TA = 25oC unless otherwise specified) Symbol IEE VIH VIL VIH VIL VIH VIL IIH IIL VIH VIL VOH VOL VM VOH VOL VOH VOL fMAX1 fMIN1 fMAX2 fMIN2 fHP1 fLP1 fHP2 fLP2 fHP3 fLP3 fOP1 fOP2 Parameter Supply Current Test Conditions VEE = 5V Pin ADS Input Voltage Pin RSE Pin DIX, DIY Input Current Input Voltage Pin DIX, DIY Pin TN1 Pin PCX, Dn R P = 1kΩ Output Voltage Pin EVR, RP = 1kΩ Pin DPR, SYN IOH = -10µA, IOL = +10µA Pin SX, SY R P = 220Ω Figure 7 Figure 8 -1.0 -4.0 -1.6 -2.4 30.0 Figure 6 14.0 15.0 10.0 27.7 25.5 18.5 Figure 3 15.0 14.0 10.0 13.3 27.0 14.5 16.8 Figure 5 Figure 9 Figure 10 Test Circuit Min. Figure 4 -0.4 -1.5 -0.4 -4.0 -1.0 -1.6 5.0 +1.0 -4.6 -0.8 -1.6 -1.2 TYp. 185 Max. Unit mA V V V V V V µA µA V V V V V V V V V MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz DC CHARACTERISTICS -1.0 -1.0 AC CHARACTERISTICS VCO VCO VCO VCO Max. Oscillation Frequency 1 Min. Oscillation Frequency 1 Max. Oscillation Frequency 2 Min. Oscillation Frequency 2 RSE RSE RSE RSE = ”H” = ”H” = ”L” = ”L” f signal = 270MHz RSE = ”H” PLL Pull in Range f signal = 177MHz RSE = ”H” f signal = 143MHz RSE = ”H” PLL Generator Frequency RSE = ”H” RSE = ”L” Frequency at 1/10 the value of signal frequency (Tested through Pin PCK) SWITCHING CHARACTERISTICS (VEE = -5V, TA = 25oC unless otherwise specified) Symbol tr tf tr tf td Parameter Rise Time Fall Time Rise Time Fall Time Delay Time Test Conditions Pins PCK, Dn R P = 1kΩ Pins SX, SY R P = 220Ω Pins PCK, Dn Figure 3 -3 Test Circuit Min. Typ. 0.8 1.4 0.7 0.7 Max. Unit nsec nsec nsec nsec nsec +3 8/22 1602A-09.TBL 1602A-08.TBL STV1602A EQUALIZER (VEE = -5V, TA = 25oC unless otherwise specified) Symbol VMAX GMAX CIN RIN Parameter Equalizer Max. Input Voltage Equalizer Max. Gain Input Capacity Input Resistance Test Conditions Pins AIX, AIY Pins AIX, freq = 100MHz Pins AIX, freq = 100MHz Test Circuit Min. 0.88 Figure 3 Typ. 30 Max. Unit Vp-p dB pF Ω Figure 1 : tr, tf, tc, td Definition tc t c /2 t c /2 80% Dn 1602A-17.EPS / 1602A-18.EPS 20% PCK 50% tr tf td tw Power save SW 9/22 1602A-19.EPS SYN pin guaranteed operation range. SYNC pin and serial to parallel conversion operate normally within the frequency and ambient temperature ranges according to the following considerations. Reclocked output. STV1602A may be used as a repeater. The reclocked output, providing characteristics almost identical to the serial output of STV1601A is available from SX (Pin 4) and SY (Pin 3). When the reclocked output is used, it is recommended not to use simultaneously use the parallel outputs (data and clock) in order to avoid possible logic errors caused by an excessively high temperature which may result from additional power dissipation created by the reclocked output circuit under certain environnmental conditions. If, for the sake of a design convenience, both reclocked and parallel outputs are to be used, the ambient temperature has to be kept as low as possible or, at least, the airflow around STV1602A must be carefully considered. In addition, it is recommended to put 220Ω resistors on all parallel outputs including the clock as shown in Figure 2. This reduces the magnitude of the spike current resulting from the parallel output circuit inside the chip and helps reduce the probability of logic errors at high temperature. Power saving in repeater mode Since the parallell output is not always required for a reclocked repeater, the chip has been designed such that the uncessary parallel logic circuit can be disabled by disconnecting Pin 8, one of VEEs, from the power supply. With this arrangement the power dissipation is reducible to about 45 percent of that of the fully functional mode. In practice, a test switch should be provided so that some parallel signals may be available during adjustment procedures as shown in Figure 2. Figure 2 : A Suggested Parallel Clock / Data Output Circuit EVR 21 1kΩ PCK 19 1kΩ D0 18 1kΩ ECL line drivers or ECL/TTL translators 220Ω 220Ω STV1602A 220Ω V EE 8 D9 9 1kΩ 0.1µF V EE (-5V) 1602A-10.TBL 10/22 -5V 10/16V 0.1 0.1 STV1602A 2 GND V EE 24 27 30 23 TRS DETECTOR SIGNAL FREQENCY MONITOR 8 SYN 20 PCK 19 7 32 ADS 1kΩ STV1602A -5V 33 DIX 22k Ω 0.1 TN1 6 10µF 220Ω 34 DIY QSW 5 FV 36 35 DPR SW3 ON : AF FREQUENCY ADJUST 220Ω 22 1 37 220Ω 330Ω RSE ESO ESI 0.1 -5V 100kΩ V R - .3V V EE -5V VCO RANGE SELECT LED Figure 3 :Test Circuit Diagram Example 10/16V 10kΩ 0.1 0.1 -5V -5V -5V 0.1 VCO FREQUENCY ADJUST V R2 10/16V 2 2 24 27 5 32 29 27 26 0.1 0.1 30 23 8 7 TRS DETECTOR SIGNAL FREQENCY GND V CC V EE 30 PCX -5V N.C. 37 1kΩ 10kΩ A SW2 4 -5V 3 SY SX FREQUENCY MONITOR 31 PCY INPUT SELECT A CABLEINPUT B DIGITAL INPUT B GND VEE SYN 20 EVR 21 PCK 19 D0 18 6 D9X 1kΩ x 4 MONITOR 7 D9Y PLL LOCK DETECTOR 1 PCK 36 8 D8X 10µF 32 ADS 9 D8Y 220Ω 10 D7X 0.1 1 220 Ω 0.1 0.1 75Ω LST D1 17 11 D7Y 0.1 75Ω 3 STV1389AQ SERIAL OUT 29 CX -5V 0.1 1kΩ x 8 HP8182A SIGNAL ANALYZER 12 D6X SX 13 D6Y 100 Ω 31 MON D2 16 D3 15 14 D5X 15 D5Y STV1601A 4 220 Ω 150Ω -5V SY 2 28 QFS SERIAL IN 41pF 16 D4X 220Ω 150Ω -5V 220 Ω 220 Ω D.U.T. STV1602A 26 AIX D4 14 D5 13 D6 12 D7 11 17 D4Y -5V 18 D3X 0.1 0.1 0.1 HP8180A 19 D3Y 150pF 0.22µ H 73Ω 41pF 25 AIY 33 DIX D8 10 D9 20 D2X 9 -5V SIGNAL GENERATOR 21 D2Y TRP 34 22 D1X 10µF/10V SW2 22kΩ TN1 6 220Ω 10µ F 0.1 23 D1Y ON : AF FREQUENCYADJUST 22kΩ -5V 220Ω 24 D0X 25 D0Y TN1 35 34 DIY 220Ω QSW 5 SW3 ON : AF FREQUENCY ADJUST RSE ESO ESI 22 FV RSE FV 1 -5V 0.1 100kΩ 37 36 DPR 35 330Ω 33 28 LED SW1 VCO RANGE SELECT VCO RANGE SELECT B A 10kΩ A HIGH RANGE B LOW RANGE VCO FREQUENCY ADJUST 10kΩ V R2 0.1 V R1 VCO FREQUENCY ADJUST -5V -5V -5V -5V 1602A-20.EPS STV1602A Figure 4 V EE -5V I EE A 10/16V 0.1 0.1 2 24 27 30 23 8 V EE 7 1kΩ 21 19 18 1kΩ D9 9 220Ω -5V 0.1µF 1kΩ 1kΩ GND EVR PCX D0 1 ESO STV1602A 37 ESI ADS 32 RSE 22 FV 36 QSW TN1 5 6 10µF SW1 10kΩ SW1 10kΩ -5V -5V POSITION ON 1602A-21.EPS Figure 5 -5V 10/16V 0.1 V1 -0.8V -1.6V V2 -1.6V -0.8V A1 I IH I IL A2 I IL I IH 2 24 27 30 23 8 V EE 7 0.1 GND 33 DIX 34 DIY STV1602A 11 12 1 ESO TN1 6 37 ESI V1 V2 ADS 32 RSE 22 FV 36 QSW 5 -5V 11/22 1602A-22.EPS 10kΩ STV1602A Figure 6 -5V 10/16V 0.1 0.1 2 24 27 30 23 8 VEE 7 GND FREQUENCY MONITOR 1kΩ 1kΩ 1kΩ 1kΩ -5V 0.1µ F 22kΩ EVR 21 PCX 19 1 ESO STV1602A D0 18 D9 37 ESI 9 ADS 32 RSE 22 FV QSW TN1 5 36 6 10µF SW2 SW1 10kΩ B -5V -5V A 10kΩ SW1 SW2 VCO RANGE POSITION A B ON ON HIGH LOW Figure 7 -5V 10/16V 0.1 0.1 10µF 2 29 CX 24 27 30 23 8 V EE 7 GND Serial IN 33 DIX 73Ω 41pF 41pF 34 DIY 1 ESO RSE 22 FV 36 DPR 35 V STV1602A TN1 QSW 5 6 V I IL 270Mb/s SIGNAL IL SERIAL IN INPUT OPEN 37 ESI ADS 32 V OH 10µ A V OL -10µA -5V 12/22 1602A-24.EPS 10kΩ 1602A-23.EPS STV1602A Figure 8 -5V 10/16V 0.1 0.1 2 24 27 30 23 8 V EE 7 GND ONE - SHOT TRS GENERATOR 33 DIX 34 DIY STV1602A 1 ESO SYN 20 V IL V VOH VOL IL 10µ A -10µA 37 ESI ADS RSE 32 22 FV 36 QSW TN1 5 6 10kΩ 22kΩ 10µF/16V SW3 1602A-25.EPS 10kΩ -5V -5V -5V Figure 9 -5V 10/16V 0.1 0.1 2 24 27 30 23 8 V EE 7 GND 6 V1 TN1 33 DIX 34 DIY 10kΩ -5V 1 ESO STV1602A D0 18 V 37 ESI ADS 32 RSE 22 FV 36 QSW 5 -5V 13/22 1602A-26.EPS 10kΩ STV1602A Figure 10 -5V 10/16V 0.1 0.1 2 24 27 30 23 8 V EE 7 FREQUENCY MONITOR 1kΩ GND 22 RSE V1 33 DIX 34 DIY 1 -5V ESO STV1602A PCX 19 -5V 0.1 37 ESI ADS 32 FV 36 QSW 5 TN1 6 22kΩ 10µF/16V SW3 1602A-27.EPS 10kΩ -5V -5V STV1602A GENERAL As shown in the overall block diagram on page 7, STV1602Ais composed of the following functions : (1) Analog input as a primary input with automatic equalizer to meet the loss characteristics of coaxial cable (2) Digital input as a secondary input to receive the encodedsignal from short distances within the same printed circuit board or the same equipment (3) Phase locked loop (PLL) variable oscillator (4) Reclocked serial output (5) Serial descrambler (6) SYNC detector (7) Deserializer (8) Parallel output buffer amplifiers (9) Three diagnostic signals : eye monitor, SYNC monitor and input data presence monitor A brief explanation of each function is given in the following sections. 1. Cable equalizer Transmission of high speed digital data by means of coaxial cable can greatly attenuate high frequency components.According to the cable length, received signals can widely differ from those sent; in such conditions, clock extraction and data identification could be difficult. 14/22 The cable equalizer overcomes this problem. The IC performs up to 30dB (typical) equalization at 135MHz, typically 300m of high-grade coaxial cable. The equalization is automatically performed according to the coaxial cable length. The input signal can be delivered either through a transformer or through a capacitor. When the digital input is selected, the equalizer is disabled. Typical characteristics of the equalization are given in Figure 31. Figure 11 : Equalizer Capacitor Coupling Input Circuit Monitor OUT 100Ω 30 GND 29 CX 10µF Serial IN 75Ω 25 AIY 47pF 1602A-28.EPS 31 MON STV1602A 26 AIX 47pF STV1602A Figure 12 : Equalizer Transformer Input Circuit Figure 15 : AGC Time Constant 10µF/16V 26 AIX 75Ω Serial IN 2.2kΩ 25 AIY 1602A-29.EPS STV1602A STV1602A 2. Digital input The serial data input can be used without the equalizer. DIX (Pin 33) and DIY (Pin 34) are differential inputs for ECL signals. From these pins, input signals are differentially amplified, therefore with no input signals, the data detectionsignals could go High and erroneousdata would be transferred to the parallel output. To avoid this, a voltage level conforming to ECL specifications must be applied between DIX and DIY pins. Also, while the analog input is in use, digital input must be kept ”quiet” in order to avoid possible errors caused by cross-talk. This cross-talk problem naturally gets most severe when the analog input cable length is close to the limit of the transmission capability. 3. Serial input selection Selection of the serial input is performed by ADS (Pin 32); when High the digital input is enabled; this input can be used for very short transmission lines. When Low, the equalizerinput is enabled;this input must be used for long transmission lines. 4. PLL In order to extract clock signals from the equalized serial data, it is processed to generate edge signals which are sent to the phase comparator. When the PLL is locked, the identifier clock (D flipflop) will be in phase with the incoming clock. The identifier clock rises at the center of the data period for easy identification. The PLL detailed block diagram is shown in Figure 16. ESI is the VCO control input (Pin 37). Normally, the phase comparator output ESO (Pin 1) is connected to ESI. Since the VCO employed has a very high sensitivity, those two nodes must be connected with a shortest distance and a minimum area of conductor In both input circuit configurations, a consideration is required in a practical design to obtain a sufficient return-loss (at least 15dB over a frequency range of 5MHz to the bit rate frequency used). To achieve this, it is effective to add a small inductance in series with the 75Ω termination resistor. Figure 13 shows an implementation example. Figure 13 : An example of technique to improve the return-loss figure for the capacitor coupling input case 1mm Printed circuit inductance 47pF R = 6mm Coaxial Cable Terminator ( Through-holeto a ground plane) 75 47pF AIY Pin 25 AIX Pin 26 1602A-30.EPS MON Pin (31) Equalized signals can be observed at this pin by connecting an oscilloscope input (50Ω). Figure 14 : Equalized Waveforms Monitoring 50Ω coaxial cable MON 35 To 50Ω input oscilloscope 75Ω 1602A-31.EPS STV1602A GND 30 CX Pin (29) Equalizer AGC time constant Connect a 10µF capacitor in serial with 2.2kΩ resistor between this pin and GND in order to obtain stable operation at all times. According to input signals, voltage changes from -2V to -2.4V can occur. 15/22 1602A-32.EPS 29 CX STV1602A on the printed circuit board. Encircling those two nodes by a ground guarding is an efficient method to prevent errors caused by an ”antenna effect”. Through FV (Pin 35) one can adjust the free running frequency; when the FV Voltage is equal to VEE, the free running frequency is the lowest; the voltage adjustment can be performed by using a Figure 16 : Serial Data Input and PLL Descrambler NZRI to NRZ conversion SX F DC E From equalizer A DL DL B C Phase Comparator VCO RSE D SY variable resistor connected between FV and VEE. RSE (Pin 22) selects the VCO frequency range; High : 140 to 270MHz, Low : 100 to 145MHz. When TN1 (Pin 6) is set High, input signals are disabled and the VCO free runs. The capacitor connected between TN1 and GND avoids mislocking problem when the power supply is switched on. DIX DIN ADS TN1 ESO ESI FV Data detection Serial data edges are detected and go through low pass filter. The processed signal is available at DPR (Pin 35).DPR goes High when an input signal is detected, otherwise it stays Low. The driving capability of this pin is weak. It is recommended to load it with a high impedance CMOS or equivalent. 5. NRZI To NRZ conversion, descrambler Serial data delivered by the identifier is available in differential mode, SX (Pin 4) and SY (Pin 3). At the same time, to recover the original data, NRZI to NRZ conversion and descrambling are performed. Figure 17 : NRZI to NRZ conversion Figure 18 : x9 + x4 + 1 Descrambler In D1 D2 D3 D4 D5 D6 D7 D8 D9 1602A-35.EPS 1602A-36.EPS Out Figure 19 : Actual x9 + x4 + 1 Descrambler In D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 Out PLL D Clock 16/22 1602A-34.EPS Serial Signal Data (NRZI) Data (NRZ) 6. Serial to parallel conversion After descrambling, serial data is sent to a 30-bit register to detect the sync word (TRS). When the sequence 111111111100000000000000000000is detected, sync word detection signal is output, the counter which divides the clock frequency by 10 is initialized and data is converted to parallel (10-bit word) to be output. 1602A-33.EPS STV1602A Each time the sync word is detected, SYN (Pin 20) changes state as shown in Figure 20. When a receiver using STV1602A is properly implemented and adjusted, the health of the implementation can be checked simply by looking at SYN (Pin 20) output while an encoded signal is present at the input. SYN is an output of a flip-flop which togglesat each detection of TRS at the SYNC detector. Since the 4:2:2 signal contains two kinds of TRSs, SAV and EAV, when the output of SYN is observed by an oscilloscope it looks like either case A or case B as shown in Figure 20 depending upon the initial condition of the Flip-Flop. When bit erros are occurring somewhere in the transmission path, SYN output is affected and looks like as shown in case C. Figure 21 illustrates the case for 4 fsc (D2 NTSC and PAL). Differing from the 4:2:2 case, SYN output has an equal mark and space ratio due to the periodic Figure 20 : SYNC Output in 4:2:2 Case (not to scale) 1 TV line 4:2:2 Data Stream E A V HBLK S A V Active Video E A V HBLK S A V Active Video E A V HBLK S A V Active Video E A V occurence (once per one TV line) of the TRS detection. However, transmission path bit errors will cause the SYN output to appear similar to the 4:2:2 case. If SYN signal is used other than for monitoring purposes, buffering similar to that of DPR is required due to the high impedance nature of SYN output. 7. Phase relation ship between parallel data and parallel clock Parallel data and clock are output so that the rising edge of the parallel clock is located at the center of the parallel data. Both parallel data and clock (nearly identical to that of single ECL) have DC levels depending on the temperature. In order to simplify the driving amplifier, a reference level (EVR) is available at Pin 21. PCX, Dn and EVR use pull down resistors (identical values). A peripheral circuit example is shown in Figure 23. Figure 24 shows a circuit to disable the parallel clock output. SYN output (case A) SYN output (case B) SYN output (case C) 1602A-37.EPS Figure 21 : SYNC Output in 4 fsc Case (not to scale) 1 TV line T R S T R S T R S 4 fsc DataStream Active Video + H- BLK Active Video + H- BLK Active Video + H- BLK SYN output 17/22 1602A-38.EPS STV1602A Figure 22 : Phase Relation of Parallel Clock, Data and EVR Voltage Level Parallel clock Parallel data V OH EVR output voltage 1601A-39.EPS V OL Figure 23 : Parallel Clock Data Output Circuit EVR 21 1kΩ PCK 19 1kΩ D0 18 1kΩ STV1602A D9 9 1kΩ 0.1µF V EE with temperature. FV pin voltage remains almost constant regardless of temperature. Figure 25 shows an example of a temperature compensation circuit using a diode (transistor with C-B diode short-circuited) and a resistor between FV and VEE. PLL pull-in range (signal frequency 270, 177 and 143MHz) are given by Figures 32, 33 and 34. 9. VCO free running frequency adjustment VCO free running frequency adjustment is performed at room temperature. If TN1 is set High, VCO is free running. Wait for 5 to 10 minutes after turning power supply ON (warm up time). While monitoring PCK (Pin 19) output, adjust the signal frequency (within ±1%) with the variable resistor connected between FV and VEE. Figure 25 : VCO Temperature Compensation and Free Running Frequency Adjustment STV1602A Figure 24 : A Circuit Example to Disable Parallel Clock CMOS inverter DPR 35 0.1µF EVR 6 1kΩ PCK 21 1kΩ 10kΩ 10kΩ STV1602A V EE 1602A-41.EPS 1602A-40.EPS 0.1µF TN1 6 FV 36 PCX 19 8. VCO temperature compensation and oscillation frequency adjustment. VCO oscillation frequency depends on the temperature as shown in Figures 29 and 30 ”Representative characteristics example”. Within the normal range of operation, frequency increases 10µ F 22kΩ Small signal transistor Frequency monitor 1kΩ 10kΩ VEE 18/22 1602A-42.EPS STV1602A Using particular codes to check overall performance Althrough the scrambling method employed effectively randomizes the incoming data and puts out a signal with a nearly uniform spectrum, there still exist some combinations of codes that give somewhat unfriendly conditions to the transmission path in terms of low frequency component or of a long run without any transitions. As shown in Figure 26, it is known that if the code words 300, 198 (hex, 10-bit) are given alternately to the parallel input of the encoder, the largest amount of DC component (nearly one TV line period) can be produced at some place with a certain probability (such a sequence is, however, destroyed when different data is input to the encoder). Even with such signals, error-free reception is possible with the STV1602Aif a proper implementation is made (refer to section 12 for a recommended circuit). Figure 26 Input data : hex, 10-bit (hex, 8-bit) Serial output when the worst sequence on DC component is occuring (case A) (case B) 300 (CO) 198 (66) 1 bit 19 bits 1602A-43.EPS Another particular combination of words, but with a different nature, is 200, 110 (hex, 10-bit) which can generate the sequence which is most vulnerable* to bit slip of nearly one TV line period. Figure 27 illustrates such a situation. Similar to the previous case, the worst sequence stops upon an arrival of a data other than the alternating 200, 110 at the input of the encoder. Figure 27 : Particular Data words for checking PLL bit slip Input data : hex, 10-bit (hex, 8-bit) Serial output when the worst sequence on bit slip is occuring 110 (44) 200 (80) 110 (44) 200 (80) 20 bits 20 bits 1602A-44.EPS 300 (CO) 198 (66) 1 bit * Stricly speaking the longest isolated run is 38 clocks for 4:2:2 and 43 clocks for 4 fsc NTSC and PAL. However, the above sequence generally shows the most critical situation for the bit slip problem. Note : Actually there exists a family of such particular code as above described. They will, h owe ve r, cre at e an id en tical sequence in the serial domain since the difference amongst the family is merely which bit is regarded as the start bit of a word. 19/22 34 DIY 35 DPR D6 12 D7 11 36 FV D8 10 -5V 10kΩ Q1 37 ESI ESO GND 2 5 3 4 SY SX VCO Center freq. adj. QSW 1 TN1 6 22kΩ VEE 7 V EE 8 D9 9 -5V 0.1µ F 10µF/16V Test jumper 1kΩ 1602A-45.EPS Parallel data out (ECL) 20/22 Serial IN (from cable) -5V HIGH D1, D2 PAL (-1.3V) 10kΩ Test point 75Ω 47pF 27 GND VEE AIX AIY GND RSE EVR (Rate select) D0 18 SYN PCK 26 25 23 22 21 19 Parallel CK 24 20 47pF LOW D2 NTSC 29 CX D1 17 30 GND D2 16 31 MON D3 15 32 (DECODER MODULE) 33 DIX D5 13 ADS (Input select) STV1602A (open) 28 QFS Figure 28 : Application Circuit Example 10µF/16V 2.2kΩ 100Ω Eye monitoring Digital IN 10kΩ -5V STV1602A D4 14 Serial IN ECL Pair Tx line STV1602A REPRESENTATIVE CHARACTERISTICS EXAMPLE Figure 29 : VCO Oscillation Frequency versus FV Pin Voltage RSE: ”H” VCO oscillation frequency (MHz) VCO oscillation frequency (MHz) Figure 30 : VCO Oscillation Frequency versus FV Pin Voltage 45°C 150 140 45°C 130 120 110 1602A-47.EPS 1602A-52.EPS 1602A-49.EPS 25°C 300 RSE : ”L” 85°C 260 45°C 220 180 85°C -15°C 1602A-46.EPS 65°C 25°C 5°C 65°C 85°C 5°C -15°C 140 0.80 0.90 1.00 1.10 1.20 1.30 100 0.90 1.00 1.10 FV pin Voltage (V) 1.20 1.30 FV pin Voltage (V) Figure 31 : An example of equalizer characteristics using 5C - 2V coaxial cable with respect to the gain for 0.5meter 20 15 10 5 Figure 32 : Pull-in Range and Free Run Frequency (270Mb/s) 30 Frequency (MHz) 29 28 27 26 25 24 Low pull in -15 5 25 45 65 85 Free run High pull in Gain (dB) 0 100 Frequency (MHz) 200 1602A-48.EPS 23 Ambient temperature (°C) Figure 33 : Pull-in Range and Free Run Frequency (177Mb/s) 21 Frequency (MHz) 20 19 18 17 16 15 -15 5 25 45 65 85 1602A-51.EPS Figure 34 : Pull-in Range and Free Run Frequency (143Mb/s) 18 Frequency (MHz) 17 16 15 14 13 12 11 -15 5 25 45 65 85 Ambient temperature (°C) Free run Low pull in High pull in High pull in Free run Low pull in 14 Ambient temperature (°C) 21/22 STV1602A PACKAGE MECHANICAL DATA 37 PINS - CERAMIC PGA Dimensions in mm 3.8 25.4 0.5 0.2 Seating plane 1.15 0.15 1.2 4.2 0.1 0.46 0.05 Pin 19 2.54 x 9 = 22.86 0.25 Pin 28 0.25 2.54 x 9 = 22.86 Pin 36 Pin 37 2.54 25.4 Bottom View 0.5 Pin 10 2.032 max. 2.54 Pin 1 Information furnished is believed to be accurate and reliable. However, SGS-THOMSON Microelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No licence is granted by implication or otherwise under any patent or patent rights of SGS-THOMSON Microelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. SGS-THOMSON Microelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of SGS-THOMSON Microelectronics. © 1994 SGS-THOMSON Microelectronics - All Rights Reserved Purchase of I2C Components of SGS-THOMSON Microelectronics, conveys a license under the Philips I2C Patent. Rights to use these components in a I2C system, is granted provided that the system conforms to the I2C Standard Specifications as defined by Philips. SGS-THOMSON Microelectronics GROUP OF COMPANIES Australia - Brazil - China - France - Germany - Hong Kong - Italy - Japan - Korea - Malaysia - Malta - Morocco The Netherlands - Singapore - Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - U.S.A. 22/22 PM-PGA37.EPS