STV7610

STV7610A PLASMA DISPLAY PANEL DATA DRIVER FEATURE s s s s s s s s s 96 OUTPUTS PLASMA DISPLAY DRIVER 100 V ABSOLUTE MAXIMUM SUPPLY 5 V SUPPLY FOR LOGIC 60/50 mA SOURCE/SINK OUTPUT MOS 60/50 mA SOURCE/SINK OUTPUT DIODE 6 bit CASCADABLE DATA BUS (20 MHz) BLANK, POLARITY CONTROL BCD TECHNOLOGY PACKAGING TQFP144 OR DICE DIE ORDER CODE: STV7610A/WAF(1) (1): Unsawn tested wafer DESCRIPTION The STV7610A is a BCD data driver for Plasma Display Panel (PDP). Using a 6-bit wide cascadable data bus, it addresses 96 high current & high voltage outputs. By serially connecting several STV7610A, any horizontal pixel definition can be performed. The 20 MHz shift clock gives an equivalent 120 MHz shift register. The STV7610A is supplied with a separated 90 V power output supply and a 5 V logic supply. All command inputs are CMOS compatible. TQFP144 (20 x 20 x 1.4 mm) (Thin Plastic Quad Flat Pack) ORDER CODE: STV7610A Version 4.2 June 2000 This is preliminary information on a new product in development or undergoing evaluation. Details are subject to change without notice. 1/17 1 STV7610A PIN CONNECTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 PIN CONNECTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 PIN LIST . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 PAD COORDINATES (IN MM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 BLOCK DIAGRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 CIRCUIT DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 NOTE 1 ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 NOTE 4 THERMAL DATA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 NOTE 4 ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 NOTE 5 AC TIMINGS REQUIREMENTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 NOTE 5 AC TIMINGS CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 FIGURE 2. INPUT/OUTPUT SCHEMATICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 FIGURE 6. PACKAGE MECHANICAL DATA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2/16 2 STV7610A PIN CONNECTIONS (DIE Pinout) OUT63 OUT62 OUT61 OUT60 OUT59 OUT58 OUT57 OUT56 OUT55 OUT54 OUT53 OUT52 OUT51 OUT50 OUT49 OUT48 OUT47 OUT46 OUT45 OUT44 OUT43 OUT42 OUT41 OUT40 OUT39 OUT38 OUT37 OUT36 OUT35 OUT34 VSSP VPP VPP OUT64 OUT65 OUT66 OUT67 OUT68 OUT69 OUT70 OUT71 OUT72 OUT73 OUT74 OUT75 OUT76 OUT77 OUT78 OUT79 OUT80 OUT81 OUT82 OUT83 OUT84 OUT85 OUT86 OUT87 OUT88 OUT89 OUT90 OUT91 OUT92 OUT93 OUT94 OUT95 OUT96 (0,0) X Y VSSP VPP VPP OUT33 OUT32 OUT31 OUT30 OUT29 STV7610A Bare Die OUT28 OUT27 OUT26 OUT25 OUT24 OUT23 OUT22 OUT21 OUT20 OUT19 OUT18 OUT17 OUT16 OUT15 OUT14 OUT13 OUT12 OUT11 OUT10 OUT9 OUT8 OUT7 OUT6 OUT5 OUT4 OUT3 OUT2 OUT1 VSSSUB VCC B6 B5 B4 B3 B2 B1 A1 A2 A3 A4 A5 VPP A6 BLK F/R CLK STB VSSP VPP POL VSSLOG VSSP 3/17 3 STV7610A PIN CONNECTIONS (TQFP Pinout) OUT63 OUT62 OUT61 OUT60 OUT59 OUT58 OUT57 OUT56 OUT55 OUT54 OUT53 OUT52 OUT51 OUT50 OUT49 OUT48 OUT47 OUT46 OUT45 OUT44 OUT43 OUT42 OUT41 OUT40 OUT39 OUT38 OUT37 OUT36 OUT35 OUT34 VSSP VSSP 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 NC NC NC 111 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 VPP VPP NC OUT64 OUT65 OUT66 OUT67 OUT68 OUT69 OUT70 OUT71 OUT72 OUT73 OUT74 OUT75 OUT76 OUT77 OUT78 OUT79 OUT80 OUT81 OUT82 OUT83 OUT84 OUT85 OUT86 OUT87 OUT88 OUT89 OUT90 OUT91 OUT92 OUT93 OUT94 OUT95 OUT96 110 NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 VP P VP P NC OUT33 OUT32 OUT31 OUT30 OUT29 OUT28 OUT27 OUT26 OUT25 OUT24 OUT23 OUT22 OUT21 OUT20 OUT19 OUT18 OUT17 OUT16 OUT15 OUT14 OUT13 OUT12 OUT11 OUT10 OUT9 OUT8 OUT7 OUT6 OUT5 OUT4 OUT3 OUT2 OUT1 STV7610A TQFP144 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 NC 71 NC POL F/R B6 B5 B4 B3 B2 B1 A1 A2 A3 A4 A5 VSSP A6 VSSSUB BLK VSSP VCC VPP VPP NC NC NC NC NC NC NC NC CLK 4/17 3 VSSLOG STB NC NC 72 STV7610A PIN LIST (TQFP144) Pin N° 3-37-38-39-41-43-48-65-67-6970-71-72-106-110-111-142-143 1-2-42-66-107-108 53 40-68-109-144 54 55 73 to 105 112 to 141 4 to 36 50 51 52 56 57 59 to 64 44 to 49 Symbol VPP V CC V SSP V SSLOG VSSSUB OUT 1 to OUT 33 OUT 34 to OUT 63 OUT 64 to OUT 96 BLK PO L FOR/ REV CLK STB A1 to A6 B6 to B1 Type NC Supply Ground Ground Ground Output Output Input Input Input Input Input Input Input Input/Output Input/Output High Voltage Supply of Power Outputs 5V Logic Supply Ground of Power Outputs Logic Ground Substrate Ground Power Output Power Output Power Output Blanking Input Polarity Input Selection of Shift Direction Clock of data Shift Register Latch of data to Outputs Forward Shift Register Input Forward Shift Register Output Description PIN LIST Output N° 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Pin N° 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 Output N° 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 Pin N ° 97 98 99 100 101 102 103 104 105 112 113 114 115 116 117 (Power outputs) Output N° 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 Pin N° 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 Output N ° 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 Pin N° 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 5/17 3 STV7610A Output N° 16 17 18 19 20 21 22 23 24 Pin N° 88 89 90 91 92 93 94 95 96 Output N° 40 41 42 43 44 45 46 47 48 Pin N ° 118 119 120 121 122 123 124 125 126 Output N° 64 65 66 67 68 69 70 71 72 Pin N° 4 5 6 7 8 9 10 11 12 Output N ° 88 89 90 91 92 93 94 95 96 Pin N° 28 29 30 31 32 33 34 35 36 PAD COORDINATES (in ΜM) Pad positions from the middle of the top side Name X OUT 48 OUT 47 OUT 46 OUT 45 OUT 44 OUT 43 OUT 42 OUT 41 OUT 40 OUT 39 OUT 38 OUT 37 OUT 36 OUT 35 OUT 34 74.0 210.0 346.0 482.0 618.0 754.0 890.0 1026.0 1162.0 1298.0 1434.0 1570.0 1706.0 1842.0 1993.0 Center Y 3034.0 3034.0 3034.0 3034.0 3034.0 3034.0 3034.0 3034.0 3034.0 3034.0 3034.0 3034.0 3034.0 3034.0 3034.0 X 80.0 80.0 80.0 80.0 80.0 80.0 80.0 80.0 80.0 80.0 80.0 80.0 80.0 80.0 80.0 Size Y 90.0 90.0 90.0 90.0 90.0 90.0 90.0 90.0 90.0 90.0 90.0 90.0 90.0 90.0 90.0 Name X OUT 33 OUT 32 OUT 31 OUT 30 OUT 29 OUT 28 OUT 27 OUT 26 OUT 25 OUT 24 OUT 23 OUT 22 OUT 21 OUT 20 OUT 19 OUT 18 OUT 17 Size Y 2795.0 2496.5 1843.0 X 90.0 90.0 90.0 Y 80.0 90.0 80.0 OUT 16 OUT 15 OUT 14 OUT 13 OUT 12 OUT 11 2117.0 2117.0 2117.0 2117.0 2117.0 2117.0 2117.0 2117.0 2117.0 2117.0 2117.0 2117.0 2117.0 2117.0 2117.0 2117.0 2117.0 2117.0 2117.0 2117.0 2117.0 2117.0 2117.0 Y 1580.0 1444.0 1308.0 1172.0 1036.0 900.0 764.0 628.0 492.0 356.0 220.0 84.0 2117.0 2117.0 -324.0 -460.0 -596.0 -732.0 -868.0 -1004.0 -1140.0 -1276.0 -1412.0 X 90.0 90.0 90.0 90.0 90.0 90.0 90.0 90.0 90.0 90.0 90.0 90.0 90.0 90.0 90.0 90.0 90.0 90.0 90.0 90.0 90.0 90.0 90.0 Y 80.0 80.0 80.0 80.0 80.0 80.0 80.0 80.0 80.0 80.0 80.0 80.0 80.0 80.0 80.0 80.0 80.0 80.0 80.0 80.0 80.0 80.0 80.0 Center Size Pad positions along the right side Center Name VSSP VPP VPP X 2116.0 2029.8 2041.5 6/17 3 STV7610A Center Name OUT 10 OUT 9 OUT 8 OUT 7 OUT 6 OUT 5 OUT 4 OUT 3 OUT 2 OUT 1 X 2117.0 2117.0 2117.0 2117.0 2117.0 2117.0 2117.0 2117.0 2117.0 2117.0 Y -1548.0 -1684.0 -1820.0 -1956.0 -2092.0 -2228.0 -2364.0 -2500.0 -2636.0 -2832.0 X 90.0 90.0 90.0 90.0 90.0 90.0 90.0 90.0 90.0 90.0 Size Y 80.0 80.0 80.0 80.0 80.0 80.0 80.0 80.0 80.0 80.0 Name A3 A2 A1 STB CLK GNDsub GND VCC F/R POL BLK Size Y X 80.0 80.0 80.0 80.0 80.0 Y 90.0 90.0 90.0 90.0 90.0 B1 B2 B3 B4 B5 B6 VPP VSSP X Center Y -3034.0 -3034.0 -3034.0 -3034.0 -3034.0 -3034.0 -3034.0 -3034.0 -3034.0 -3034.0 -3034.0 -3034.0 -3034.0 -3034.0 -3034.0 -3034.0 -3034.0 -3034.0 -3034.0 X 80.0 80.0 80.0 80.0 80.0 80.0 80.0 80.0 80.0 80.0 80.0 80.0 80.0 80.0 80.0 80.0 80.0 80.0 80.0 Size Y 90.0 90.0 90.0 90.0 90.0 90.0 90.0 90.0 90.0 90.0 90.0 90.0 90.0 90.0 90.0 90.0 90.0 90.0 90.0 1049.0 899.0 749.0 449.0 299.0 156.5 3.0 -158.0 -299.0 -449.0 -599.0 -749.0 -899.0 -1049.0 -1199.0 -1349.0 -1499.0 -1698.0 -1904.0 Pad positions along the bottom side Center Name X VSSP VPP A6 A5 A4 1904.0 1698.0 1499.0 1349.0 1199.0 -3034.0 -3034.0 -3034.0 -3034.0 -3034.0 7/17 3 STV7610A Pad Positions along the left side Name X OUT 96 OUT 95 OUT 94 OUT 93 OUT 92 OUT 91 OUT 90 OUT 89 OUT 88 OUT 87 OUT 86 OUT 85 OUT 84 OUT 83 OUT 82 OUT 81 OUT 80 OUT 79 OUT 78 OUT 77 OUT 76 OUT 75 OUT 74 OUT 73 OUT 72 OUT 71 OUT 70 -2117.0 -2117.0 -2117.0 -2117.0 -2117.0 -2117.0 -2117.0 -2117.0 -2117.0 -2117.0 -2117.0 -2117.0 -2117.0 -2117.0 -2117.0 -2117.0 -2117.0 -2117.0 -2117.0 -2117.0 -2117.0 -2117.0 -2117.0 -2117.0 -2117.0 -2117.0 -2117.0 Center Y -2832.0 -2636.0 -2500.0 -2364.0 -2228.0 -2092.0 -1956.0 -1820.0 -1684.0 -1548.0 -1412.0 -1276.0 -1140.0 -1004.0 -868.0 -732.0 -596.0 -460.0 -324.0 -188.0 -52.0 84.0 220.0 356.0 492.0 628.0 764.0 X 90.0 90.0 90.0 90.0 90.0 90.0 90.0 90.0 90.0 90.0 90.0 90.0 90.0 90.0 90.0 90.0 90.0 90.0 90.0 90.0 90.0 90.0 90.0 90.0 90.0 90.0 90.0 Size Y 80.0 80.0 80.0 80.0 80.0 80.0 80.0 80.0 80.0 80.0 80.0 80.0 80.0 80.0 80.0 80.0 80.0 80.0 80.0 80.0 80.0 80.0 80.0 80.0 80.0 80.0 80.0 OUT 63 OUT 62 OUT 61 OUT 60 OUT 59 OUT 58 OUT 57 OUT 56 OUT 55 OUT 54 OUT 53 OUT 52 OUT 51 OUT 50 OUT 49 Name OUT 69 OUT 68 OUT 67 OUT 66 OUT 65 OUT 64 VPP VPP VSSP X Center Y 900.0 1036.0 1172.0 1308.0 1444.0 1580.0 1843.0 2496.5 2795.5 X 90.0 90.0 90.0 90.0 90.0 90.0 90.0 90.0 90.0 Size Y 80.0 80.0 80.0 80.0 80.0 80.0 80.0 80.0 80.0 -2117.0 -2117.0 -2117.0 -2117.0 -2117.0 -2117.0 -2041.5 -2029.8 2116.0 Pad Positions along the top side Name X -1980.0 -1830.0 -1694.0 -1558.0 -1422.0 -1286.0 -1150.0 -1014.0 -878.0 -742.0 -606.0 -470.0 -334.0 -198.0 -62.0 Center Y 3034.0 3034.0 3034.0 3034.0 3034.0 3034.0 3034.0 3034.0 3034.0 3034.0 3034.0 3034.0 3034.0 3034.0 3034.0 X 80.0 80.0 80.0 80.0 80.0 80.0 80.0 80.0 80.0 80.0 80.0 80.0 80.0 80.0 80.0 Size Y 90.0 90.0 90.0 90.0 90.0 90.0 90.0 90.0 90.0 90.0 90.0 90.0 90.0 90.0 90.0 8/17 3 STV7610A BLOCK DIAGRAM CLK 56 FOR/REV 52 VCC 16-BIT SHIFT REGISTER A1 59 P1 P91 49 B1 16-BIT SHIFT REGISTER A2 60 P2 P92 48 B2 16-BIT SHIFT REGISTER A3 61 P3 P93 47 B3 16-BIT SHIFT REGISTER A4 62 P4 P94 46 B4 16-BIT SHIFT REGISTER A5 63 P5 P95 45 B5 A6 64 16-BIT SHIFT REGISTER P6 P96 44 B6 P1 P6 P95 P96 STB 57 Q1 Q2 LATCH Q95Q96 54 VSSLOG 55 VSSSUB 53 VCC VCC POL 50 VCC BLK 51 LOGIC VSSP Pins 40-68-109-144 VPP Pins 1-2-42-66-107-108 73 OUT1 36 OUT96 STV7610A 9/17 3 STV7610A CIRCUIT DESCRIPTION The STV7610A contains all the logic and the power circuits necessary to drive the columns of a Plasma Display Panel (P. D. P.). The binary value of each pixel of the displayed line is loaded into the shift register. Data are input in a 6-bit wide data bus to A1 - A6 input (case of forward shift mode). Data are shifted at each low to high transition of the CLK shift clock. After 16 shifts the first data are available on B1 - B6 outputs. These B1 - B6 outputs can be used to cascade several drivers to perform any horizontal resolution. The forward/ reverse (FOR/ REV ) input is used to select the direction of the shift register, A1 - A6 and B1 - B6 data bus input/output status is set according to the selected direction. FOR/ REV = H, A is an input and B is an output. Serial inputs, CLK, STB inputs are Smith trigger inputs. If not used in the application, Blanking ( BLK ), Polarity (POL are internaly pulled to level ”H”. The maximum frequency of the shift clock is 20 MHz. This leads to an equivalent 120 MHz serial shift register. On low level of STB, data is transferred from shift register to the latch stage. Data will not be refreshed as long as STB is kept high. Blanking input ( BLK ) forces the power outputs to low level when pulled low. All the power outputs are set at high level when the Polarity command ( POL) is pulled low and the Blanking ( BLK ) input is at high level. VSSSUB and VSSLOG must be connected as close as possible to the logical reference ground of the application. Shift Register Truth Table Input FOR/ REV H H L L CLK Rise H or L Rise H or L Input/Outp ut A IN IN OUT OUT B OUT OUT IN IN Shift Register Function Output Q Forward shift Steady Reverse shift Steady Power Output Truth Table Qn X X X L H STB X X H L L BL K L H H H H PO L X L H H H Driver Output L H Qn L H Comments Output low Output high Data latched Data copied Data copied Note 1 Qn+1 = A1, Qn + 2 = A2, Qn + 3 = A3, Qn + 4 = A4, Qn + 5 = A5, Qn + 6 = A6, n = [0,6,12,18,...,90] 10/17 3 STV7610A ABSOLUTE MAXIMUM RATINGS Symbol VCC OUTi Parameter Logic Supply Range (Pin 53) Output Pins (4 to 36, 73 to 105, 112 to 141) Logic Input Voltage (Pins 50, 51, 52, 56, 57, 59 to 64) Logic Output Voltage (Pin 44 to 49) Driver Output Current ( Note 2) ( Note 4) Diode Output Current ( Note 3) ( Note 4) Junction Temperature Operating Temperature Storage Temperature Value -0.3, +7 -0.3, +100 -0.3, +VCC +0.3 -0.3, +VCC + 0.3 -60/ +50 -50/ +60 +150 -20, +85 -50, +150 Unit V V V V mA mA °C °C °C VIN V OUT IPOUT IDOUT Tj Toper Tstg Note 2 Through one power output (all power outputs). Note 3 Through one power output for all power outputs (see Test Diagram) with Junction temperature lower or equal than Tjmax. Note 4 These parameters are measured during ST’s internal qualification which includes temperature characterisation on standard batches and on corners batches of the process. These parameters are not tested on the parts. THERMAL DATA Symbol R th(j-a) Parameter Junction-ambient Thermal Resistance Typ. Value 41 Unit °C/W 11/17 3 STV7610A ELECTRICAL CHARACTERISTICS (VCC = 5 V, VPP = 90 V, VSSP = 0 V, VSSLOG = 0 V, VSSSUB = 0 V, Tamb = 25°C, fCLK = 20 MHz, unless otherwise specified) Symbol SUPPLY VCC ICCH ICCL VPP IPPH Logic Supply Voltage Logic Supply Current (all inputs high) Logic Dynamic Supply Current Power Output Supply Voltage Power Output Supply Current (steady outputs) fCLK = 20 MHz 4.5 15 5 26 5.5 100 90 100 V µA mA V µA Parameter Test Conditio ns Min. Typ. Max. Unit OUTPUT (VPP = 15 V to 90 V) OUT 1- OUT 96 VPOUTH VPOUTL VDOUTH VDOUTL Power Output Voltage Drop (High Level) (versus VPP) Power Output Voltage Drop (Low Level) Output Diode Voltage (High Level) Output Diode Low Level IPOUTH = - 30 mA IPOUTH = - 45mA IPOUTL = + 30 mA IDOUTH = +45 mA ( Note 5) IDOUTL = - 30mA ( Note 5) 4.0 4.5 1.6 1.05 -0.95 6.0 6.5 4 4 -4 V V V V V A1-A6, B1-B6 VOH VOL INPUT CLK, FOR/ REV , STB, PO L , BLK , A1-A6, B1-B6 VIH VIL IIH I IL Input Voltage (High Level) Input Voltage (Low Level) High Level Input Current Low Level Input Current CLK, A1-A6, B1-B6, STB, FOR/ REV , BLK , PO L VIH = VCC VIL = 0 V -10 -40 0.8 VCC 0.2VCC 10 V V µA µA µA Logic Output (High Level) Logic Output (Low Level) IOH = -1 mA IOL = +1 mA 4 4.2 0.12 0.4 V V Note 5 See test diagram page 14. 12/17 3 STV7610A AC TIMINGS REQUIREMENTS (VCC = 4.5 V to 5.5 V, Tamb = -20 to +85°C, input signals max leading edge & trailing edge (tR, tF) = 10 ns) Symbol tWHCLK tWLCLK tSDAT tHDAT tSFR tDSTB tSSTB tSTB tBLK tPOL Parameter Duration of clock (CLK) pulse at high level Duration of clock (CLK) pulse at low level Set-up Time of data input before clock (low to high) transition Hold Time of data input after clock (low to high) transition Forward/ reverse (FOR/ REV ) Set-up Time before clock (low to high) transition Minimum Delay to latch ( ST B ) after clock (low to high) transition Minimum Delay to latch ( ST B ) before clock (low to high) transition Latch ( ST B ) Low Level Pulse Duration Blanking ( BLK ) Pulse Duration Polarity ( PO L ) Pulse Duration Min. 15 15 10 10 100 10 10 20 500 500 ns ns ns ns ns Typ. Max. Unit ns ns ns ns AC TIMINGS CHARACTERISTICS (VCC = 5 V, VPP = 90 V, VSPP = 0 V, VSSLOG = 0 V, VSSSUB = 0 V, Tamb = 25°C) (VIL(Max.) = 0.2 Vcc, VIH(Min.) = 0.8 VCC , VOH = 4.0V, V OL = 0.4 V, unless otherwise specified) Symbol tCLK tRDAT tFDAT tPHL1 tPLH1 tPHL2 tPLH2 tPHL3 tPLH3 tPHL4 tPLH4 Data clock Period Logical Data Output Rise Time (CL=10pF) Logical Data Output Fall Time (CL=10pF) Delay of logic data output (high to low transition) after clock (CLK) transition Delay of logic data output (low to high transition) after clock (CLK) transition Delay of power output change (high to low transition) after clock (CLK) transition Delay of power output change (low to high transition) after clock (CLK) transition Delay of power output change (high to low transition) after Latch (STB) transition Delay of power output change (low to high transition) after Latch (STB) transition Delay of power output change (high to low transition) to Blank or Polarity ( BLK , PO L ) transition Delay of power output change (low to high transition) to Blank or Polarity ( BLK , PO L ) transition Power Output Rise Time ( Note 6) Power Output Fall Time ( Note 6) Parameter Min. Typ. Max. Unit 50 12 11 30 30 135 80 115 70 100 55 20 20 50 50 180 180 165 165 160 160 ns ns ns ns ns ns ns ns ns ns ns tROUT tFOUT - 50 80 150 200 ns ns Note 6 One output among 96, loading capacitor CL = 50pF, other outputs at low level. 13/17 3 STV7610A Figure 1. : AC Characteristics Waveform tCLK tWHCLK tWLCLK “1” CLK 50% 50% tSDAT 50% “0” tHDAT “1” A INPUT 50% 50% “0” tFDAT 90% B OUTPUT 10% tRDAT tSTB STB tDSTB “1” 50% 50% “0” tSSTB tSFR “1” 10% tPLH1 “0” 90% tPHL1 “1” F/R “0” tPHL3 90% 10% tPLH3 tBLK “1” BLK (POL=#0#) 50% 50% “0” tPHL4 OUTn 90% 10% tF OUT 10% tR OUT tPLH4 90% “1” tPHL2 “1” OUTn 90% 10% tPLH2 “0” “0” 14/17 3 STV7610A Figure 2. : Test Configuration V PP=VSSP VPP=V SSP VDOUTH IDOUTH VDOUTL VSSP VSSP IDOUTL Output sinking current as positive value, sourcing current as negative value INPUT/OUTPUT SCHEMATICS Figure 3. : PO L , BLK , F/ R Input VCC Figure 5. : A1 to A6, B1 to B6 VCC VCC A1 to A6, B1 to B6 Pins 59 to 64, 49 to 44 VCC VCC POL, BLK, F/R Pins 51, 50, 52 GNDLOG GNDLOG GNDSUB GNDSUB Figure 4. : CLK, STB Input VCC VCC Figure 6. : Power Output VPP CLK, STB Pins 56, 57 OUT1 to OUT 96 Pins 73 to 105, 112 to 141, 4 to 36 GNDLOG GNDSUB VSSP 15/17 3 STV7610A PACKAGE MECHANICAL DATA 144 PINS - THIN PLASTIC QUAD FLAT PACK (TQFP) A A2 144 e A1 109 0,076 mm 0.03 inch SEATING PLANE 1 108 36 73 E3 E1 E 37 D3 D1 D 72 L1 L 0,25 mm .010 inch GAGE PLANE K Millimeters Dimensions Min. A A1 A2 B C D D1 D3 e E E1 E3 L L1 K 0.45 0.05 1.35 0.17 0.09 22.00 20.00 17.50 0.50 22.00 20.00 17.50 0.60 1.00 0° (Min.), 7° (Max.) 0.75 0.018 1.40 0.22 Typ. Max. 1.60 0.15 1.45 0.27 0.20 0.002 0.053 0.0067 0.0035 Min. Inches Typ. Max. 0.063 0.006 0.055 0.0087 0.057 0.011 0.008 0.866 0.787 0.689 0.020 0.866 0.787 0.689 0.024 0.039 0.030 16/17 B c STV7610A Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibili ty for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This public ation supersedes and replaces all information previously suppl ied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a trademark of STMicroelectronics. © 2000 STMicroelectronics - All Rights Reserved Purchase of I C Components of STMicroelectronics, conveys a license under the Philip s I2C Patent. Rights to use these components in a I2C system, is granted provided that the system conforms to the I2C Standard Specifications as defined by Philips. STMicroelectronics GROUP OF COMPANIES Australia - Brazil - China - Finland - France - Germany - Italy - Japan - Korea - Malaysia - Malta - Mexico - Morocco - The Netherlands - Singapore - Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - U.S.A. http://www .st.com 2 17/17 4