STV7618WAF

STV7618 PLASMA DISPLAY PANEL DATA DRIVER FEATURES s s s s s s s 96 Outputs Plasma Display Driver 90V Absolute Maximum Rating 3.3V / 5V Compatible Logic -40 / 30 mA Source / Sink Output MOS 3 or 6 Bit Data Bus (40 MHz) BCD Process Packaging Adapted to Customer’s Request (DICE, COB, COF, TAB). Die ORDER CODE: STV7618/WAF (1) (1)Unsawn tested wafer DESCRIPTION STV7618 is a data driver for Plasma Display Panel (PDP) designed in the ST proprietary BCD high voltage technology. Using a 3 or 6 bit wide data bus, it can control 96 high current & high voltage outputs. The STV7618 is supplied with a separated 70V power output supply and a 5V logic supply. All command inputs are CMOS and 3.3V logic levels compatible. Version 4.2 April 2002 1/16 1 STV7618 Revision follow-up Target specification 05/2000 version 1.1 document creation 05/2000 version 1.2 few changes in figures 07/2000 version 1.3 addition of pads dimensions/coordinates, few changes in figures and electrical characteristics 02/2001 version 1.4 TBD mentions replaced with values for Vouthl and Voutlh Datasheet 06/2001 version 4.0 general update 10/2001 version 4.1 addition of die photo in cover page new pads dimensions 04/2002 version 4.2 Cover page features related to output diode current deleted New values for Source/sink output MOS: -40/30mA Absolute maximum ratings IPOUT values -150/150mA added definition and values for IDOUT -200/300mA Addition of note 4: Transient current. Spike current duration inferior to 300ns. Tested wafer disclaimer chapter added 2/15 2 STV7618 1 - BLOCK DIAGRAM CLK F/R BS A1 P1 16bit Shift register P91 A2 P2 16bit Shift register P92 A3 P3 16bit Shift register P93 A4 P4 16bit Shift register P94 A5 P5 16bit Shift register P95 A6 P6 16bit Shift register P96 Latch STB Q1 Q2 Q3 Q4 Q5 Q6 Q94 Q95 Q96 VSSLOG VSSSUB POC & & & & VCC BLK & & & & STV7618 VSSP OUT1 OUT96 VPP 3/15 STV7618 2 - DIE PIN OUT / DIE DESCRIPTION OUT56 OUT41 OUT40 y 0/0 x OUT2 OUT1 VPP VPP VSSP VSSP VSSSUB POC A6 A5 A4 A3 A2 BS A1 STB VCC F/R CLK VSSLOG BLK OUT57 OUT95 OUT96 VPP VPP VSSP VSSP 4/15 VSSLOG STV7618 3 - PADS DIMENSIONS (in µm)/ PADS POSITIONS The reference is the centre of the die (x=0, y=0) TOP SIDE from left to right Centre: X -774.478 -671.288 -568.098 -464.907 -361.718 -258.528 -155.338 -52.147 51.042 154.232 257.422 360.612 463.802 566.992 670.267 773.458 Centre: Y 2700.96 2700.96 2700.96 2700.96 2700.96 2700.96 2700.96 2700.96 2700.96 2700.96 2700.96 2700.96 2700.96 2700.96 2700.96 2700.96 BOTTOM SIDE from right to left Centre: X 773.542 670.352 567.162 463.972 360.782 258.442 155.252 52.062 -51.128 -154.318 -257.508 -360.698 -463.888 -567.078 -670.352 -773.542 Name OUT56 OUT55 OUT54 OUT53 OUT52 OUT51 OUT50 OUT49 OUT48 OUT47 OUT46 OUT45 OUT44 OUT43 OUT42 OUT41 Size:x 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 SIze: y 90 90 90 90 90 90 90 90 90 90 90 90 90 90 90 90 Name VSSLOG CLK F/R POC VCC STB BLK A1 A2 A3 A4 A5 A6 VSSSUB BS VSSLOG Centre:Y -2701.045 -2701.045 -2701.045 -2701.045 -2701.045 -2701.045 -2701.045 -2701.045 -2701.045 -2701.045 -2701.045 -2701.045 -2701.045 -2701.045 -2701.045 -2701.045 Size:x 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 SIze: y 90 90 90 90 90 90 90 90 90 90 90 90 90 90 90 90 5/15 STV7618 RIGHT SIDE from top to bottom Centre: X 892.670 892.670 892.670 892.670 892.670 892.670 892.670 892.670 892.670 892.670 892.670 892.670 892.670 892.670 892.670 892.670 892.670 892.670 892.670 892.670 892.670 892.670 892.670 892.670 892.670 892.670 892.670 892.670 892.670 892.670 892.670 892.670 892.670 892.670 892.670 892.670 892.670 892.670 892.670 892.670 LEFT SIDE from bottom to top Centre: X -892.670 -892.670 -892.670 -892.670 -892.670 -892.670 -892.670 -892.670 -892.670 -892.670 -892.670 -892.670 -892.670 -892.670 -892.670 -892.670 -892.670 -892.670 -892.670 -892.670 -892.670 -892.670 -892.670 -892.670 -892.670 -892.670 -892.670 -892.670 -892.670 -892.670 -892.670 -892.670 -892.670 -892.670 -892.670 -892.670 -892.670 -892.670 -892.670 -892.670 Name OUT40 OUT39 OUT38 OUT37 OUT36 OUT35 OUT34 OUT33 OUT32 OUT31 OUT30 OUT29 OUT28 OUT27 OUT26 OUT25 OUT24 OUT23 OUT22 OUT21 OUT20 OUT19 OUT18 OUT17 OUT16 OUT15 OUT14 OUT13 OUT12 OUT11 OUT10 OUT9 OUT8 OUT7 OUT6 OUT5 OUT4 OUT3 OUT2 OUT1 Centre:Y 1950.792 1847.602 1744.327 1641.138 1537.947 1434.757 1331.568 1228.378 1125.188 1021.998 918.807 815.618 712.428 609.238 506.048 402.857 299.668 196.478 93.288 -9.902 -113.092 -216.282 -319.472 -422.662 -525.852 -629.042 -732.232 -835.422 -938.612 -1041.802 -1144.992 -1248.182 -1351.372 -1454.562 -1557.752 -1660.942 -1764.132 -1867.322 -1970.512 -2073.702 Size:x 90 90 90 90 90 90 90 90 90 90 90 90 90 90 90 90 90 90 90 90 90 90 90 90 90 90 90 90 90 90 90 90 90 90 90 90 90 90 90 90 SIze: y 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 Name VSSP VSSP VPP VPP OUT96 OUT95 OUT94 OUT93 OUT92 OUT91 OUT90 OUT89 OUT88 OUT87 OUT86 OUT85 OUT84 OUT83 OUT82 OUT81 OUT80 OUT79 OUT78 OUT77 OUT76 OUT75 OUT74 OUT73 OUT72 OUT71 OUT70 OUT69 OUT68 OUT67 OUT66 OUT65 OUT64 OUT63 OUT62 OUT61 Centre:Y -2486.208 -2383.018 -2279.912 -2176.722 -2073.702 -1970.512 -1867.322 -1764.132 -1660.942 -1557.752 -1454.562 -1351.372 -1248.182 -1144.992 -1041.802 -938.612 -835.422 -732.232 -629.042 -525.852 -422.662 -319.472 -216.282 -113.092 -9.902 93.288 196.478 299.668 402.857 506.048 609.238 712.428 815.618 918.807 1021.998 1125.188 1228.378 1331.568 1434.757 1537.947 Size:x 90 90 90 90 90 90 90 90 90 90 90 90 90 90 90 90 90 90 90 90 90 90 90 90 90 90 90 90 90 90 90 90 90 90 90 90 90 90 90 90 SIze: y 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 6/15 STV7618 Centre: X 892.670 892.670 892.670 892.670 Centre: X -892.670 -892.670 -892.670 -892.670 Name VPP VPP VSSP VSSP Centre:Y -2176.722 -2279.912 -2383.018 -2486.208 Size:x 90 90 90 90 SIze: y 75 75 75 75 Name OUT60 OUT59 OUT58 OUT57 Centre:Y 1641.138 1744.327 1847.602 1950.792 Size:x 90 90 90 90 SIze: y 75 75 75 75 7/15 STV7618 4 - DATA BUS CONFIGURATION BS F/R Input CLK A1 A2 L L A3 A4 A5 A6 A1 A2 L H A3 A4 A5 A6 Out Out Out Out Out Out Out Out Out Out Out Out 01 01 02 03 04 05 06 91 92 93 94 95 96 02 07 08 09 10 11 12 85 86 87 88 89 90 03 13 14 15 16 17 18 79 80 81 82 83 84 04 19 20 21 22 23 24 73 74 75 76 77 78 05 25 26 27 28 29 30 67 68 69 70 71 72 Data Shift 06 31 32 33 34 35 36 61 62 63 64 65 66 ... 11 61 62 63 64 65 66 31 32 33 34 35 36 12 67 68 69 70 71 72 25 26 27 28 29 30 13 73 74 75 76 77 78 19 20 21 22 23 24 14 79 80 81 82 83 84 13 14 15 16 17 18 15 85 86 87 88 89 90 07 08 09 10 11 12 16 91 92 93 94 95 96 01 02 03 04 05 06 Reverse Shift Forward Shift CLK A1 H L A2 A3 A1 H H A2 A3 Out Out Out Out Out Out 01 01 02 03 94 95 96 02 04 05 06 91 92 93 03 07 08 09 88 89 90 04 10 11 12 85 86 87 05 13 14 15 82 83 84 06 16 17 18 79 80 81 ... 27 79 80 81 16 17 18 28 82 83 84 13 14 15 29 85 86 87 10 11 12 30 88 89 90 07 08 09 31 91 92 93 04 05 06 32 94 95 96 01 02 03 Reverse Forward This table describes the position of the first data sampled by the first rising edge of the CLK signal. For the first configuration described in the above table, (BS = “L” and F/R= “L”), data on A1 bus sampled by the 1st clock pulse is applied on Output1. After 16 clock pulses this data will be shifted to Output 91. 8/15 STV7618 5 - PIN DESCRIPTION Symbol OUT(01-96) VSSP VPP BLK POC F/R BS VCC VSSLOG VSSSUB CLK STB IN (A1-A6) IN (A1-A3) Function Output Ground Supply Input Input Input Input Supply Ground Ground Input Input Input Input Power output Ground of power outputs High voltage supply of power outputs Blanking input Power output control input Selection of shift direction Selection of 3/6 bits shift register 5V logic supply Logic ground Substrate ground Clock of data shift register Latch of data to outputs Shift register input for BS = “L” Shift register input for BS = “H” Description 9/15 STV7618 6 - CIRCUIT DESCRIPTION STV7618 includes all the logic and power circuits necessary to drive column electrodes of a Plasma Display Panel (P. D. P.). Binary values of each pixel of the displayed line are loaded into the shift register by a 6 bits wide (A1 - A6) or 3 bits wide (A1 A3) data bus depending on the configuration of the BS input pin. Data is shifted at each low to high transition of the CLK clock. The forward /reverse (F/R) input is used to select the direction of the shift register. The BS input is used to configure the shift register either in 3 x 32 bits or in 6 x 16 bits. In case of a 3bits arrangement, A1, A2 and A3 data bus input pins are used. The 3 shift registers are loaded with 32 clock pulses. A4, A5 and A6 data bus input pins are at high impedance status. Table 1: Shift register truth table Input BS X X X X H L F/R L L H H X X CLK rise H or L rise H or L X X Shift register function Output Q Forward shift Steady Reverse shift Steady 3 bits shift register 6 bits shift register The maximum frequency of the shift clock is 40MHz. This leads to an equivalent 240 MHz serial shift register for a 6 x 16 bits arrangement. When the STB signal is Low, data are transferred from the shift register to the latch and power output stages. All the output data are kept memorised and held in the latch stage when the latch input STB is pulled high. Vsssub and Vsslog must be connected as close as possible to the logical reference ground of the application. STV7618 is supplied with a 5 volt power supply. All the logic inputs can be driven either by 5V CMOS logic, or by 3.3V CMOS logic. Table 2: Power output truth table Qn X X X L H STB X X H L L BLK L H H H H POC X L H H H Driver Output all L all H Qn L H Comments Output at low level Output at high level Data latched Data copied Data copied Qn+1 = A1, Qn+2 = A2, Qn+3 = A3, Qn+4 = A4, Qn+5 = A5, Qn+6 = A6, n = [0,6,12,18,...,90] and BS = “L” 10/15 STV7618 7 - ABSOLUTE MAXIMUM RATINGS Symbol Vcc Vpp Vin Ipout Idout Tjmax Tstg Toper Vout Logic supply range Driver supply range Logic input voltage range Driver Output Current ( Note 1) ( Note 3) ( Note 4) Diode Output Current ( Note 2) ( Note 3) ( Note 4) Maximum junction temperature Storage temperature range Operating ambient temperature Output power voltage range Parameter Value -0.3, +7 -0.3, +90 -0.3, Vcc+0.3 -150 / +150 -200 / +300 125 -50, +150 -20, +85 -0.3, +90 Unit V V V mA mA °C °C °C V Note 1 Through one power output (all power outputs). Note 2 Through one power output for all power outputs (see Test Diagram) with Junction temperature lower or equal than Tjmax. Note 3 These parameters are measured during ST’s internal qualification which includes temperature characterisation on standard batches and on corners batches of the process. These parameters are not tested on the parts. Note 4 Transient current. Spike current duration inferior to 300ns. 11/15 STV7618 ELECTRICAL CHARACTERISTICS (Vcc = 5V, Vpp = 70V, Vssp = 0V, Vss = 0V, Tamb = 25°C, FCLK = 40 MHz, unless otherwise specified) Symbol SUPPLY Vcc Icc Iccl Icc Vpp Vpp Ipph OUTPUT OUT1-OUT96 Vpouth Power output high level (voltage drop versus Vpp) @Ipouth = - 25mA and Vpp = 70V Power output low level @ Ipoutl = + 25mA Output diode voltage drop @ Idouth = + 30mA (Note 7) Output diode voltage drop @ Idoutl = - 30mA (Note 7) 11 16 V Logic supply voltage Logic supply current (Note 5) Logic Dynamic Supply Current (FCLK=20Mhz) (Note 6) Logic Supply Current (Vih=2.0V) Power output supply voltage - DC mode Power output supply voltage - AC mode Power output supply current (steady outputs) 15 15 4.50 20 500 5 5.5 100 750 70 75 100 V µA mA µA V V µA Parameter Min Typ Max Unit Vpoutl - 8 13 V Vdouth - 1 2 V Vdoutl INPUT -2 -1 - V CLK, F/R, STB, POC, BLK, BS, A1-A6 Vih Vil Iih Iil Cin Note 5: Note 6: Note 7: Note 8: Input high level Input low level High level input current (Vih >=2.0V) Low level input current (Vil = 0v) Input capacitance (Note 8) 2.0 0.9 5 5 15 V V µA µA pF Logic input levels compatible with 5V CMOS logic All data inputs are commuted at 10MHz see Figure 2.Test configuration page15 This parameter is measured during ST’s internal qualification which includes temperature characterization on standard and corner batches of the process. This parameter is not tested on the part. 12/15 STV7618 AC TIMING REQUIREMENTS (Vcc = 4.5v to 5.5v, T amb = -20 to +85°C, input signals max leading edge & trailing edge (tr,tf) = 5ns) Symbol tCLK tWHCLK tWLCLK tSDAT tHDAT tHSTB tSTB tSSTB Data clock period Duration of CLK pulse at high level Duration of CLK pulse at low level Set-up time of data input before low to high clock transition Hold-time of data input after low to high clock transition Hold-time of STB after low to high clock transition STB low level pulse duration STB set-up time before CLK rise Parameter Min 25 10 10 5 5 5 10 5 Typ Max Unit ns ns ns ns ns ns ns ns AC TIMING CHARACTERISTICS (Vcc = 5V, Vpp = 70V, Vssp = 0V, Vsssub = 0V, Vsslog = 0V, Tamb = 25°C, FCLK = 40MHz,) ( Vilmax = 0.2Vcc, Vihmin = 0.8Vcc) Symbol tPHL1 tPLH1 tPHL2 tPLH2 tPHL3 tPLH3 tR OUT tF OUT Parameter Delay of power output change after CLK transition - high to low - low to high Delay of power output change after STB transition - high to low - low to high Delay of power output change after BLK, POC transition - high to low - low to high Power output rise time (Note 9) Power output fall time (Note 9) 50 50 25 20 90 120 90 90 200 200 ns ns ns ns 30 25 95 95 ns ns 35 30 100 100 ns ns Min Typ Max Unit Note 9: one output among 96, loading capacitor CL = 50pF, other outputs at low level 13/15 STV7618 Figure 1. AC Characteristics Waveform tCLK tWHCLK tWLCLK “1” CLK “0” tSDAT tHDAT “1” A INPUT 50% 50% “0” tSTB STB tHSTB “1” 50% 50% “0” tSSTB tPHL2 90% 10% tPLH2 tPHL1 “1” 90% 10% tPLH1 “0” OUTn “1” BLK (POC=”L”) 50% 50% “0” tPHL3 OUTn 90% 10% tF OUT 10% tR OUT tPLH3 90% “1” “0” 14/15 STV7618 Figure 2. Test configuration VPP=V SSP VPP=VSSP VDOUTH IDOUTH VDOUTL V SSP VSSP IDOUTL Output sinking current as positive value, sourcing current as negative value 8 - TESTED WAFER DISCLAIMER All wafers are tested and guaranteed to comply with all datasheet limits up to the point of wafer sawing for a period of ninety (90) days from the delivery date. We remind you that it is the customer’s responsibility to test and qualify their application in which the die is used. ST Microelectronics is ready to support the customer when qualifying the product. 15/15 STV7618 Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. 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