STV7620WAF

STV7620M PLASMA DISPLAY PANEL DATA DRIVER FEATURES s s s s s s s s 96 Outputs Plasma Display Driver 95V Absolute Maximum Rating Reduced EMI (Electro Magnetic Interference) 3.3 V/ 5V Compatible Logic -40 / 30mA Source / Sink Output Mos 3 or 6 Bit Data Bus (40MHz) BCD Process Packaging Adapted to Customer Request (DICE, COB, COF, TAB). DESCRIPTION STV7620M is a data driver for Plasma Display Panels (PDPs) designed in the ST’s proprietary BCD high voltage technology. A new shape of the output pulse generated by the STV7620M ensures a noticeable EMI reduction. Using a 3 or 6 bit wide data bus, the STV7620M can control 96 high current, high voltage outputs. The STV7620M is supplied by a separate 80V for the power outputs and 5 V for the logic. All command inputs are CMOS and 3.3 V logic level compatible. DIE ORDER CODE: STV7620M/WAF(1) (1) tested wafer Please contact STMicroelectronics for ordering information concerning samples or bump version 26 February 2004 This is preliminary information on a new product now in development. Details are subject to change without notice. 1/17 1 STV7620M Revision follow-up Target specification 02/2001 version 1.0 document creation 03/2001 version 1.1 general update, addition of EMI and figure 1 04/2001 version 1.2 general update, new pads dimensions 10/2001 version 1.3 addition of die photo in cover page, new pads dimensions Electrical characteristics: replaced a few TBD mentions with values AC timing characteristics: some TBD replaced with values F/R replaced with F/R Electrical characteristics: Idoutl/h value replaced with ±30mA Preliminary data 02/2002 version 3.0 whole document: sales type becomes STV7620M for slow, medium, fast general update 04/02/2002 version 3.1 general update 05/22/2002 version 3.2 issued from version 3.0 Addition of input/output schematics 04/2003 version 3.3 sales type changed to STV7620M general updates 04/2003 version 3.4 general updates 05/2003 version 3.5 Page 1, Description paragraph, power output supply changed to 80V. 10/2003 version 3.6 added section 4 BUMP DIMENSIONS on page 7 26 Feb. 2004 version 3.7 Page 11: Icc changed from 100 to 15 µA and Ipph from 100 to 10 µA 2/17 2 STV7620M 1 BLOCK DIAGRAM Figure 1. STV7620M block diagram CLK F/R BS A1 P1 16bit Shift register P91 A2 P2 16bit Shift register P92 A3 P3 16bit Shift register P93 A4 P4 16bit Shift register P94 A5 A6 P5 16bit Shift register P95 P6 16bit Shift register P96 VSSLOG STB Q1 Q2 Q3 Q4 Q5 Q6 LATCH Q94 Q95 Q96 VSSSUB POC & & & & VCC BLK & & & & VSSP OUT1 OUT96 VPP 3/17 STV7620M 2 DIE PIN OUT / DIE DESCRIPTION 2.06 OUT56 OUT41 OUT40 y 0/0 x OUT2 OUT1 VPP VPP VSSP VSSP VSSSUB POC BS A6 A5 A4 A3 A2 A1 STB VCC F/R VSSLOG BLK CLK OUT57 5.68 OUT95 OUT96 VPP VPP VSSP VSSP 4/17 VSSLOG STV7620M 3 PADS DIMENSIONS (in µm)/ PADS POSITIONS The reference is the centre of the die (x=0, y=0) Pad size is specified for wire-bonding options . TOP SIDE from left to right Name OUT56 OUT55 OUT54 OUT53 OUT52 OUT51 OUT50 OUT49 OUT48 OUT47 OUT46 OUT45 OUT44 OUT43 OUT42 OUT41 Centre:X -773.670 -670.480 -567.290 -464.100 -360.910 -257.720 -154.530 -51.340 51.850 155.040 258.230 361.420 464.610 567.800 669.460 772.650 Centre:Y 2695.987 2695.987 2695.987 2695.987 2695.987 2695.987 2695.987 2695.987 2695.987 2695.987 2695.987 2695.987 2695.987 2695.987 2695.987 2695.987 Size:x 76.330 76.330 76.330 76.330 76.330 76.330 76.330 76.330 76.330 76.330 76.330 76.330 76.330 76.330 76.330 76.330 SIze: y 102.425 102.425 102.425 102.425 102.425 102.425 102.425 102.425 102.425 102.425 102.425 102.425 102.425 102.425 102.425 102.425 BOTTOM SIDE from right to left Name Vsssub BS Vsslog Centre:X -567.885 -669.545 -771.630 Centre:Y -2695.988 -2695.988 -2695.988 Size:x 76.330 76.330 76.330 SIze: y 102.425 102.425 102.425 RIGHT SIDE from top to bottom Name OUT40 OUT39 OUT38 OUT37 OUT36 OUT34 OUT33 OUT32 OUT31 OUT30 OUT29 OUT28 Centre:X 887.612 887.612 887.612 887.612 887.612 887.612 887.612 887.612 887.612 887.612 887.612 887.612 887.612 887.612 887.612 887.612 887.612 887.612 887.612 887.612 887.612 887.612 887.612 887.612 887.612 887.612 Centre:Y 1949.985 1846.795 1745.135 1641.945 1538.755 1332.375 1229.185 1125.995 1022.805 919.615 816.425 713.235 610.045 506.855 403.665 300.475 197.285 94.095 -9.095 -112.285 -215.475 -318.665 -421.855 -525.045 -628.235 -731.425 Size:x 102.425 102.425 102.425 102.425 102.425 102.425 102.425 102.425 102.425 102.425 102.425 102.425 102.425 102.425 102.425 102.425 102.425 102.425 102.425 102.425 102.425 102.425 102.425 102.425 102.425 102.425 SIze: y 76.330 76.330 76.330 76.330 76.330 76.330 76.330 76.330 76.330 76.330 76.330 76.330 76.330 76.330 76.330 76.330 76.330 76.330 76.330 76.330 76.330 76.330 76.330 76.330 76.330 76.330 BOTTOM SIDE from right to left Name Vsslog Clk F/R Pol Vcc Stb Blk A1 A2 A3 A4 A5 A6 Centre:X 771.630 669.545 566.355 463.165 359.975 257.635 154.445 51.255 -51.935 -155.125 -258.315 -361.505 -464.695 Centre:Y -2695.988 -2695.988 -2695.988 -2695.988 -2695.988 -2695.988 -2695.988 -2695.988 -2695.988 -2695.988 -2695.988 -2695.988 -2695.988 Size:x 76.330 76.330 76.330 76.330 76.330 76.330 76.330 76.330 76.330 76.330 76.330 76.330 76.330 SIze: y 102.425 102.425 102.425 102.425 102.425 102.425 102.425 102.425 102.425 102.425 102.425 102.425 102.425 OUT27 OUT26 OUT25 OUT24 OUT23 OUT22 OUT21 OUT20 OUT19 OUT18 OUT17 OUT16 OUT15 OUT14 5/17 STV7620M RIGHT SIDE from top to bottom Name OUT13 OUT12 OUT11 OUT10 OUT9 OUT8 OUT7 OUT6 OUT5 OUT4 OUT3 OUT2 OUT1 Vpp Vpp Vssp Vssp Centre:X 887.612 887.612 887.612 887.612 887.612 887.612 887.612 887.612 887.612 887.612 887.612 887.612 887.612 887.612 887.612 887.612 887.612 Centre:Y -834.615 -937.805 -1040.995 -1144.185 -1247.375 -1350.565 -1453.755 -1556.945 -1660.135 -1763.325 -1866.515 -1969.705 -2072.895 -2175.915 -2279.105 -2382.210 -2485.400 Size:x 102.425 102.425 102.425 102.425 102.425 102.425 102.425 102.425 102.425 102.425 102.425 102.425 102.425 102.425 102.425 102.425 102.425 SIze: y 76.330 76.330 76.330 76.330 76.330 76.330 76.330 76.330 76.330 76.330 76.330 76.330 76.330 76.330 76.330 76.330 76.330 LEFT SIDE from bottom to top Name OUT84 OUT83 OUT82 OUT81 OUT80 OUT79 OUT78 OUT77 OUT77 OUT75 OUT74 OUT73 OUT72 OUT71 OUT70 OUT69 OUT68 OUT67 Centre:X -887.612 -887.612 -887.612 -887.612 -887.612 -887.612 -887.612 -887.612 -887.612 -887.612 -887.612 -887.612 -887.612 -887.612 -887.612 -887.612 -887.612 -887.612 -887.612 -887.612 -887.612 -887.612 -887.612 -887.612 -887.612 -887.612 -887.612 -887.612 Centre:Y -834.615 -731.425 -628.235 -525.045 -421.855 -318.665 -215.475 -112.285 -9.095 94.095 197.285 300.475 403.665 506.855 610.045 713.235 816.425 919.615 1022.805 1125.995 1229.185 1332.375 1435.565 1538.755 1641.945 1745.135 1846.795 1949.985 Size:x 102.425 102.425 102.425 102.425 102.425 102.425 102.425 102.425 102.425 102.425 102.425 102.425 102.425 102.425 102.425 102.425 102.425 102.425 102.425 102.425 102.425 102.425 102.425 102.425 102.425 102.425 102.425 102.425 SIze: y 76.330 76.330 76.330 76.330 76.330 76.330 76.330 76.330 76.330 76.330 76.330 76.330 76.330 76.330 76.330 76.330 76.330 76.330 76.330 76.330 76.330 76.330 76.330 76.330 76.330 76.330 76.330 76.330 LEFT SIDE from bottom to top Name Vssp Vssp Vpp Vpp OUT96 OUT95 OUT94 OUT93 OUT92 OUT91 OUT90 OUT89 OUT88 OUT87 OUT86 OUT85 Centre:X -887.612 -887.612 -887.612 -887.612 -887.612 -887.612 -887.612 -887.612 -887.612 -887.612 -887.612 -887.612 -887.612 -887.612 -887.612 -887.612 Centre:Y -2485.400 -2382.210 -2279.105 -2175.915 -2072.895 -1969.705 -1866.515 -1763.325 -1660.135 -1556.945 -1453.755 -1350.565 -1247.375 -1144.185 -1040.995 -937.805 Size:x 102.425 102.425 102.425 102.425 102.425 102.425 102.425 102.425 102.425 102.425 102.425 102.425 102.425 102.425 102.425 102.425 SIze: y 76.330 76.330 76.330 76.330 76.330 76.330 76.330 76.330 76.330 76.330 76.330 76.330 76.330 76.330 76.330 76.330 OUT66 OUT65 OUT64 OUT63 OUT62 OUT61 OUT60 OUT59 OUT58 OUT57 6/17 STV7620M 4 BUMP DIMENSIONS 74 µm 96 µm 20 µm ≥103.2 µm Bump composition: gold 5 BS DATA BUS CONFIGURATION F/R Input CLK A1 A2 L L A3 A4 A5 A6 A1 A2 L H A3 A4 A5 A6 Out Out Out Out Out Out Out Out Out Out Out Out 01 01 02 03 04 05 06 91 92 93 94 95 96 02 07 08 09 10 11 12 85 86 87 88 89 90 03 13 14 15 16 17 18 79 80 81 82 83 84 04 19 20 21 22 23 24 73 74 75 76 77 78 05 25 26 27 28 29 30 67 68 69 70 71 72 Data Shift 06 31 32 33 34 35 36 61 62 63 64 65 66 ... 11 61 62 63 64 65 66 31 32 33 34 35 36 12 67 68 69 70 71 72 25 26 27 28 29 30 13 73 74 75 76 77 78 19 20 21 22 23 24 14 79 80 81 82 83 84 13 14 15 16 17 18 15 85 86 87 88 89 90 07 08 09 10 11 12 16 91 92 93 94 95 96 01 02 03 04 05 06 Reverse Shift Forward Shift CLK A1 H L A2 A3 A1 H H A2 A3 Out Out Out Out Out Out 01 01 02 03 94 95 96 02 04 05 06 91 92 93 03 07 08 09 88 89 90 04 10 11 12 85 86 87 05 13 14 15 82 83 84 06 16 17 18 79 80 81 ... 27 79 80 81 16 17 18 28 82 83 84 13 14 15 29 85 86 87 10 11 12 30 88 89 90 07 08 09 31 91 92 93 04 05 06 32 94 95 96 01 02 03 Reverse Forward This table describes the position of the first data sampled by the first rising edge of the CLK signal. For the first configuration described in the above table, (BS = “L” and F/R= “L”), data on A1 bus sampled by the 1st clock pulse is applied on Output1. After 16 clock pulses this data will be shifted to Output 91. 7/17 STV7620M 6 PIN DESCRIPTION Symbol OUT(01-96) VSSP VPP BLK POC F/R BS VCC VSSLOG VSSSUB CLK STB IN (A1-A6) IN (A1-A3) OUT(A4-A6) Function Output Ground Supply Input Input Input Input Supply Ground Ground Input Input Input Input output Power output Ground of power outputs High voltage supply of power outputs Blanking input Power output control input Selection of shift direction Selection of 3/6 bits shift register 5V logic supply Logic ground Substrate ground Clock of data shift register Latch of data to outputs Shift register input for BS = “L” Shift register input for BS = “H” A1, A2, A3 shift register output for BS=”H” Description 8/17 STV7620M 7 CIRCUIT DESCRIPTION The maximum frequency of the shift clock is 40MHz. This leads to an equivalent 240MHz serial shift register for a 6 x 16 bits arrangement. When the STB signal is Low, data are transferred from the shift register to the latch and the power output stages. All the output data are kept memorised and held in the latch stage when the latch input STB is pulled high. Vsssub and Vsslog must be connected as close as possible to the logical reference ground of the application. STV7620M is supplied with a 5 volt power supply. All the logic inputs can be driven either by 5V CMOS logic or by 3.3 V CMOS logic. A low EMI function has been implemented: the falling edge of the outputs has 2 slopes, a smooth one for 30ns followed by a steeper one. STV7620M includes all the logic and power circuits necessary to drive column electrodes of a Plasma Display Panel (P. D. P.). Binary values of each pixel of the displayed line are loaded into the shift register by a 6 bit wide (A1 - A6) or 3 bit wide (A1 - A3) data bus, depending on the configuration of the BS input pin. Data is shifted at each low-tohigh transition of the CLK clock. The forward/reverse (F/R) input is used to select the direction of the shift register. The BS input sets the configuration of the shift register either in 3 x 32 bits or in 6 x 16 bits. In case of a 3 bit arrangement, A1, A2 and A3 data bus input pins are used. The 3 shift registers are loaded with 32 clock pulses. A4, A5 and A6 data bus pins are the outputs of A1, A2 and A3 shift registers respectively. Table 1: Shift register truth table Input BS X X X X H L F/R L L H H X X CLK rise H or L rise H or L X X Shift register function Output Q Forward shift Steady Reverse shift Steady 3 bits shift register 6 bits shift register Table 2: Power output truth table Pn X X X L H STB X X H L L BLK L H H H H POC X L H H H Driver Output all L all H Qn L H Comments Output at low level Output at high level Data latched Data copied Data copied Pn+1 = A1, Pn+2 = A2, Pn+3 = A3, Pn+4 = A4, Pn+5 = A5, Pn+6 = A6, n = [0,6,12,18,...,90] and BS = “L” 9/17 STV7620M 8 ABSOLUTE MAXIMUM RATINGS Symbol Vcc Vpp Vin Ipout Idout Tjmax Tstg Vout Logic supply range Driver supply range Logic input voltage range Driver output current (Note 1)(Note 3) (Note 4) Diode Output Current (Note 2) (Note 3) (Note 4) Maximum junction temperature Storage temperature range Output power voltage range Parameter Value -0.3, +7 -0.3, +95 -0.3, Vcc+0.3 - 40 /+30 -200 /+300 125 -50, +150 -0.3, +90 Unit V V V mA mA °C °C V Note 1: Through one power output. Note 2: Through one power output for all power outputs (see Figure 4) with junction temperature lower than or equal to Tjmax Note 3: These parameters are measured during ST’s internal qualification which includes temperature characterisation on standard batches and on corners batches of the process. These parameters are not tested on the parts. Note 4: Transient current. Spike current duration inferior to 300ns. Caution: in accordance with the Absolute Maximum Rating System (IEC 60134), product quality may suffer if the maximum rating is exceeded even momentarily for any parameter. That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum rating are not exceeded. 10/17 STV7620M 9 ELECTRICAL CHARACTERISTICS Symbol SUPPLY Vcc Icc Iccl Icc Vpp Ipph OUTPUT OUT1-OUT96 Vpouth Vpoutl Vdouth Vdoutl INPUT CLK, F/R, STB, POC, BLK, BS, A1-A6 Vih Vil Iih Iil Iih Cin A4-A6 Voh Vol Logic output high level (Ioh = -1mA) Logic output low level (Iol = 1mA) 4.85 0.1 V V Input high level Input low level High level input current (Vih ≥ 2.0V) Low level input current (Vil = 0V) High level input current for BS (Vih = 5V) Input capacitance 2.0 20 15 0.9 5 5 V V µA µA µA pF Power output high level (voltage drop versus Vpp) @Ipouth = - 20mA and Vpp = 70V Power output low level @ Ipoutl = + 20mA Output diode voltage drop @ Idouth = + 30mA (Note 7) Output diode voltage drop @ Idoutl = - 30mA (Note 7) -2 7.5 5 1 -1 14 11 2 V V V V Logic supply voltage Logic supply current (Note 5) Logic Dynamic Supply Current (FCLK= 20Mhz) (Note 6) Logic Supply Current (Vih= 2.0V) Power output supply voltage Power output supply current (steady outputs) 15 4.50 20 500 5 5.5 15 750 80 10 V µA mA µA V µA Parameter Min. Typ Max Unit (Vcc = 5V, Vpp = 70V, Vssp = 0V, Vss = 0V, Tamb = 25°C, FCLK = 40 MHz, unless otherwise specified) Note 5: Logic input levels compatible with 5V CMOS logic Note 6: All data inputs are commuted at 10MHz Note 7: see Figure 4.Test configuration page15 11/17 STV7620M 10 AC TIMING REQUIREMENTS (Vcc = 4.5 V to 5.5V, T amb = -20 to +85°C, input signals max leading edge & trailing edge (tr,tf) = 5 ns) Symbol tCLK tWHCLK tWLCLK tSDAT tHDAT tHSTB tSTB tSSTB Data clock period Duration of CLK pulse at high level Duration of CLK pulse at low level Set-up time of data input before low to high clock transition Hold-time of data input after low to high clock transition Hold-time of STB after low to high clock transition STB low level pulse duration STB set-up time before CLK rise Parameter Min. 25 10 10 5 5 5 10 5 Typ Max Unit ns ns ns ns ns ns ns ns 12/17 STV7620M 11 AC TIMING CHARACTERISTICS (Vcc = 5V, Vpp = 70 V, Vssp = 0V, Vsssub = 0V, Vsslog = 0V, Tamb = 25°C, FCLK = 40 MHz,) (Vilmax = 0.2Vcc, Vihmin = 0.8Vcc) Symbol tPHL1 tPLH1 tPHL2 tPLH2 tPHL3 tPLH3 tR OUT tF OUT tS tR DAT tF DAT tPHL4 tPLH4 - high to low - low to high Delay of power output change after STB transition - high to low - low to high Delay of power output change after BLK, POC transition - high to low - low to high Power output rise time (Note 8) Power output fall time (Note 8) Width of the falling edge smooth shape (not tested) Logic data output rise time (CL = 10pF) Logic data output fall time (CL = 10pF) Delay of logic data output change after CLK transition - high to low - low to high 12 13 25 25 ns ns 50 50 25 20 30 9 5 90 90 200 200 20 12 ns ns ns ns ns ns ns 95 95 ns ns Parameter Delay of power output change after CLK transition 35 30 100 100 ns ns Min. Typ Max Unit Note 8: one output among 96, loading capacitor CL = 50pF, other outputs at low level 13/17 STV7620M Figure 2. AC Characteristics Waveform tCLK t WHCLK tWLCLK “1” CLK 50% 50% tSDAT 50% “0” tHDAT “1” A INPUT tPHL4 50% tF DAT 50% “0” A4, 5, 6 “BS=H” tSTB tPLH4 tHSTB tR DAT “1” STB 50% 50% “0” tSSTB tPHL2 90% 10% tPLH2 tPHL1 “1” 90% 10% tPLH1 “0” OUTn “1” BLK (POC=”L”) 50% tPHL3 50% “0” tPLH3 OUTn see Figure 3 90% 10% t F OUT 10% 90% “1” “0” tR OUT 14/17 STV7620M Figure 3. Zoom for OUTn showing tS and tF OUT tF OUT OUTn 90% 10% tS Figure 4. Test configuration VPP=VSSP VPP=VSSP VDOUTH IDOUTH VDOUTL VSSP VSSP IDOUTL Output sinking current as positive value, sourcing current as negative value 15/17 STV7620M 12 - INPUT/OUTPUT SCHEMATICS Figure 5. B/S input VCC VCC Figure 6. A4 to A6 VCC VCC A4 to A6 BS VCC GNDSUB GNDLOG GNDLOG GNDSUB GNDLOG Figure 7. CLK, STB, r/R, POC, BLK, A1 to A3 inputs VCC VCC CLK, STB, F/R POC, BLK, A1 to A3 Figure 8. Power output VPP OUT1 to OUT 96 GNDSUB GNDLOG VSSP 16/17 STV7620M Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without the express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics All other names are the property of their respective owners 2004 STMicroelectronics - All Rights Reserved. STMicroelectronics Group of Companies Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan - Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States http://www.st.com © 17/17 3