STV7623

STV7623 480 output high-voltage gate driver Features ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ 2-level high voltage output gate driver 480 channels with -40/+35 mA source/sink output current capability 75 V output swing within +/- 45 V limits 3.0 to 3.6 V digital power supply 1.8 V CMOS input signal compatibility Selectable 480 or 400 outputs Direct input to bidirectional shift registers Selectable polarity and blanking function High voltage BCD process technology Bumped dice in tray Output stage similar to STV7622 PCB-less compatible dice The STV7623 is a 1-bit x 480 shift register with dual rail high voltage/medium current output, with global blank and polarity control. The maximum shift frequency starts from 1 MHz for a 1.8 V type input signal, up to 10 MHz for a 3.3 V type input signal. This generic device can be used for segmented/dot matrix electroluminescent displays to drive an array of organic electronic transistors, or for technologies related to e-Paper/e-Reader/digital signage solutions. The device can be daisy-chained for various display resolutions. STV7623 die Description Table 1. Device summary Order code STV7623WPB3 Temperature -25°C to +70°C Package Bumped dice Packing 3-inch tray August 2011 Doc ID 018939 Rev 1 1/27 www.st.com 27 Contents STV7623 Contents 1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1.1 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2.1 2.2 2.3 Device operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Device power supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Power sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3 4 5 Truth tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Absolute maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 5.1 5.2 5.3 DC electrical characteristics (DGND = 0 V) . . . . . . . . . . . . . . . . . . . . . . . 11 AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Timing requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 6 7 8 Packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Pad information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 2/27 Doc ID 018939 Rev 1 STV7623 Description 1 Description Figure 1. STV7623 block diagram O U T1 O U T2 O U T 3 O U T4 O U T 477 O U T 47 8 O U T 479 O U T 4 8 0 VP L e v e l S h ifte r VN ^ POL ^ ^ ^ ^ ^ ^ ^ DVDD D GN D B LA N K S TV 1 4 8 0 b it s b i - d ire c tio n a l s h ift re g i s te r C LK D IR S TV 2 JU S TIF Y L E N G TH TE S T AM08731V1 Doc ID 018939 Rev 1 3/27 Description STV7623 1.1 Pin description Figure 2. PCB-Less COF pinout diagram T est20 T est19 T est18 T est17 T est16 T est15 T est14 T est13 T est12 T est11 O U T480 VP DVDD DGND VN STV2 TEST D IR C LK B LA N K POL B LA N K C LK D IR LE N G TH STV1 VN DGND DVDD VP 0U T 1 T est10 T est9 T est8 T est7 T est6 T est5 T est4 T est3 T est2 T est1 T e st2 0 T e st1 9 T e st1 8 T e st1 7 T e st1 6 T e st1 5 T e st1 4 T e st1 3 T e st1 2 T e st1 1 T est2 0 T est1 9 T est1 8 T est1 7 T est1 6 T est1 5 T est1 4 T est1 3 T est1 2 T est1 1 O u t4 8 0 O u t4 7 9 O u t4 7 8 O u t4 7 7 - O U T 480 VP DVDD DGND VN STV2 TEST D IR DVDD C LK B LA N K POL DGND POL B LA N K C LK JU S TIF Y D IR LE N G T H STV1 VN DGND DVDD VP 0U T 1 T e st1 0 T e st9 T e st8 T e st7 T e st6 T e st5 T e st4 T e st3 T e st2 T e st1 O u t4 O u t3 O u t2 O u t1 T est1 0 T e st9 T e st8 T e st7 T e st6 T e st5 T e st4 T e st3 T e st2 T e st1 Figure 2 shows the possible design of a custom COF with wire on array (WOA) routing (PCB-less). This example supports only 480 outputs. Table 2. Pin description I/O In In Function Shift clock Input Shift direction Control pin Start pulse input/output pin Description Clock input for the chip internal shift register. Data is shifted at each rising edge of this clock. This pin controls the output shifting direction. These pins are used to control the channel start pulse input or output pin. The function of these two pins depends on the status of DIR pin (refer to the Section 3: Truth tables) This pin is used to control the channel output. When BLANK is high, the shift register is bypassed (overriden) and all driver outputs are fixed to VN level instantly, (when POL= L). It is assumed this signal affect few outputs Pin name CLK DIR STV1 STV2 I/O BLANK In Output enable control 4/27 Doc ID 018939 Rev 1 STV7623 Table 2. Pin description (continued) I/O Function Description Description Pin name POL In Polarity pin When POL is low, VP and VN are swapped functionally at the output pins level. This signal is assumed static. The output voltage is either VP or VN for driving the gate electrode, depending on the data stored in the shift register. It is assumed that only up to 4 outputs are changing level simultaneously. High voltage supply (eg +50 V) Digital power supply Digital ground Negative supply Test pin (must be grounded in application) When LENGTH =0, enable 480 outputs When LENGTH =1, enable 400 outputs This signal is assumed static Only applicable when LENGTH=1 When JUSTIFY = 0, use outputs 0 to 399 When JUSTIFY = 1, use outputs 80 to 479 This signal is assumed static. OUT1..OUT480 Out Driver output pins VP DVDD DGND VN TEST LENGTH Power Power Power Power In In Power supply Power supply Power supply Power supply Test pin Nb of active outputs JUSTIFY In Partial output justify mode In the pinout diagram: ● TEST is used to test the device. Doc ID 018939 Rev 1 5/27 Functional description STV7623 2 Functional description The STV7623 includes all the logic and power circuits necessary to drive the thin-film transistor (TFT) of an active matrix display backplane. A low-voltage logic block manages data information, and a high-voltage block converts the low-voltage information stored in the logic block into high-voltage signals applied to the display gate lines. 2.1 Device operation In the condition of DIR=L, the STV1 start pulse input is sensed at the rising edge of CLK and stored in the first stage of shift register, which causes the first scan signal is outputted from the OUT1 output pin. While stored data is transferred to the next stage of the shift register at the rising edge of the CLK signal, new data of STV1 is sensed and stored simultaneously. The output pin (OUT1 to OUT480) supplies VP or VN voltage to the gate lines depending on the data stored in the shift register. For normal operation, a VP voltage is outputted one by one like a shift token from OUT1 to OUT480, in sync with CLK pulse. STV2 goes up to high level at the 400/480th falling edge of CLK and goes down to low level at the 401/481th falling edge of CLK. This STV2 is connected to the next driver IC STV1 signal to cascade (daisy chain) them. When STV2 is an output, the signal is activated for 1/2 clock later. When the chip is configured in 400 output mode, only the first 400 bits entering the shift register are used, the remaining 80 outputs are removed from the shift register. Figure 3. Example of input/output timing DIR = H Example of input/output timing (DIR=0) 1 CLK STV1 BLANK OUT1 OUT2 OUT3 OUT4 OUT5 OUT6 OUT480 STV2 2 3 4 5 6 7 479 480 481 482 6/27 Doc ID 018939 Rev 1 STV7623 Functional description 2.2 Device power supply The STV7623 must be used with the following conditions when operating: – – – Figure 4. VP - VN < 75 V VP-DGND > 10 V DGND-VN > 10V Device power supply Output 1 to 480 VP DVDD DGND VN Logic input AM08733V1 2.3 Power sequencing To prevent the device from being damaged by latchup, the power ON/OFF sequence it is recommended to follow the procedure below: – – Power OFF => ON: DVDD -> VN -> VP Power ON => OFF, VP -> VN -> DVDD Doc ID 018939 Rev 1 7/27 Functional description Figure 5. Power sequencing STV7623 VP DVDD D GN D VN AM08734V1 8/27 Doc ID 018939 Rev 1 STV7623 Truth tables 3 Truth tables Table 3. Output level truth table Input pins Data bit 0 1 X X 1 0 Blank 0 0 1 1 0 0 POL 1 1 1 0 0 0 OUTn VP (+) VN (-) VP (+) VN (-) VP (+) VN (-) Table 4. Output ordering truth table Configurations Comments Length 0 0 1 1 0 0 1 1 Justify 0 1 0 1 0 1 0 1 Dir 0 0 0 0 1 1 1 1 In STV1 STV1 STV1 STV1 STV2 STV2 STV2 STV2 First OUT1 OUT1 OUT1 OUT81 OUT480 OUT480 OUT400 OUT480 Last OUT480 OUT480 OUT400 OUT480 OUT1 OUT1 OUT1 OUT81 Out STV2 STV2 STV2 STV2 STV1 STV1 STV1 STV1 All outputs All outputs 1..400 81..480 All outputs All outputs 1..400 81..480 When only 400 outputs are used, the remaining 80 outputs remain static. Doc ID 018939 Rev 1 9/27 Absolute maximum rating STV7623 4 Absolute maximum rating Stressing the device above the rating listed in the “absolute maximum ratings” table may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Table 5. Symbol VDD VP VN Vp-Vn VIN Ipout Idout Vout VESD Tjmax Tstg Digital supply range Positive voltage supply Negative voltage supply Voltage difference Logic input voltage range Driver output current x(1) (2) (3) Diode output current (1) (2) (3) Absolute maximum ratings (VSS = 0 V, 25 °C) Parameter Value -0.3 to +4.0 -0.3 to +50 +0.3 to -50 90 -0.3 to DVDD+0.3 - 70 to +35 -200 to +300 -0.3 to +90 2 -40 to +100 -65 to +150 Unit V V V V mV mA mA V kV °C °C Output voltage range ESD susceptibility, human body model (100 pF discharged through 1.5 KΩ), on all except the VCC pins(4) Maximum junction temperature Storage temperature range (die) 1. Measurements done on one single output, x. The other outputs are either not used or are connected to output x. Assumes junction temperature remains less than Tjmax during measurement. 2. All transient current measurements are made under conditions close to those encountered in a typical application (that is, with duration of any output current spike always less than 300 ns). 3. These parameters are measured during STMicroelectronics’ internal qualification which includes temperature characterization on standard as well as corner batches of the process. These parameters are not tested in production. 10/27 Doc ID 018939 Rev 1 STV7623 Electrical characteristics 5 5.1 Electrical characteristics DC electrical characteristics (DGND = 0 V) DVDD = 3.3 V, VP = 30 V, VN = -45V, TAMB = 25 °C, fCLK = 1 MHz, unless otherwise specified. Table 6. Symbol DVDD IDD IDDL Electrical characteristics - supply Value Parameter Min Digital supply voltage Digital supply current(1) Digital dynamic supply current (CLK1 freq = 1 MHz)(2) Digital supply current at VIH = 2.0 V DC power output positive supply voltage DC power output negative supply voltage Voltage gap Vp-Vn Power output supply current (steady outputs) 3.0 – – Typ 3.3 60 900 Max 3.6 – – V µA µA Unit IDD VP VN VP-VN IPPH – +10 – 20 – 80 – – – – – – -10 80 500 µA V V V µA 1. For 3.3V CMOS input logic levels (0 or 3.3 V) 2. All input data is switched at 0.5 MHz rate. Table 7. Symbol Electrical characteristics - OUT1 to OUT480 Value Parameter Min Power output high level (voltage drop versus VP) at Ipouth = -20 mA and VP = 30 V Power output low level at Ipoutl = +20 mA, VN=-45 V Output upper diode voltage drop at Idouth = +30 mA Output lower diode voltage drop at Idoutl = -30 mA Typ Max Unit Vpouth – 4 – V Vpoutl Vdouth Vdoutl – – -2 6 1 -1 – 2 – V V V Doc ID 018939 Rev 1 11/27 Electrical characteristics STV7623 Table 8. Electrical characteristics - standard mode, TTL/LVCMOS inputs: CLK, DIR, blank, POL, STV1, STV2, length, justify Value Parameter Min Typ – – – – – – Max DVDD 0.6 DVdd DGND+0.3 1 1 V V V V µA µA High level input voltage Low level input voltage High level output voltage IOH = 200 µA Low level output voltage IOH = 200 µA High level input current (VIH ≥ 2.0 V) Low level input current (VIL = 0 V) 1.2 DGND DVDD-0.3 DGND -1 -1 Unit Symbol VIH VIL VOH VOL IIH IIL Figure 6. Output test configuration VP VP VN VN 12/27 Doc ID 018939 Rev 1 STV7623 Figure 7. Supply voltage (VP,VN) setting examples VP VP VP VP VP Electrical characteristics VP > 10V 0V = DGND VN < -10V VN VN VN VN VP-VN < 80V VP > 10V VN < -10V VN 5.2 AC characteristics DVDD = 3.3 V to 3.6 V, Tamb = -20°C to +85°C, input signal edge maximum rise and fall times (tr, tf) = 3 ns load condition: 68 pF, 3.9 kΩ, 333 pF. Table 9. Symbol tCLK FCLK tWHCLK tWLCLK tSDAT tHDAT AC timing requirements Value Parameter Min Data clock period Max clock frequency Duration of clock pulse at high level Duration of clock pulse at low level Input data set-up time before low-to-high clock transition Input data hold-time after low-to-high clock transition 0.1 – 400, 40(2) 400, 40(2) 25 25 Typ – 200k – – – – Max – 1M/10M(1)(2) – – – – µs Hz ns ns ns ns Unit 1. If the digital inputs are 3.3V +/-10%, max clock frequency can be 10 MHz 2. Output blanked during data shift. Test condition: 25 °C ambient, VP = +30, VN = -45 V, DVDD = 3.3 V. Doc ID 018939 Rev 1 13/27 Electrical characteristics STV7623 5.3 Timing requirements DVDD = 3.3 V, VP = +30 V, VN = -45 V, Tamb = 25 °C, Fclk= 1 MHz, VILmax = 0.2 × DVDD, VIHmin = 0.8 × DVDD Table 10. Symbol AC timing characteristics Value Parameter Min Delay of power output change after CLK transition - High to low - Low to high Delay of power output change after POL transition - High to low - Low to high Delay of power output change after BLANK transition - High to low - Low to high Typ Max Unit tPHL1 tPLH1 – 100 – ns tPHL2 tPLH2 – 100 – ns tPHL3 tPLH3 – 100 – ns 14/27 Doc ID 018939 Rev 1 STV7623 Packing information 6 Packing information Figure 8. Tray (top view) Doc ID 018939 Rev 1 15/27 Packing information Figure 9. Tray (bottom view) STV7623 16/27 Doc ID 018939 Rev 1 STV7623 Figure 10. Die orientation in tray Packing information DIE IDENTIFICATION Doc ID 018939 Rev 1 17/27 Pad information STV7623 7 Pad information Figure 11. Pad dimensions and coordinates (in µm) OT U 113 OT U 368 V P DD VD DN GD V N DN GD V N DN GD DD VD V P Y DIE FACE UP X (0,0) V P DD VD DN GD V N DN GD V N DN GD DD VD V P The reference (x=0, y=0) is the centre of the die. Output pad pitch is 68 µm. Stress relief pads are connected to VN (VSS). Pad size: ● ● ● Type 1: (north/south pads) 51 x 51 µm, 68 µm linear pitch, passivation opening 34 x 34 µm. Type 2: (east/west) pads Type 3: stress relief die corner pads Alignment: 2 alignment marks, using 2 metals across the input long edge of the die. Die size = 51 mm2, with special reticle/wafer map adjustments. 18/27 OT 2 U 11 OT U1 VP P DD VD DN GD V N SV T1 LNT E GH D IR JU T Y S IF CK L BN LA K PL O DN GD PL O BN LA K CK L DD VD D IR TS ET SV T2 V N DN GD DD VD V P OT 0 U 48 OT 9 U 36 Doc ID 018939 Rev 1 STV7623 Pad information ************************* * * * PADS extraction * * * ************************* release 1.4 Mon Mar 01 18:49:21 SGT 2010 CHIP NAME: STV7623_Top_ICPack All dimensions are in Microns. Pad Placement values correspond to each pad center coordinates. Pad Placement Origin is the center of the die. LEAD PAD NAME PAD PLACEMENTS PAD DIMENSIONS X= Y= X= Y= Note: vss! == VN line vss! OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT -8803.79 -8670.0 -8602.0 -8534.0 -8466.0 -8398.0 -8330.0 -8262.0 -8194.0 -8126.0 -8058.0 -7990.0 -7922.0 -7854.0 -7786.0 -7718.0 -7650.0 -7582.0 -7514.0 -7446.0 -7378.0 -7310.0 -7242.0 -7174.0 -7106.0 -7038.0 -6970.0 -6902.0 -6834.0 -6766.0 -6698.0 -6630.0 -6562.0 -6494.0 -6426.0 -6358.0 -6290.0 -6222.0 -6154.0 -6086.0 -6018.0 -5950.0 -5882.0 -5814.0 -5746.0 -5678.0 -5610.0 -5542.0 -5474.0 -5406.0 -5338.0 -5270.0 -5202.0 -5134.0 -5066.0 -4998.0 -4930.0 -4862.0 -4794.0 -4726.0 -4658.0 -4590.0 -4522.0 -4454.0 -4386.0 -4318.0 -4250.0 -4182.0 -4114.0 -4046.0 -3978.0 1251.455 1145.46 1145.46 1145.46 1145.46 1145.46 1145.46 1145.46 1145.46 1145.46 1145.46 1145.46 1145.46 1145.46 1145.46 1145.46 1145.46 1145.46 1145.46 1145.46 1145.46 1145.46 1145.46 1145.46 1145.46 1145.46 1145.46 1145.46 1145.46 1145.46 1145.46 1145.46 1145.46 1145.46 1145.46 1145.46 1145.46 1145.46 1145.46 1145.46 1145.46 1145.46 1145.46 1145.46 1145.46 1145.46 1145.46 1145.46 1145.46 1145.46 1145.46 1145.46 1145.46 1145.46 1145.46 1145.46 1145.46 1145.46 1145.46 1145.46 1145.46 1145.46 1145.46 1145.46 1145.46 1145.46 1145.46 1145.46 1145.46 1145.46 1145.46 73.1 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 73.1 (stress relief bump) 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 Doc ID 018939 Rev 1 19/27 Pad information OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT -3910.0 -3842.0 -3774.0 -3706.0 -3638.0 -3570.0 -3502.0 -3434.0 -3366.0 -3298.0 -3230.0 -3162.0 -3094.0 -3026.0 -2958.0 -2890.0 -2822.0 -2754.0 -2686.0 -2618.0 -2550.0 -2482.0 -2414.0 -2346.0 -2278.0 -2210.0 -2142.0 -2074.0 -2006.0 -1938.0 -1870.0 -1802.0 -1734.0 -1666.0 -1598.0 -1530.0 -1462.0 -1394.0 -1326.0 -1258.0 -1190.0 -1122.0 -1054.0 -986.0 -918.0 -850.0 -782.0 -714.0 -646.0 -578.0 -510.0 -442.0 -374.0 -306.0 -238.0 -170.0 -102.0 -34.0 34.0 102.0 170.0 238.0 306.0 374.0 442.0 510.0 578.0 646.0 714.0 782.0 850.0 918.0 986.0 1054.0 1122.0 1190.0 1258.0 1326.0 1394.0 1462.0 1530.0 1598.0 1666.0 1734.0 1802.0 1870.0 1938.0 2006.0 2074.0 2142.0 2210.0 2278.0 1145.46 1145.46 1145.46 1145.46 1145.46 1145.46 1145.46 1145.46 1145.46 1145.46 1145.46 1145.46 1145.46 1145.46 1145.46 1145.46 1145.46 1145.46 1145.46 1145.46 1145.46 1145.46 1145.46 1145.46 1145.46 1145.46 1145.46 1145.46 1145.46 1145.46 1145.46 1145.46 1145.46 1145.46 1145.46 1145.46 1145.46 1145.46 1145.46 1145.46 1145.46 1145.46 1145.46 1145.46 1145.46 1145.46 1145.46 1145.46 1145.46 1145.46 1145.46 1145.46 1145.46 1145.46 1145.46 1145.46 1145.46 1145.46 1145.46 1145.46 1145.46 1145.46 1145.46 1145.46 1145.46 1145.46 1145.46 1145.46 1145.46 1145.46 1145.46 1145.46 1145.46 1145.46 1145.46 1145.46 1145.46 1145.46 1145.46 1145.46 1145.46 1145.46 1145.46 1145.46 1145.46 1145.46 1145.46 1145.46 1145.46 1145.46 1145.46 1145.46 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 STV7623 20/27 Doc ID 018939 Rev 1 STV7623 OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT 2346.0 2414.0 2482.0 2550.0 2618.0 2686.0 2754.0 2822.0 2890.0 2958.0 3026.0 3094.0 3162.0 3230.0 3298.0 3366.0 3434.0 3502.0 3570.0 3638.0 3706.0 3774.0 3842.0 3910.0 3978.0 4046.0 4114.0 4182.0 4250.0 4318.0 4386.0 4454.0 4522.0 4590.0 4658.0 4726.0 4794.0 4862.0 4930.0 4998.0 5066.0 5134.0 5202.0 5270.0 5338.0 5406.0 5474.0 5542.0 5610.0 5678.0 5746.0 5814.0 5882.0 5950.0 6018.0 6086.0 6154.0 6222.0 6290.0 6358.0 6426.0 6494.0 6562.0 6630.0 6698.0 6766.0 6834.0 6902.0 6970.0 7038.0 7106.0 7174.0 7242.0 7310.0 7378.0 7446.0 7514.0 7582.0 7650.0 7718.0 7786.0 7854.0 7922.0 7990.0 8058.0 8126.0 8194.0 8262.0 8330.0 8398.0 8466.0 8534.0 1145.46 1145.46 1145.46 1145.46 1145.46 1145.46 1145.46 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51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 73.1 Pad information 51.0 51.0 51.0 51.0 73.1 (die corner, stress relief pad) 73.1 (die corner, stress relief pad) 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 73.1 (die corner, stress relief pad) Doc ID 018939 Rev 1 25/27 Revision history STV7623 8 Revision history Table 11. Date 17-Aug-2011 Document revision history Revision 1 Initial release. Changes 26/27 Doc ID 018939 Rev 1 STV7623 Please Read Carefully: Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale. Purchasers are solely responsible for the choice, selection and use of the ST products and services described herein, and ST assumes no liability whatsoever relating to the choice, selection or use of the ST products and services described herein. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. 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The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners. © 2011 STMicroelectronics - All rights reserved STMicroelectronics group of companies Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Philippines - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America www.st.com Doc ID 018939 Rev 1 27/27