STV7697WAF

STV7697A PLASMA DISPLAY PANEL SCAN DRIVER FEATURES s s s s s s s s s s . 64 OUTPUTS PLASMA DISPLAY DRIVER 170V ABSOLUTE MAXIMUM SUPPLY 5V SUPPLY FOR LOGIC 100/400 mA SOURCE / SINK OUTPUT 700 mA SOURCE / SINK OUTPUT DIODE 64-BIT SHIFT REGISTER (20 MHz) BLANK CONTROL COMPLEMENTARY OUTPUT CONTROL BCD TECHNOLOGY 100 PINS PQFP PACKAGE OR DICE. DESCRIPTION The STV7697A is a scan driver for Plasma Display Panel (PDP) implemented in ST’s proprietary BCD technology. Using a 64-bit cascadable 20 MHz shift register, it drives 64 high current & high voltage outputs. By serially connecting several STV7697A, any vertical pixel definition can be performed. The STV7697A is supplied with a separated 160V power output supply and a 5V logic supply.All command inputs are CMOS compatible. The STV769 7A package is a 100 pins PQFP. PQFP100 (14 x 20 x 2.80 mm) (Full Plastic Quad Flat Pack) ORDER CODE: STV7697A ORDER CODE: STV7697A/WAF (1) (1): Unsawn Tested Wafer Version 4.2 June 2000 This is preliminary information on a new product in development or undergoing evaluation. Details are subject to change without notice. 1/15 1 TABLE OF CONTENTS PIN ASSIGNMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 BLOCK DIAGRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 CIRCUIT DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Note 1 ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Note 1 THERMAL DATA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Note 5 ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Note 6 AC TIMINGS REQUIREMENTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Note 6 AC TIMINGS CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Figure 2. INPUT/OUTPUT SCHEMATICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Figure 6. PACKAGE MECHANICAL DATA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2 2/15 2 (Die pinout) VSSSUB VPP VSSLOG VSSSUB VSSLOG VSSLOG VCC VPP VPP OUT32 OUT31 VSSP VSSP VSSP VSSP VSSP OUT34 OUT33 VPP VSSP (TQFP pinout) VSSLOG VSSSUB VSSSUB VSSP VSSP VPP VPP VSSP VSSP VSSP VSSP VSSLOG VSSLOG VCC VPP 41 40 39 38 37 36 35 34 33 32 31 OUT30 OUT29 OUT28 OUT27 OUT26 OUT25 OUT24 OUT23 OUT22 OUT21 OUT20 OUT19 x (0,0) OUT18 OUT17 OUT16 OUT15 OUT14 OUT13 OUT12 OUT11 OUT10 OUT9 OUT8 OUT7 OUT6 OUT5 OUT4 OUT3 OUT2 OUT1 y OUT35 OUT36 OUT37 OUT38 OUT39 OUT40 OUT41 OUT42 OUT43 OUT44 OUT45 OUT46 OUT47 OUT48 OUT49 OUT50 OUT51 OUT52 OUT53 OUT54 OUT55 OUT56 OUT57 OUT58 OUT59 OUT60 OUT61 OUT62 OUT63 OUT64 VPP PIN CONNECTIONS PIN CONNECTIONS OUT31 OUT32 OUT33 OUT34 50 49 48 47 46 45 44 43 42 OUT30 OUT35 OUT36 OUT37 OUT38 OUT39 OUT40 OUT41 OUT42 OUT43 OUT44 OUT45 OUT46 OUT47 OUT48 OUT49 OUT50 OUT51 OUT52 OUT53 OUT54 OUT55 OUT56 OUT57 OUT58 OUT59 OUT60 OUT61 OUT62 OUT63 OUT64 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 100 90 91 92 93 94 95 96 97 98 99 51 30 OUT29 52 OUT28 53 OUT27 54 OUT26 55 OUT25 56 OUT24 57 OUT23 58 OUT22 59 OUT21 60 OUT20 61 OUT19 62 OUT18 63 OUT17 64 OUT16 65 OUT15 66 OUT14 67 Bare Die PQFP100 OUT13 68 OUT12 69 STV7697A STV7697A OUT11 70 OUT10 71 OUT9 72 OUT8 73 OUT7 74 OUT6 75 OUT5 76 OUT4 77 OUT3 78 OUT2 79 OUT1 80 81 NC NC VPP VPP VCC STB CLK VSSP VSSP VSSLOG SOUT(SIN) 82 83 84 85 86 87 88 89 VPP VPP VPP VPP VCC VSSP VSSP VSSP VSSP BLK POL STB CLK VSSLOG NC SIN(SOUT) F/R SOUT(SIN) VPP VPP F/R VSSP VSSP BLK POL SIN(SOUT) STV7697A 3/15 3 STV7697A PIN ASSIGNMENT (TQFP100) Pin Number 33-37-44-48-81-84-97-100 41 - 90 34-35-36-45-46-47-82-83-98-99 38-43 39-40-42-94 1 to 32, 49 to 80 91 85 86 87 89 92 93 88-95-96 Symbol V PP VCC VSSP V SSSUB VSSLOG OUT 64 to OUT 1 SOUT (SIN) POL BLK F/ R SIN (SOUT) ST B CLK NC Type Supply Supply Ground Ground Ground Output Output Input Input Input Input Input Input Function High Voltage Supply of power outputs 5 V Logic Supply Ground of power outputs Substrate Ground Logic Ground Power Output Shift Register Data Output (forward) Polarity Selection Output Blanking Command Selection of shift direction Shift Register Data Input (forward) Latch of data to outputs Clock of data shift register PIN ASSIGNMENT (Power Outputs) Output N° 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Pin N° 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 Output N° 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 Pin N° 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 Output N° 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 Pin N ° 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 Output N° 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 Pin N° 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 4/15 3 STV7697A PADS DIMENSIONS (in µm)/ PADS POSITIONS The reference is the centre of the die (x=0, y=0) TOP SIDE from left to right Name VPP VSSP VSSP VPP VSSLOG CLK STB SOUT VCC SIN F/R BLK POL VPP VSSP VSSP VPP Centre:X Centre:Y -2468.5 -2313.5 -2188.5 -2063.5 -1620.0 -1430.0 -781.0 -612.5 -335.5 379.5 548.0 1082.0 1853.0 2021.5 2156.5 2291.5 2454.5 4135.0 4135.0 4135.0 4134.5 4135.0 4135.0 4135.0 4135.0 4144.5 4135.0 4135.0 4135.0 4135.0 4140.0 4140.0 4140.0 4129.5 Size:x 75.0 75.0 75.0 75.0 75.0 75.0 75.0 75.0 75.0 75.0 75.0 75.0 75.0 75.0 75.0 75.0 75.0 SIze: y 90.0 90.0 90.0 90.0 90.0 90.0 90.0 90.0 90.0 90.0 90.0 90.0 90.0 90.0 90.0 90.0 90.0 Name OUT1 OUT2 OUT3 OUT4 OUT5 OUT6 OUT7 OUT8 OUT9 OUT10 Name OUT34 OUT33 VPP VSSP VSSP VSSP VPP VSSSUB VSSLOG VSSLOG VCC VSSLOG VSSSUB Centre:X Centre:Y -2468.0 -2318.0 -2182.0 -2047.0 -1912.0 -1777.0 -1642.0 -683.0 -382.5 419.5 618.5 951.0 1308.0 -4087.5 -4089.5 -4089.5 -4093.0 -4093.0 -4093.0 -4089.5 -4088.0 -4088.0 -4087.5 -4087.5 -4087.5 -4087.5 Size:x 75.0 75.0 75.0 75.0 75.0 75.0 75.0 75.0 75.0 75.0 75.0 75.0 75.0 SIze: y 90.0 90.0 90.0 90.0 90.0 90.0 90.0 90.0 90.0 90.0 90.0 90.0 90.0 OUT11 OUT12 OUT13 OUT14 OUT15 OUT16 OUT17 OUT18 OUT19 OUT20 OUT21 OUT22 OUT23 OUT24 Centre:X Centre:Y 2647.0 2647.0 2647.0 2647.0 2647.0 2647.0 2647.0 2647.0 2647.0 2647.0 2647.0 2647.0 2647.0 2647.0 2647.0 2647.0 2647.0 2647.0 2647.0 2647.0 2647.0 2647.0 2647.0 2647.0 3697.0 3484.0 3238.5 2992.5 2743.0 2506.5 2264.0 2018.0 1774.5 1529.0 1285.5 1040.0 796.5 551.0 307.5 62.0 -181.5 -427.0 -670.5 -916.0 -1159.5 -1405.0 -1648.5 -1894.0 Size:x 90.0 90.0 90.0 90.0 90.0 90.0 90.0 90.0 90.0 90.0 90.0 90.0 90.0 90.0 90.0 90.0 90.0 90.0 90.0 90.0 90.0 90.0 90.0 90.0 SIze: y 75.0 75.0 75.0 75.0 75.0 75.0 75.0 75.0 75.0 75.0 75.0 75.0 75.0 75.0 75.0 75.0 75.0 75.0 75.0 75.0 75.0 75.0 75.0 75.0 BOTTOM SIDE from left to right (continued) Name VPP VSSP VSSP VSSP VPP OUT32 OUT31 Centre:X Centre:Y 1438.5 1797.5 1932.5 2067.5 2193.0 2318.0 2468.5 -4087.5 -4093.5 -4093.5 -4093.5 -4093.5 -4093.5 -4093.5 Size:x 75.0 75.0 75.0 75.0 75.0 75.0 75.0 SIze: y 90.0 90.0 90.0 90.0 90.0 90.0 90.0 RIGHT SIDE from top to bottom BOTTOM SIDE from left to right 5/15 3 STV7697A RIGHT SIDE from top to bottom (continued) Name OUT25 OUT26 OUT27 OUT28 OUT29 OUT30 Centre:X Centre:Y 2647.0 2647.0 2647.0 2647.0 2647.0 2647.0 -2137.5 -2383.5 -2627.0 -2872.5 -3116.0 -3363.0 Size:x 90.0 90.0 90.0 90.0 90.0 90.0 SIze: y 75.0 75.0 75.0 75.0 75.0 75.0 LEFT SIDE from bottom to top (continued) Name OUT61 OUT62 OUT63 OUT64 Centre:X Centre:Y -2646.5 -2646.5 -2646.5 -2646.5 2949.5 3228.5 3487.0 3763.0 Size:x 90.0 90.0 90.0 90.0 SIze: y 75.0 75.0 75.0 75.0 LEFT SIDE from bottom to top Name OUT35 OUT36 OUT37 OUT38 OUT39 OUT40 OUT41 OUT42 OUT43 OUT44 OUT45 OUT46 OUT47 OUT48 OUT49 OUT50 OUT51 OUT52 OUT53 OUT54 OUT55 OUT56 OUT57 OUT58 OUT59 OUT60 Centre:X Centre:Y -2646.5 -2646.5 -2646.5 -2646.5 -2646.5 -2646.5 -2646.5 -2646.5 -2646.5 -2646.5 -2646.5 -2646.5 -2646.5 -2646.5 -2646.5 -2646.5 -2646.5 -2646.5 -2646.5 -2646.5 -2646.5 -2646.5 -2646.5 -2646.5 -2646.5 -2646.5 -3363.0 -3116.0 -2872.5 -2627.0 -2383.5 -2137.5 -1894.0 -1648.5 -1405.0 -1159.5 -916.0 -670.5 -427.0 -181.5 62.0 307.5 551.0 796.5 1040.0 1285.5 1529.0 1774.5 2018.0 2264.0 2506.5 2743.0 Size:x 90.0 90.0 90.0 90.0 90.0 90.0 90.0 90.0 90.0 90.0 90.0 90.0 90.0 90.0 90.0 90.0 90.0 90.0 90.0 90.0 90.0 90.0 90.0 90.0 90.0 90.0 SIze: y 75.0 75.0 75.0 75.0 75.0 75.0 75.0 75.0 75.0 75.0 75.0 75.0 75.0 75.0 75.0 75.0 75.0 75.0 75.0 75.0 75.0 75.0 75.0 75.0 75.0 75.0 6/15 3 STV7697A BLOCK DIAGRAM VCC CLK 93 SIN (SOUT) 89 STB 92 Q1 Q2 P1 S1 64-BIT SHIFT REGISTER P64 S64 87 F/R 91 SOUT (SIN) VSSSUB Pins 38-43 VSSLOG Pins 39-40-42-94 VCC Pins 41-90 VSSP Pins 34-35-36-45-46 47-82-83-98-99 VPP 1 VPP Pins 33-37-44-48 81-84-97-100 LATCH Q63Q64 VCC BLK 86 VCC POL 85 --- --- STV7697A VSSP 80 OUT1 VPP VSSP OUT64 CIRCUIT DESCRIPTION The STV7697A contains all the logic and the power circuits necessary to drive rows of a Plasma Display Panel (P. D. P.). The state of the displayed line is loaded into the shift register. Data are shifted at each low to high transition of the (CLK) shift clock. After 64 shifts the first bit is available at the serial output. This output can be used to cascade several drivers to perform any vertical resolution. The forward / reverse (F/R) input is used to select the direction of the shift register, data input/output status is set according to the selected direction. SIN, CLK, STB inputs are Smith trigger inputs . If not used on the application, F/R, BLK, POL logical inputs are internaly pulled to level ”1”. The maximum frequency of the shift clock is 20 MHz. All the data are memorized into the latch stage when the strobe input (STB) is pulled high. Blanking input (BLK) forces the power outputs to high level when pulled high with polarity input (POL) at high level and forced to low level with POL at low level. The level of the power output is inverted when the polarity command (POL) is pulled high. Sustain current must not be sunk in the power output to VPP when the power supply is applied. VSSLOG and VSSSUB must be connected as close as possible to the logical reference ground of the application. Shift Register Truth Table Input F/R H H L L CLK Rise H or L Rise H or L Input /Outp ut SIN IN IN OUT OUT Shift Register Function SOUT Output Q OUT OUT IN IN Forward Shift Steady Reverse Shift Steady 7/15 3 STV7697A Power Output Truth Table Qn (1) X X H L H L X X STB X X L L L L H H BLK H H L L L L L L POL H L L L H H L H Driver Output All H All L H L L H Qn Qn Forced to High Forced to Low Copy Data Copy Data Copy Inverted Data Copy Inverted Data Data Latched Inverted Data Latched Comments Note 1 Qn is the parallel output of the shift register (n = 1 to 64). Qn takes the value of serial input (SIN) after ”n” shift clock periods. ABSOLUTE MAXIMUM RATINGS Symbol VCC VPP VIN V OUT VPOUT IPOUT IDOUT Tjmax Toper Tstg Logic Supply Range Driver Supply Range Logic Input Voltage Range Logic Output Voltage Range Driver Output Voltage Range Driver Output Current (3) (5) Diode Output Current (4) (5) Operating Temperature Junction Temperature (2) Storage Temperature Parameter Value -0.3, +7 -0.3, +170 -0.3, VCC +0.3 -0.3, VCC + 0.3 -0.3, VPP +100/-400 ± 700 -20, +85 +125 -50,+150 Unit V V V V V mA mA °C °C °C THERMAL DATA Symbol Rth(j-a) P oper Tjoper Parameter Junction-ambient Thermal Resistance (2) Operating Power Dissipation (Tamb = 25°C) Operating Junction Temperature (2) Max Max Max Value 50 2 +125 Unit ° C/W W °C Note 2 For PQFP100 packaging. Note 3 Through one power output. Note 4 Through one power output with VPP = VSSP (see test diagram) . Note 5 These parameters are measured during ST’s internal qualification which includes temperature characterisation on standard batches and on corners batches of the process. These parameters are not tested on the parts. 8/15 3 STV7697A ELECTRICAL CHARACTERISTICS (VCC = 5 V, V PP = 160 V, VSSP = 0 V, VSSLOG = VSSSUB = 0 V, Tamb = 25°C, fCLK = 20 MHz, unless otherwise specified) Symbol SUPPLY VCC I CCH ICCL VPP IPPH OUTPUT OUT1-OUT64 VPOUTH V POUTL VDOUTH VDOUTL SOUT VOH VOL Logic Output High Level Logic Output Low Level IOH = 1 mA IOL = -1 mA 4 0.4 V V Power Output High Level (voltage drop versus VPP) Power Output Low Level Output Diode High Level Output Diode Low Level IPOUTH = - 10 mA IPOUTH = - 40 mA IPOUTL = 200 mA IDOUTH = +400 mA (5) IDOUTL = - 400 mA (5) 10 -10 5 3.1 2.3 -2.2 10 10 V V V V V Logic Supply Voltage Logic Supply Current (all inputs high) Logic Supply Current Power Output Supply Voltage Power Output Supply Current (steady outputs) fCLK = 8 MHz, SIN = 1010 4.5 15 5 5.3 5.5 100 160 100 V µA mA V µA Parameter Test Condition s Min. Typ. Max. Unit INPUT (CLK, F/ R , ST B, POL, BLK, SIN, ) V IH VIL IIH IIL Input High Level Input Low Level High Level Input Current Low Level Input Current CLK, SIN, ST B , F/ R , BLK, POL VIH = VCC VIL = 0 V 0.8 VCC 70 0.2V CC 10 10 100 V V µA µA µA Note 6 Compatible with power dissipation (see test diagram). 9/15 3 STV7697A AC TIMINGS REQUIREMENTS (VCC = 4.5 V to 5.5 V, Tamb = -20 to +85°C, input signals max leading edge & trailing edge (tR, tF) = 10 ns) Symbol tCLK tWHCLK tWHCLK tSDAT tHDAT tSFR tDSTB tSTB tBLK tPOL Data Clock Period Duration of clock (CLK) pulse at high level Duration of clock (CLK) pulse at low level Set-up Time of data input before clock low to high transition Hold Time of data input after clock low to high transition Forward/reverse (F/R) Set-up Time before low to high transition Minimum Delay to latch STB after clock low to high transition Strobe STB Pulse Duration Blank (BLK) Pulse Duration Polarity (POL) Pulse Duration Parameter Min. 50 15 15 10 10 100 10 20 500 500 Typ. Max. Unit ns ns ns ns ns ns ns ns ns ns AC TIMINGS CHARACTERISTICS (VCC = 5 V, V PP = 90 V, VSSP = 0 V, VSSLOG = VSSSUB = 0 V, Tamb = 25°C, fCLK = 20 MHz, VILMax. = 0.2 Vcc, VIHMin. = 0.8 VCC, VOH = 4.0 V, VOL = 0.4 V, CL = 15pF, unless otherwise specified) Symbol tCLK tRDAT tFDAT tPHL1 tPLH1 tPHL2 tPLH2 tPHL3 tPLH3 tPHL4 tPLH4 tROUT tFOUT Data Clock Period Logical Data Output Rise Time Logical Data Output Fall Time Delay of logic data output after clock (CLK) high to low transition Delay of logic data output after clock (CLK) low to high transition Delay of power output change after clock (CLK) high to low transition Delay of power output change after clock (CLK) low to high transition Delay of power output change after blanking (BLK) high to low transition Delay of power output change after blanking (BLK) low to high transition Delay of power output change after polarity (POL) high to low transition Delay of power output change after polarity (POL) low to high transition Power Output Rise Time (7) Power Output Fall Time (7) Parameter Min. 50 Typ. 20 11 45 48 120 120 110 110 100 60 Max. 80 80 180 180 165 165 160 160 200 200 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns Note 7 One output among 64, loading capacitor COUT = 100pF, other outputs at low level. 10/15 3 STV7697A Figure 1. AC Characteristics Waveform tCLK tWLCLK tWHCLK ”1” CLK 50% 50% tSDAT 50% ”0” tHDAT ”1” SIN 50% tPLH1 50% ”0” tFDAT SOUT ”1” 50% ”0” tSTB tDSTB ”1” 50% ”0” tSFR ”1” 10% 10% 90% 90% tRDAT STB 50% F/R 50% ”0” tPHL2 ”1” 90% 10% tPLH2 tBLK ”1” ”0” OUTn BLK 50% tPLH3 50% ”0” tPHL3 90% ”1” OUTn 10% ”0” tPOL ”1” POL 50% tROUT 90% 10% 90% 10% tFOUT tPHL4 90% 50% ”0” tPLH4 ”1” 10% OUTn ”0” 11/15 STV7697A Figure 2. Test Configuration VPP VDOUTH OUTI IDOUTL VPP OUTI VDOUTL IDOUTL VSSP VSSP Output sinking current as positive value, sourcing current as negative value 12/15 STV7697A INPUT/OUTPUT SCHEMATICS Figure 3. F/R, BLK, POL, HIZ VCC (Pins 41, 90) Figure 5. SIN, SOUT Input VCC (Pins 41, 90) SIN, SOUT (Pins 89, 91) F/R, BLK, POL (Pins 87, 86, 85) VSSSUB (Pins 38, 43) VSSLOG (Pins 39, 40, 42, 94) VSSSUB (Pins 38, 43) VSSLOG (Pins 39, 40, 42, 94) VSSLOG (Pins 39, 40, 42, 94) Figure 4. CLK, STB VCC (Pins 41, 90) Figure 6. Power Output VPP (Pins 33, 37, 44, 48, 81, 84, 97, 100) CLK, STB (Pins 93, 92) OUTi (Pins 1 to 32, 49 to 80) VSSSUB (Pins 38, 43) VSSLOG (Pins 39, 40, 42, 94) VSSP (Pins 34, 35, 36, 45, 46, 47, 82, 83, 98, 99) 13/15 STV7697A PACKAGE MECHANICAL DATA 100 PINS - THIN PLASTIC QUAD FLAT PACK (PQFP100) A A2 80 e A1 51 0,10 mm .004 inch SEATING PLANE 81 50 E3 E1 100 31 E B 1 D3 D1 D 30 c L1 Millimeters Dimensions Min. A A1 A2 B C D D1 D3 e E E1 E3 L L1 K 0.65 16.95 13.90 0.25 2.55 0.22 0.13 22.95 19.90 23.20 20.00 18.85 0.65 17.20 14.00 12.35 0.80 1.60 0° (Min.), 7° (Max.) 0.95 0.026 17.45 14.10 0.667 0.547 2.80 3.05 0.38 0.23 23.45 20.10 Typ. Max. 3.40 0.010 0.100 0.0087 0.005 0.903 0.783 Min. L K Inches Typ. Max. 0.134 0.110 0.120 0.015 0.009 0.913 0.787 0.742 0.026 0.677 0.551 0.486 0.031 0.063 0.923 0.791 0.687 0.555 0.037 14/15 STV7697A Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this public ation are subject to change witho ut notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a trademark of STMicroelectronics. © 2000 STMicroelectronics - All Rights Reserved Purchase of I2C Components of STMicroelectronics, conveys a license under the Philip s I2C Patent. Rights to use these components in a I2C system, is granted provided that the system conforms to the I2C Standard Specifications as defined by Philip s. STMicroelectronics GROUP OF COMPANIES Australia - Brazil - China - Finland - France - Germany - Italy - Japan - Korea - Malaysia - Malta - Mexico - Morocco - The Netherlands - Singapore - Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - U.S.A. http://www .st.com 15/15 4