STV8267

® STV82x7 Digital Audio Decoder/Processor for A2 and NICAM Television/Video Recorders DATASHEET Key Features ■ Full-Automatic Multi-Standard Demodulation B / G / I / L / M / N / D / K Standards Mono AM and FM ● FM 2-Carrier (German and Korean Zweiton) and NICAM ● ● The STV82x7 family, based on audio digital signal processors (DSP), performs high quality and advanced dedicated digital audio processing.These devices provide all of the necessary resources for automatic detection and demodulation of analog audio transmissions for European and Asian terrestrial TV broadcasts. Virtual or true, multi-channel capabilities and easy digital links make them ideal for digital audio low cost consumer applications. Starting from enhanced stereo up to independent control of 5 loudspeakers and a subwoofer (5.1 channels), the STV82x7 family offers standard and advanced features plus sound enhancements, spatial and virtual effects to enhance television viewer comfort and entertainment. ■ Multi-Channel Capability 3 I²S digital inputs, S/PDIF (pass-thru/out) 1 I²S digital output (shared with one of the I²S digital inputs) ● 5.1 analog outputs ● Dolby Pro Logic ● Dolby Pro Logic II ● ● ■ Sound Processing: Loudspeaker ST royalty-free processing: ST WideSurround, ST OmniSurround (Virtual Dolby Surround and Virtual Dolby Digital compliant) and ST Dynamic Bass ● SRS WOW , SRS TruSurround XT (Virtual Dolby Surround and Virtual Dolby Digital compliant) ● Independent Volume / Balance ● Smart Volume Control (SVC), 5-band equalizer and loudness ● ■ Sound Processing: Headphone Smart Volume Control (SVC), Bass-Treble, Loudness and SRS TruBass ● Independent Volume / Balance ● ■ Analog Audio Matrix 4 stereo inputs ● 3 stereo outputs ● THRU mode ● 2 V RMS capability ● ■ Audio Delay for Audio Video Synchronization Embedded stereo delay up to 90 ms when processing at 32KHz (demodulator input mode) and up to 60 ms when processing at 48KHz (SCART only input mode) ● Independent delay on headphone and loudspeaker channels ● January 2006 ™ ® ™ ® ® ® ® ® ™ ® ® ® Typical Applications Analog and digital TV with virtual surround sound ● Analog and digital TV with multi-channel surround sound ● DVD and HDD recorders ● “Palm size” portable TV ● ® ® ST x7 82 V ® © 2004 SRS Labs, Inc. All rights reserved, SRS and the SRS logo are registered trademarks of SRS Labs, Inc. “Dolby”, “Pro Logic”, and the double-D symbol are trademarks of Dolby Laboratories. Rev. 4.1 1/156 ®® ®® ® ™ ™ ® ™ CLK_SEL XTALIN XTALOUT 2/156 I²S Inputs/Output IRQ Headphone Detection Sound IF SIF Headphone Digital Audio Processing Control Logic Volume Balance Mute Matrix Stereo Audio DAC PCM_CLK Loudspeakers Stereo Audio DAC DATA_0 DATA_1 DATA_2 LR_CLK LS_L LS_R LS_C LS_SUB Headphone / Surround HP_LSS_L HP_LSS_R S/PDIF Out S/PDIF In Stereo Audio DAC Loudspeakers Digital Audio Processing Volume, Equalizer, Balance, Dolby Pro Logic Dolby Pro Logic II , ST WideSurround, ST Dynamic Bass, ST OmniSurround, Loudness,Smart Volume Control, Bass Management, Beeper SRS WOW or TruSurround XT Stereo Audio DAC Block Diagram I²S Interface Pre-scaler Digital Audio Matrix AGC Volume, Balance, Loudness, Smart Volume Control, Bass/Treble, SRS Trubass A/D S_CLK Digital FM/AM NICAM FM 2-carrier Demodulation Mono Input MONO_IN Audio A/D SC1_IN_L SC1_IN_R SC2_IN_L SC2_IN_R 2 VRMS SC1_OUT_L SC1_OUT_R SC3_IN_L SC3_IN_R Clock Generator Input Analog Audio Matrix Output Analog Audio Matrix 2 VRMS SC2_OUT_L SC2_OUT_R SC4_IN_L SC4_IN_R I²C Interface 2 VRMS SC3_OUT_L SC3_OUT_R SCART Outputs SCART Inputs SDA SCL I²C STV82x7 STV82x7 Table of Contents Chapter 1 1.1 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 STV82x7 Overview .............................................................................................................. 9 1.1.1 Core Features ............................................................................................................................................9 1.1.2 Software Information ...............................................................................................................................10 1.1.3 Device Input Modes .................................................................................................................................10 1.1.4 Electrical Features ...................................................................................................................................11 1.2 1.3 Typical Applications ........................................................................................................... 11 Pin Descriptions and Application Diagrams ....................................................................... 15 Chapter 2 Chapter 3 3.1 3.2 System Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 Digital Demodulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 Sound IF Signal .................................................................................................................. 22 Demodulation ..................................................................................................................... 23 Chapter 4 4.1 4.2 4.3 4.4 4.5 4.6 Dedicated Digital Signal Processor (DSP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 Back-end Processing ......................................................................................................... 25 Audio Processing ............................................................................................................... 26 ST WideSurround ............................................................................................................... 30 ST OmniSurround .............................................................................................................. 30 Dolby Pro Logic II Decoder ................................................................................................ 30 Bass Management ............................................................................................................. 30 4.6.1 Bass Management Configuration 0 .........................................................................................................31 4.6.2 Bass Management Configuration 1 .........................................................................................................32 4.6.3 Bass Management Configuration 2 .........................................................................................................33 4.6.4 Bass Management Configuration 3 .........................................................................................................34 4.6.5 Bass Management Configuration 4 .........................................................................................................35 4.7 SRS WOW and TruSurround XT ...................................................................................... 35 4.7.1 SRS TruSurround ....................................................................................................................................35 4.7.2 SRS WOW ...............................................................................................................................................36 4.8 4.9 4.10 4.11 4.12 4.13 4.14 Smart Volume Control (SVC) ............................................................................................. 36 ST Dynamic Bass .............................................................................................................. 37 5-Band Audio Equalizer ..................................................................................................... 37 Bass/Treble Control ........................................................................................................... 37 Automatic Loudness Control .............................................................................................. 38 Volume/Balance Control .................................................................................................... 38 Soft Mute Control ............................................................................................................... 39 3/156 STV82x7 4.15 4.16 Beeper ................................................................................................................................ 39 Internal Audio/Video Delay (Lip Sync) ............................................................................... 40 Chapter 5 Chapter 6 6.1 6.2 Analog Audio Matrix (In / Out) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41 I²S Interface (In / Out) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42 I²S Inputs ............................................................................................................................ 42 I²S Output ........................................................................................................................... 44 Chapter 7 Chapter 8 8.1 8.2 S/PDIF Input/Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46 Power Supply Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47 Standby Mode (Loop-through mode) ................................................................................. 47 Power on Reset .................................................................................................................. 47 Chapter 9 9.1 9.2 9.3 Additional Controls and Flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48 Headphone Detection ........................................................................................................ 48 IRQ Generation .................................................................................................................. 48 I²C Bus Expander ............................................................................................................... 48 Chapter 10 Chapter 11 11.1 11.2 11.3 11.4 STV82x7 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49 I²C Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50 I²C Address and Protocol ................................................................................................... 50 Start-up and Configuration Change Procedure .................................................................. 51 Process Flow during Patch Loading and DSP Initialization ............................................... 53 Input Configuration Change ............................................................................................... 54 Chapter 12 12.1 12.2 12.3 12.4 12.5 12.6 12.7 Register List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55 I²C Register Map ................................................................................................................ 56 STV82x7 General Control Registers .................................................................................. 62 Clocking 1 .......................................................................................................................... 64 Demodulator ....................................................................................................................... 66 Demodulator Channel 1 ..................................................................................................... 69 Demodulator Channel 2 ..................................................................................................... 73 NICAM Registers ............................................................................................................... 78 4/156 STV82x7 12.8 12.9 12.10 12.11 12.12 12.13 12.14 12.15 12.16 12.17 12.18 12.19 12.20 12.21 12.22 12.23 12.24 Stereo Mode ....................................................................................................................... 80 Analog Control ................................................................................................................... 81 Clocking 2 .......................................................................................................................... 83 DSP Control ....................................................................................................................... 84 Automatic Standard Recognition ........................................................................................ 88 Audio Preprocessing and Selection Registers ................................................................... 92 Matrixing ........................................................................................................................... 100 Audio Processing ............................................................................................................. 105 5-Band Equalizer / Bass-Treble for Loudspeakers .......................................................... 117 Headphone Bass-Treble .................................................................................................. 119 Volume ............................................................................................................................. 122 Beeper .............................................................................................................................. 132 Mute ................................................................................................................................. 133 S/PDIF .............................................................................................................................. 134 Headphone Configuration ................................................................................................ 134 DAC Control ..................................................................................................................... 135 AutoStandard Coefficients Settings ................................................................................. 137 Chapter 13 13.1 13.2 13.3 13.4 13.5 13.6 13.7 13.8 13.9 13.10 13.11 13.12 13.13 13.14 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .140 Absolute Maximum Ratings ............................................................................................ 140 Thermal Data .................................................................................................................. 140 Power Supply Data .......................................................................................................... 140 Crystal Oscillator ............................................................................................................. 141 Analog Sound IF Signal .................................................................................................. 141 SIF to I²S Output Path Characteristics ............................................................................. 142 SCART to SCART Analog Path Characteristics .............................................................. 142 SCART and MONO IN to I²S Path Characteristics .......................................................... 143 I2S to LS/HP/SUB/C Path Characteristics ....................................................................... 143 I²S to SCART Path Characteristics .................................................................................. 144 MUTE Characteristics ...................................................................................................... 144 Digital I/Os Characteristics ............................................................................................... 144 I²C Bus Characteristics .................................................................................................. 145 I2S Bus Interface .............................................................................................................. 146 Chapter 14 Input/Output Groups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .148 5/156 STV82x7 Chapter 15 Package Mechanical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .153 6/156 STV82x7 General Description 1 General Description The STV82x7 is a multistandard TV sound demodulator and audio processor which integrates SRS WOW , SRS TruSurround XT , Dolby Pro Logic , Dolby Pro Logic II ,Virtual Dolby Surround (VDS) and Virtual Dolby Digital (VDD) capability. ST advanced algorithms such as ST OmniSurround, ST WideSurround, ST Dynamic Bass are also available in this audio sound processor. ST OmniSurround is a certified Dolby algorithm for the Virtual Dolby Digital (VDD) and the Virtual Dolby Surround (VDS). When using VDD or VDS, either a Dolby D igital or a Pro Logic (or Pro Logic II ) decoder is mandatory respectively. This chip performs automatic multistandard analog TV stereo sound identification and demodulation (no specific I²C programming is required). It offers various audio processing functions such as equalization, loudness, beeper, volume, balance, and surround effects. It provides a cost-effective solution for analog and digital TV designs. The STV82x7 is perfectly suited to current and future digital TV platforms, based on audio/video digital chips (STD2000, DTV100 platform) which include an internal digital decoder (MPEG, Dolby Digital...). In the case where a Dolby Digital decoder is embedded in the audio/video digital chip, Virtual Dolby Digital can be obtained. For the CTV100/120 platforms, this device is offered as an alternative solution to the first-generation chassis that uses the STV82x6. ® ® ® ® ® ® ® ® ® ® ™ ® ® ® ® ™ ® ® ® 7/156 General Description STV82x7 Table 1: STV82x7 Version List STV8247 S T V 8 2 1 7 S T V 8 2 3 7 S T V 8 2 4 7 D S X S T V 8 2 5 7 D STV8257 S T V 8 2 5 7 D S X S T V 8 2 5 7 S X STV8267 S T V 8 2 6 7 D S X STV8277 S T V 8 2 7 7 D S X STV8287 S T V 8 2 8 7 D S X S T V 8 2 4 7 D S T V 8 2 6 7 D S T V 8 2 7 7 D S T V 8 2 8 7 D Demodulation FM 2 Carrier and NICAM Multi-Channel Capabilities Analog loudspeakers output number I²S In (exclusive with I²S Out) S/PDIF (Pass-thru or Output) 2.1 1 1 2.1 1 1 2.1 1 1 X 2.1 1 1 X 2.1 3 1 X 2.1 3 1 X 2.1 3 1 5.1 1 1 X 5.1 1 1 X 5.1 3 1 X 5.1 3 1 X 5.1 3 1 VDS PLII X 5.1 3 1 VDS PLII X X X X X X X X X X X X X X capability1 Audio Processing ST Voice, ST Dynamic Bass ST WideSurround, ST OmniSurround2 Figure 1: Package Ordering Information Order Code: STV82x7 (Tray) STV82x7/T (Tape & Reel) FP TQ 80 ® For Example: STV8257DSX/T will be delivered in Tape & Reel conditioning 8/156 ® 2. When using Virtual Dolby Digital or Virtual Dolby Surround with ST OmniSurround or SRS XT a Dolby Digital or a Pro Logic (or Pro Logic II ) decoder is mandatory. TruSurround ® ® ® ® 1. Dolby Digital Bypass capability or Virtual Dolby decoder (for example STD2000). ® ® ™ SRS TruSurround XT ® ® ™ ™ ® ® SRS WOW (WOW) ® ® ® ® Dolby Dolby Pro Logic (DPLI) or Pro Logic II (DPLII) ® Virtual Dolby ® Virtual Dolby Surround Digital X X X X X DPLI DPLI DPLI DPLI (internal) (internal) (internal) (internal) DPLI DPLI DPLI DPLI DPLII DPLII X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X Digital are obtained with the use of an external Dolby Digital STV82x7 General Description 1.1 1.1.1 STV82x7 Overview Core Features ● Single audio source processing: — IF source and/or analog stereo input (SCART) — one digital source with a maximum of 6 synchronous channels (5.1 is obtained across three I²S) ● ● SIF input signal with Automatic Gain Control (AGC) Digital Demodulator with automatic standard detection and demodulation for AM, FM mono, FM 2 carriers (German or Korean FM 2-carrier) and NICAM Audio processor working at 32 kHz, 44.1 kHz or 48 kHz with specific features: — For Loudspeakers (L, R, LS, R S, SubW, C): Dolby Pro Logic II Decoder with Bass Management SRS WOW or TruSurround XT including Virtual Dolby Digital ST WideSurround ST OmniSurround ST Dynamic Bass 5-band Equalizer or Bass-Treble Loudness Smart Volume Control Volume/Balance/Soft-mute Beeper Video Processing Delay Compensation — For Headphone: SRS TruBass Smart Volume Control Bass-Treble Loudness Volume/Balance/Soft-mute Beeper Video Processing Delay Compensation ● ● ● Shared outputs for headphone and loudspeakers surround channels: Analog matrix with: — five external inputs: four SCART inputs (2 VRMS capable) one analog mono input (0.5 VRMS) — one internal input from a digital matrix via a DAC — three external outputs (2 VRMS capable) — one internal output for the digital matrix (using an internal ADC) ● Digital matrix with: — three input modes (Demodulator/SCART, SCART only and I²S) — three stereo outputs (Loudspeakers, Headphone and SCART) ● ● ● High-end audio DAC S/PDIF pass-thru/output for connection with an external amplifier/decoder Internal multiplexer for the S/PDIF output (to share the internal S/PDIF output and the S/PDIF output generated by the external decoder of the digital broadcast) 9/156 ® ® ™ ® ™ ™ ® ® ® Surround and Virtual Dolby General Description ● ● ● STV82x7 Specific stand-by mode (Loop-through) Control by I²C bus (two I²C addresses) System PLL and Clock Generation using either a single quartz oscillator or a differential clock input 1.1.2 Software Information The different software combinations are listed in Table 2. Table 2: Input/Output Software Configurations Output (Number of Channels) Input (Number of Channels) 2 (+1) 1 2 (L and R) ST WideSurround or SRS WOW ST WideSurround or SRS WOW ST WideSurround or SRS TruSurround XT or ST OmniSurround or Dolby Pro Logic + SRS TruSurround XT or Dolby Pro Logic + ST OmniSurround SRS TruSurround XT or ST OmniSurround or Downmix SRS TruSurround XT or ST OmniSurround or Downmix 4 (+1) 5 (+1) 4 (+1) No processing 5 (+1) Downmix Note: 1 In addition to the above sound processing, it is always possible to add ST Voice and also ST Dynamic Bass algorithms. 2 The SRS TruSurround and ST OmniSurround are approved by Dolby as Virtual Dolby Surround (VDS) and Virtual Dolby Digital (VDD). The SRS ● ● ● WOW 1.1.3 Device Input Modes ● ● ● Demodulator only mode (with output fS = 32 kHz) Demodulator and SCART mode (with output fS = 32 kHz) SCART only mode (with output fS = 48 kHz) 10/156 ™ SRS TruBass ™ SRS Dialog Clarity ™ SRS 3D Mono/Stereo ™ ™ ● SRS WOW system includes: ® ● SRS TruSurround ™ ® ® ® ® ® ® ® The SRS TruSurround XT system is composed of: ® ® ® ™ ™ ® ™ ® ® ® 2 (LT and RT) ™ ™ ™ ® ® ® ® ® Dolby Pro Logic No processing ® ® STV82x7 ● General Description I²S mode (with output fS = 32, 44.1 or 48 kHz) 1.1.4 Electrical Features Multi Power Supply: 1.8 V, 3.3 V and 8 V. Power Consumption: ● ● lower than 1 W in Functional mode (full features) 200 mW in Loop-through mode corresponding to Switch-off of all digital blocks 1.2 Typical Applications The STV82x7 is specified to enable flexible, analog and digital TV chassis design (refer to Figure 2, Figure 3, Figure 4 and Figure 5). The main considerations are: ● ● ● ● all necessary connections between devices can be provided through the TV set, pseudo stand-by mode used to copy to VCR or the DVD sources when the TV set is OFF, possible application compatibility with STV82x6 (TQFP80 package) TV design, pin-to-pin compatibility with STV82x8 (TQFP80 package) TV design. The STV82x7 is used to process a single audio source (analog or digital). However, it is possible to process two audio sources simultaneously using an STV82x7 interconnection (two chips can be easily connected). In the case of a single audio source, it is possible to hear and record in the same time: the same audio stream can be simultaneously output on headphone, loudspeakers, S/PDIF and the SCART connectors. Note: Headphone and loudspeakers can be used simultaneously for dual-language purposes or for different sound settings (e.g. volume). In this case, certain restrictions occur (see Section 4.2: Audio Processing). For more connections, the SCART-to-SCART path can be used. The use of these full analog paths implies that the sound is not digitally processed. ® — External audio input interface using 3 x I²S (for decoded streams such as Dolby and/or standard stereo streams) Digital 11/156 General Description STV82x7 Figure 2: STV8237 Typical Application (Enhanced Stereo) Tuner R STV8237 or Multistandard Demodulation - FM 2-carrier and NICAM Sound Processing - Volume, Balance, 5-Band Equalizer - ST WideSurround - SRS WOW SubW L Left Right Figure 3: STV8247 Typical Application (Analog Virtual Sound) Tuner STV8247DSX or Multistandard Demodulation - FM 2-carrier and NICAM Sound Processing - Volume, Balance, 5-Band Equalizer - SRS TruSurround XT - ST OmniSurround - Virtual Dolby Surround1 SubW Left Right 1. When using VDS with ST OmniSurround or SRS TruSurround XTTM, a Pro Logic decoder is mandatory. 12/156 ® ™ ™ ® ® ® R L STV82x7 Figure 4: STV8257 Typical Application (Digital: Virtual Sound) General Description Multi-Channel Digital Decoder Tuner or Left Right 1. When using VDS with ST OmniSurround or SRS TruSurround XTTM, a Pro Logic decoder is mandatory. 2. When using VDD with ST OmniSurround or SRS TruSurround XTTM, a Dolby Digital decoder is mandatory. Figure 5: STV8277 Typical Application (Digital TV: Multi-Channel and Virtual Sound) Multi-Channel Digital Decoder Tuner or Left Right Shared with surround LS/RS decoder is mandatory. ® 2. When using VDD with ST OmniSurround or SRS TruSurround XT TM , a Dolby Digital decoder is mandatory. ® 1. When using VDS with ST OmniSurround or SRS TruSurround XTTM, a Pro Logic ™ ® ® ® ® ® ® (Dolby Digital) I²S S/PDIF Pass-thru STV8287DSX Multistandard Demodulation - FM 2-carrier and NICAM Audio Processing - Volume, Balance, 5-Band Equalizer - Dolby Pro Logic II - 5.1 Analog Outputs - SRS TruSurround XT - ST OmniSurround - Virtual Dolby Surround1 - Virtual Dolby Digital2 ® ® ™ ® ® ® ® (Dolby Digital) R S/PDIF Pass-thru SubW I²S STV8257DSX Multistandard Demodulation - FM 2-carrier and NICAM Audio Processing - Volume, Balance, 5-Band Equalizer - SRS TruSurround XT - ST OmniSurround - Virtual Dolby Surround1 - Virtual Dolby Digital2 L R RS SubW C LS L 13/156 General Description Figure 6: STV8217 Typical Application (Digital Recorder) STV82x7 MPEG Codec Tuner I²S or STV8217 Multistandard Demodulation - FM 2-carrier and NICAM Left Right 14/156 STV82x7 General Description 1.3 Pin Descriptions and Application Diagrams ● ● ● ● ● ● ● AP DP I O OD B A = Analog Power = Digital Power = Input = Output = Open-Drain = Bi-Directional = Analog Table 3: TQFP80 Pin Description (Sheet 1 of 3) Pin No. 1 2 3 4 5 6 7 8 9 10 STV82x7 Pin Name SC1_OUT_L SC1_OUT_R VCC_H GND_H SC3_OUT_L SC3_OUT_R VCC33_SC GND33_SC SC1_IN_L SC1_IN_R Type (STV82x7) A A AP AP A A AP AP A A Function for STV82x7 (Function for STV82x6 in italic characters) SCART1 Audio Output Left SCART1 Audio Output Right 8 V Power for Audio I/O & ESD High Current Ground for Audio Outputs SCART3 Audio Output Left SCART3 Audio Output Right 3.3 V Power for Audio Buffers & DAC / ADC Ground for Audio Buffers & DAC / ADC SCART1 Audio Input Left SCART1 Audio Input Right Audio Bias Voltage Decoupling 1.55 V (Switched VREF decoupling pin for Audio Converters (VMCP)) Ground for DACs Bandgap Voltage Reference Decoupling 1.2 V (V REF decoupling pin for Audio Converters (VMC)) SCART2 Audio Input Left SCART2 Audio Input Right 3.3 V Power for Audio DACs (3.3 V Power Supply for Audio Buffers and SCART) Ground for Audio DACs (Ground for Audio Buffers and SCART) SCART2 Audio Output Left SCART2 Audio Output Right Polarization of the NISO (connected to 3.3 V) (8 V / 5 V Power supply for SCART & Audio buffers) Ground for DAC 1.8 to 3.3 V Converters 3.3 V Power for DAC 1.8 to 3.3 V Converters (Voltage Reference for Audio buffers) AO1L STV82x6 Pin Name AO1R Not connected Connected to Ground Not connected Not connected VDDC GNDC AI1L AI1R 11 VREFA A VMC1 12 13 14 15 16 17 18 19 20 21 22 GND_SA VBG SC2_IN_L SC2_IN_R VCC33_LS GND33_LS SC2_OUT_L SC2_OUT_R VCC_NISO VSS33_CONV VDD33_CONV AP A A A AP AP A A AP AP AP Connected to Ground VMC2 AI2L AI2R VDDA GNDAH AO2L AO2R VDDH Connected to Ground VREFA 15/156 General Description Table 3: TQFP80 Pin Description (Sheet 2 of 3) Pin No. 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 STV82x7 STV82x7 Pin Name SC3_IN_L SC3_IN_R SCL_FLT SCR_FLT LS_C LS_L LS_R LS_SUB HP_LSS_L HP_LSS_R VSS18_CONV VDD18_CONV HP_DET ADR_SEL VSS18 VDD18 SCL SDA VSS18 VDD18 RST S/PDIF_IN S/PDIF_OUT VDD33_IO1 VSS33_IO1 CK_TST_CTRL VSS18 VDD18 CLK_SEL XTALIN_CLKXTP Type (STV82x7) A A A A A A A A A A DP DP I I DP DP OD OD DP DP I I O DP DP D DP DP I I Function for STV82x7 (Function for STV82x6 in italic characters) SCART3 Audio Input Left SCART3 Audio Input Right SCART Filtering Left SCART Filtering Right (Bandgap Voltage Source Decoupling) Center Output Left Loudspeaker Output Right Loudspeaker Output Subwoofer Output Left Headphone Output or Left Surround Output Right Headphone Output or Right Surround Output Ground for Digital part of the DAC/ADC (Substrate Analog/Digital Shield) 1.8 V Power for Digital part of the DAC/ADC Headphone Detection Hardware Address selection for I²C Bus Ground for Digital part 1.8 V Power for Digital part I²C Clock Input I²C Data I/O Ground for Digital part 1.8 V Power for Digital part (5 V Power Regulator Control) Main Reset Input Serial Audio Data Input (System Clock output) Serial Audio Data Output (I²S Master Clock output) 3.3 V Power for Digital part Ground for Digital part To be Grounded Ground for Digital part 1.8 V Power for Digital part Clock Input Format Selection Crystal Oscillator Input or Differential Input Positive (Crystal Oscillator Input) AI3L AI3R STV82x6 Pin Name Not connected BGAP Not connected LSL LSR SW HPL HPR GNDSA Not connected HPD ADR Connected to Ground Not connected SCL SDA Connected to Ground REG RESET SYSCK MCK VDD1 GND1 Not connected GNDSP Not connected Not connected XTI 16/156 STV82x7 Table 3: TQFP80 Pin Description (Sheet 3 of 3) Pin No. 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 General Description STV82x7 Pin Name XTALOUT_CLKXTM VCC18_CLK1 GND18_CLK1 GND18_CLK2 VCC18_CLK2 VSS33_IO2 VDD33_IO2 I2S_PCM_CLK I2S_SCLK I2S_LR_CLK I2S_DATA0 I2S_DATA1 I2S_DATA2 VDD18 VSS18 BUS_EXP IRQ GND_PSUB VDD18_ADC VSS18_ADC SIF_P SIF_N GNDPW_IF VCC18_IF GND18_IF MONO_IN SC4_IN_L SC4_IN_R Type (STV82x7) O AP AP DP DP DP DP I/O I/O I/O I/O I I DP DP O O AP DP DP A A AP AP AP A A A Function for STV82x7 (Function for STV82x6 in italic characters) Crystal Oscillator Output or Differential Input Negative (Crystal Oscillator Output) XTO STV82x6 Pin Name 1.8 V Power for Clock PLL Analog & Crystal Oscillator 1/2 VDDP (3.3 V Power supply for Analog PLL Clock) Ground for Clock PLL Analog & Crystal Oscillator 1/2 Ground for Clock PLL Digital 1/2 1.8 V Power for Clock PLL Digital 1/2 (3.3 V Power supply for Digital core, DSPs & IO Cells) Ground for Digital IO pins 60 to 69 3.3 V power for Digital IO pins 60 to 69 I²S Slave Clock Input/Output Channel 1, 2 & 3 I²S Clock Input/Output Channel 1, 2 & 3 (I²S bus data output) I²S Word Select Input/Output Channel 1,2 & 3 (Stereo Detection output / I²S Bus Data input) I²S Data Input/Output Stereo Channel 1 (I²S Bus Word Select output) I²S Data Input Stereo Channel 2 (I²S Bus Clock output) I²S Data Input Stereo Channel 3 (Bus Expander Output 1) 1.8 V Power for Digital Core & I/O Cells Pin Ground for Digital Core & I/O Cells Pin Bus Expander Function (Bus Expander Output 2) Interrupt Request to Microprocessor Ground Substrate Connection VDD 1.8 V for ADC (Digital Part) Ground to Complement 1.8 V VDD for ADC Sound IF input (positive) Sound IF input (negative) (ADC VTOP Decoupling pin) Polarization for the IF block (Voltage Reference for AGC Decoupling pin) 1.8 V Power for IF AGC & ADC Ground for IF AGC & ADC Mono Input (for AM Mono) SCART4 Audio Input Left SCART4 Audio Input Right GNDP GND2 VDD2 Connected to Ground Not connected Not connected SDO ST/SDI WS SCK BUS1 Not connected Connected to Ground BUS0 IRQ Connected to Ground Not connected Connected to Ground SIF VTOP VREFIF VDDIF GNDIF MONOIN Not connected Not connected 17/156 +1.8V 10µH + C9 330µF L18 C10 100nF L 15 100µH L14 1 1 L2 C69 33nF C68 100µH 33nF C67 33nF C66 33nF C65 33nF C64 33nF L17 100µH L16 100µH Headphone detection 100µH SL1 100µH 2 3 3 +3.3V 100nF C12 Address select C13 100nF + L13 C63 33nF C62 33nF + SCL SDA 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 C14 100nF C15 C75 220 C58 100nF C74 220 C57 100nF 330pF R8 330pF 100nF + L1 10µH +3.3V R9 R1 +3.3V + 470K C16 470nF Reset + SPDIF IN SDA SCL VDD18 VSS18 ADR_SEL HP_DET VDD18_CONV VSS18_CONV HL_LSS_R HP_LSS_L LS_SUB LS_R LS_L LS_C SCR_FLT SCL_FLT SC3_IN_R SC3_IN_L VDD33_CONV VSS33_CONV + SPDIF OUT + L4 C18 100nF TQFP80 C19 100nF IC1 STV82x7 +3.3V + 10µH + C17 10µF + C46 1µF + 10µF C45 1µF SC1 IN Right C73 C47 330pF + R7 R6 220 C72 330pF + C41 10µF C25 100nF 220 C44 100nF 10µF + + +1.8V C 42 100nF R5 220 330pF R4 220 C26 100nF C27 100nF 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 C21 1.8V 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 VSS18 VDD18 RST_N SPDIF_IN SPDIF_OUT VDD33_IO VSS33_IO CK_TST_CTRL VSS18 VDD18 CLK_SEL XTALIN/CLKXTP XTALOUT/CLKXTM VCC18_CLK1 GND18_CLK1 GND18_CLK2 VCC18_CLK2 VSS33_IO VDD33_IO I2S_PCM_CLK 10µH L12 C71 330pF C70 +8V VCC_NISO SC2_OUT_R SC2_OUT_L GND33_LS VCC33_LS SC2_IN_R SC2_IN_L VBG GND_SA VREFA SC1_IN_R SC1_IN_L GND33_SC VCC33_SC SC3_OUT_R SC3_OUT_L GND_H VCC_H SC1_OUT_R SC1_OUT_L 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 27pF + + I2S_SCLK I2S_LR_CLK I2S_DATA0 I2S_DATA1 I2S_DATA2 VDD18 VSS18 BUS_EXP IRQ GND_PSUB VDD18_ADC VSS18_ADC SIF_P SIF_N GND_PWIF VCC18_IF GND18_IF MONO_IN SC4_IN_L SC4_IN_R C22 XT1 27MHz CRYSTAL + 1.8V Figure 7: STV82x7 Application Diagram 27pF C37 + + C33 100nF + C43 47µF L10 10µH C34 22nF L6 1.8V C32 220nF 10µH + C23 47µF R3 560 10µH C29 100nF C 30 100nF L11 + + + + + + 18/156 C8 1µF C7 1µF C6 1µF C5 1µF C4 1µF C3 1µF S C3 IN Right SC3 IN Left C61 1µF C60 1µF C59 47µF SC2 OUT Right SC2 OUT Left C56 10µF C55 10µF SC2 IN Right SC2 IN Left 100nF C51 10µF C50 100nF C49 C53 1µF C54 1µF C52 SC1 IN Left SC3 OUT Right 10µF C48 SC3 OUT Left SC1 OUT Right SC1 OUT Left 1µF 1µF C36 1µF C38 SC4 IN Right SC4 IN Left Mono IN C40 10µF C39 10µF +1.8V C35 IRQ 100pF BUS EXPANDER I2S DATA 2 I2S DATA 1 I2S DATA 0 I2S LR CLK I2S SCLK I2S PCM CLK SIF LS Center LS Left LS Right Subwoofer HP Left/LS surround Left General Description HP Right/LS surround Right STV82x7 STV82x7 with LS Center LS Left LS Right Subwoofer HP Left/LS surround Left HP Right/LS surround Right L17 +1.8V + C9 330µF L18 C69 33nF 100µH C68 33nF C67 33nF C66 33nF C65 33nF C64 33nF L8 * 10µH * L16 100µH C10 100nF L15 100µH * * L14 Headphone detection 100µH 1 1 * L13 +3.3V SL1 100µH 2 C63 10µF C13 100nF C62 33nF + C78 3 Address select 3 100µH * 100nF C12 + + SCL SDA 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 C14 100nF +3.3V 0 R13 220 C58 100nF + C77 10µF C57 100nF 0 + R19 C76 10µF 0 R11 R8 220 C74 330pF R9 L2 10µH +8V R1 +3.3V + 470K Reset C16 470nF C15 R14 0 100nF 330pF + SPDIF IN + SDA SCL VDD18 VSS18 ADR_SEL HP_DET VDD18_CONV VSS18_CONV HL_LSS_R HP_LSS_L LS_SUB LS_R LS_L LS_C SCR_FLT SCL_FLT SC3_IN_R SC3_IN_L VDD33_CONV VSS33_CONV SPDIF OUT R10 330 +8V + L7 +3.3V C18 100nF TQFP80 C19 100nF IC1 STV82x6 / STV82x7 10µH + + C17 10µF R18 0 + C46 1µF + 10µF C45 1µF SC1 IN Right R7 220 +1.8V C25 100nF R6 + 1 +1.8V 220 C72 330pF C73 330pF + C43 10µF 10µH L3 +8V SL2 C42 100nF C21 C26 100nF C27 R15 0 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 C44 100nF + + 2 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 VSS18 VDD18 RST_N SPDIF_IN SPDIF_OUT VDD33_IO VSS33_IO CK_TST_CTRL VSS18 VDD18 CLK_SEL XTALIN/CLKXTP XTALOUT/CLKXTM VCC18_CLK1 GND18_CLK1 GND18_CLK2 VCC18_CLK2 VSS33_IO VDD33_IO I2S_PCM_CLK VCC_NISO SC2_OUT_R SC2_OUT_L GND33_LS VCC33_LS SC2_IN_R SC2_IN_L VBG GND_SA VREFA SC1_IN_R SC1_IN_L GND33_SC VCC33_SC SC3_OUT_R SC3_OUT_L GND_H VCC_H SC1_OUT_R SC1_OUT_L R5 220 330pF R4 220 330pF C71 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 3 + I2S_SCLK I2S_LR_CLK I2S_DATA0 I2S_DATA1 I2S_DATA2 VDD18 VSS18 BUS_EXP IRQ GND_PSUB VDD18_ADC VSS18_ADC SIF_P SIF_N GND_PWIF VCC18_IF GND18_IF MONO_IN SC4_IN_L SC4_IN_R XT1 27MHz CRYSTAL 100nF R2 + C40 10µF C39 10µF C70 1 +1.8V + SL3 270k C37 + + 2 R16 C36 0 C33 100nF C32 220nF + C79 47µF L4 10µH L5 10µH C34 C35 +3.3V +1.8V 1µF C22 1.8V 10µH 3 L6 + C23 47µF Figure 8: STV82x6/STV82x7 Compatible Application Electrical Diagram 560 10µH C29 100nF L11 22nF R17 C30 100nF C31 100nF 0 R3 100pF General Description 19/156 Note : components with * are only mandatory in case of DOLBY certification + + + C61 1µF C60 1µF C59 47µF L1 10µH C75 C56 10µF C55 10µF C53 1µF C54 1µF C52 100nF C51 10µF C41 10µF R12 82 +8V C47 10µF C48 10µF C38 1µF 1µF + + + + C8 1µF C7 1µF C6 1µF C5 1µF C4 1µF C3 1µF + Part L1 L2 L3 L4 L5,L6 L8 L13,L14 L15,L16 L17,L18 R2 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 C3 C9 C10,C13 C15,C18 C21,C22 C23 C27,C29 C30 C31 C41 C42 C43 C59 C63 C64,C65 C66,C67 C68,C69 C70,C71 C72,C73 C74,C75 C76,C77 C78 C79 SL2 SL3 with STV82x6 Not Connected 10µH Not Connected 10µH Not Connected Not Connected strap strap strap 270K 330 Not Connected 82 Not Connected 0 ohm 0 ohm Not Connected Not Connected 0 ohm Not Connected Not Connected Not Connected Not Connected Not Connected 22 pF Not Connected Not Connected Not Connected 100 nF 10 µF Not Connected Not Connected 10 µF 100 nF Not Connected Not Connected Not Connected Not Connected Not Connected Not Connected 10 µF 10 µF 10 µF between 2-3 between 2-3 STV82x7 10µH Not Connected 10µH Not Connected 10µH 10µH 100µH * 100µH * 100µH * Not Connected Not Connected 0 ohm Not Connected 0 ohm Not Connected Not Connected 0 ohm 0 ohm Not Connected 0 ohm 1 µF 330 µF 100 nF 100 nF 27 pF 47 µF 100 nF 100 nF Not Connected Not Connected 100 nF 10 µF 47 µF 33 nF 33 nF 33 nF 33 nF 330 pF 330 pF 330 pF Not Connected Not Connected 47 µF between 1-2 between 1-2 SC3 IN Right SC3 IN Left SC2 OUT Right SC2 OUT Left SC2 IN Right SC2 IN Left C50 100nF C49 SC1 IN Left SC3 OUT Right SC3 OUT Left SC1 OUT Right SC1 OUT Left SC4 IN Right SC4 IN Left Mono IN SIF IRQ BUS EXPANDER / BUS I2S DATA 2 / BUS1 I2S DATA 1 / SCK I2S DATA 0 / WS I2S LR CLK / SDI I2S SCLK / SDO I2S PCM CLK General Description L17 * + C9 330µF L18 * C10 100nF 100µH L14 * 100µH L13 * 100µH 1 L15 * 100µH L16 * 100µH C69 33nF 100µH C68 33nF C67 33nF C66 33nF C65 33nF C64 33nF +1.8V L2 10µH Headphone detection 1 +3.3V SL1 100nF C12 2 3 Address select C13 C62 33nF C63 33nF 3 + + SCL 100nF SDA +3.3V C14 100nF R1 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 3 +3.3V C75 C58 100nF 100nF 470K C15 R9 220 330pF SL1 ( see Table 1) R8 C74 220 C57 100nF 330pF + C16 470nF Reset 2 + SPDIF IN 1 + SDA SCL VDD18 VSS18 ADR_SEL HP_DET VDD18_CONV VSS18_CONV HL_LSS_R HP_LSS_L LS_SUB LS_R LS_L LS_C SCR_FLT SCL_FLT SC3_IN_R SC3_IN_L VDD33_CONV VSS33_CONV SPDIF OUT + L4 C19 100nF TQFP80 IC1 STV82x7 or STV82x8 +3.3V + + 10µH + C17 10µF C18 100nF + C46 1µF 10µF + + R7 220 R6 220 C72 330pF C42 100nF R5 220 330pF R4 220 C71 + 10µH L12 +8V C41 10µF C25 100nF 330pF C44 100nF + + +1.8V C26 100nF C27 100nF C21 + 1.8V 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 C73 VSS18 VDD18 RST_N SPDIF_IN SPDIF_OUT VDD33_IO VSS33_IO CK_TST_CTRL VSS18 VDD18 CLK_SEL XTALIN/CLKXTP XTALOUT/CLKXTM VCC18_CLK1 GND18_CLK1 GND18_CLK2 VCC18_CLK2 VSS33_IO VDD33_IO I2S_PCM_CLK + VCC_NISO SC2_OUT_R SC2_OUT_L GND33_LS VCC33_LS SC2_IN_R SC2_IN_L VBG GND_SA VREFA SC1_IN_R SC1_IN_L GND33_SC VCC33_SC SC3_OUT_R SC3_OUT_L GND_H VCC_H SC1_OUT_R SC1_OUT_L 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 27pF + I2S_SCLK I2S_LR_CLK I2S_DATA0 I2S_DATA1 I2S_DATA2 VDD18 VSS18 BUS_EXP IRQ GND_PSUB VDD18_ADC VSS18_ADC SIF_P SIF_N GND_PWIF VCC18_IF GND18_IF MONO_IN SC4_IN_L SC4_IN_R C22 XT1 27MHz CRYSTAL C70 330pF C37 1µF + 1.8V 27pF 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 + + + R11 L6 100nF 10µH + + L10 1.8V C32 220nF C43 47µF 10µH + C23 +1.8V SIF C34 22nF C35 IRQ 47µF 10K C33 R3 560 10µH C29 100nF C30 100nF L11 L11 Figure 9: STV82x7/STV82x8 Compatible Application Electrical Diagram (TQFP80) Note 1 : components with * are only mandatory in case of Dolby certification STV82x7 Note 2 : C35 value is 100 pF for STV82x7 and 150pF for STV82x8 + + + + + + + + 20/156 Table 1 : SL1 configuration STV82x7 : between 2 and 3 (pin 20 connected to 3.3V) STV82x8 : between 1 and 2 (pin 20 connected to ground) C8 1µF C7 1µF C6 1µF C5 1µF C4 1µF C3 1µF SC3 IN Right SC3 IN Left C61 1µF C60 1µF C59 47µF L1 10µH SC2 OUT Right SC2 OUT Left C56 10µF C55 10µF SC2 IN Right SC2 IN Left 100nF C51 10µF C50 100nF C49 C53 1µF C54 1µF C52 C45 1µF SC1 IN Right C47 10µF C48 10µF SC1 IN Left SC3 OUT Right SC3 OUT Left SC1 OUT Right SC1 OUT Left C38 1µF R12 10K C36 1µF SC4 IN Right SC4 IN Left Mono IN C40 10µF C39 10µF BUS EXPANDER I2S DATA 2 I2S DATA 1 I2S DATA 0 I2S LR CLK I2S SCLK I2S PCM CLK LS Center LS Left LS Right Subwoofer HP Left/LS surround Left HP Right/LS surround Right STV82x7 System Clock 2 System Clock The System Clock integrates 2 independent frequency synthesizers. The first frequency synthesizer can be used in one of two modes: ● ● In Mode 1, it is used by the demodulator, and the frequecy is 49.152 MHz. In Mode 2, it is used by the I²S input and is synchronous with the input frequency (fS = 32, 44.1 or 48 kHz) and the frequency is 49.152 MHz (for fS = 32 or 48 kHz) or 45.1584 MHz (for fS = 44.1 kHz). The second frequency synthesizer is used by the DSP core and can be adjusted between 100 and 150 MHz depending on the application (around 106 MHz at reset value). In I²S output mode, clocks are generated by synthesizer 1. The default values are designed for a standard 27 MHz reference frequency provided by a stable single crystal or an external differential clock signal (for example, from the STV35x0) depending on the CLK_SEL pin configuration (CLK_SEL = 1 means a single crystal, 0 means an external differential clock). The 27 MHz value is the recommended frequency for minimizing potential RF interference in the application. The sinusoidal clock frequency, and any harmonic products, remain outside the TV picture and sound IFs (PIF/SIF) and Band-I RF. Note: A change in the reference frequency is compatible with other default I²C programming values, including those of the built-in Automatic Standard Recognition System. 21/156 Digital Demodulator STV82x7 3 Digital Demodulator The Digital Demodulator (see Figure 10) is composed of two channels. The first channel demodulates an FM or an AM signal. The second channel demodulates FM 2-carrier or NICAM signals (stereo demodulation). All channel parameters are programmed automatically by the built-in Automatic Standard Recognition System (Autostandard) in order to find the correct sound standard. Channels can also be programmed manually via the I²C interface for very specific standards not included among the known standards. Figure 10: Demodulator Block Diagram Channel 1 = Mono Left AM Demodulator DCO1+ Mixer CAROFFSET1 (22h) Channel Filter FIR1 FM Demodulator AM AM/FM Mono (To Sound Preprocessing) FML AUTOSTD_STATUS (8Eh) SIF AGC Amp A/D AUTOSTD AGC Control AGC_CTRL (0Eh) AGC_GAIN (0Fh) AUTOSTD_TIMERS (8Dh) AUTOSTD_CTRL (8Ah) AUTOSTD_STANDARD_DETECT (8Bh) AUTOSTD_STEREO_DETECT (8Ch) FM Demodulator DCO2 + Mixer Channel Filter FIR2 CAROFFSET2 (3Ah) Channel 2 = Stereo/Mono Right DQPSK Demodulator NICAM Decoder Zweiton Decoder DEMOD_STAT(0Dh) ZWT_STAT (42h) NICAM_STAT(3Fh) FM Stereo (To Sound Preprocessing) NICAM L NICAM R (To Sound Preprocessing) 3.1 Sound IF Signal The Analog Sound Carrier IF is connected to the STV82x7 via the SIF pin. Before Analog-to-Digital Conversion (ADC), an Automatic Gain Control (AGC) is performed to adjust the incoming IF signal to the full scale of the ADC. A preliminary video rejection is recommended to optimize conversion and demodulation performances. The AGC system provides a gain value allowing for a wide range of SIF input levels and is activated for all standards, except L/L’. In this particular case, the sound carrier is AM-modulated and an automatic level adjustment would only damage the transmitted audio signal. A preset I²C parameter is provided to define the gain of the AGC used in Manual mode (Registers AGC_CTRL and AGC_GAIN). Note: For optimum AM demodulation performance, it is recommended to use the MONO Input. 22/156 STV82x7 Digital Demodulator 3.2 Demodulation The demodulation system operates by default in Automatic mode. In this mode, the STV82x7 is able to identify and demodulate any TV sound standard including NICAM and A2 systems (see Table 4) without any external control via the I²C interface. It consists of the two demodulation channels (Channel 1 = Mono Left and Channel 2 = Mono Right/Stereo) to simultaneously process two sound carriers in order to handle all transmission modes (stereo and up to three mono languages). The built-in Automatic Standard Recognition System (Autostandard) automatically programs the appropriate bits in the I²C registers which are forced to Read-only mode for users (see Section 12.1). The programming is optimized for each standard to be identified and demodulated. Each mono and stereo standard can be removed (or added) from the List of Standards to be recognized by programming registers AUTOSTD_STANDARD_DETECT and AUTOSTD_STEREO_DETECT, respectively. The identified standard is displayed in register AUTOSTD_STATUS and any change to standard is flagged to the host system via pin IRQ. This flag must be reset by re-programming the MSBs of register AUTOSTD_CTRL while checking the detected standard status by reading registers AUTOSTD_STATUS, NICAM_STAT and ZWT_STAT. Moreover, the detection of Stereo mode during demodulation is also flagged in register AUTOSTD_STATUS. Important: L/L’ and D/K standards cannot be automatically processed because the same frequency is used for the MONO carrier. An exclusive L/DK selection must programmed in register AUTOSTD_CTRL. This may be externally controlled by detecting the RF modulation sign, which is negative for all TV standards except L/L’. To recover out-of standard FM deviations or the Sound Carrier Frequency Offset, additional I²C controls are provided without interfering with the Automatic Standard Recognition System (Autostandard). DK-NICAM Overmodulation Recovery: Four different FM deviation ranges can be selected (via register AUTOSTD_CTRL) for the DK standard while the Autostandard system remains active. The maximum FM deviation is 500 kHz in DK Mono mode and 350 kHz in DK NICAM mode (limited by overlapping FM and NICAM spectrum values). The demodulated signal peak level (proportional to the FM deviation) is detected by the Peak Detector and written to registers PEAK_DET_L and PEAK_DET_R. This value is used to implement Automatic Overmodulation Detection via an external I²C control. Important: Only the selection of the 50 kHz FM deviation standard is compatible with the other DKA2* standards (DK1, DK2 or DK3). These standards must be removed from the list of standards (registers AUTOSTD_STANDARD_DETECT and AUTOSTD_STEREO_DETECT) when programming larger FM deviations reserved only for DK-NICAM standards. Table 4: Recognized Standards Type Name Carrier 1 (MHz) 5.5 5.5 A2 5.5 6.5 6.5 A2* 6.5 5.850 6.258 27 50 80 J17 50 µs 40 54.6875 23/156 5.850 5.742 27 27 50 50 80 80 J17 50 µs 40 54.6875 Carrier 2 (MHz) Roll Pilot De-off Frequency emphasis (%) (kHz) Nom. Max. Over FM Deviation System Sound Type FM Mono B/G FM/NICAM FM 2-Carrier FM Mono D/K FM/NICAM D/K1 FM 2-Carrier Digital Demodulator Table 4: Recognized Standards (Continued) Type Name A2* A2* Carrier 1 (MHz) 6.5 6.5 6.0 6.0 6.5 4.5 A2+ 4.5 4.724 6.552 5.850 15 15 27 27 50 50 27 50 80 J17 J17 75 µs 75 µs 100 40 Carrier 2 (MHz) 6.742 5.742 STV82x7 System Sound Type Roll Pilot De-off Frequency emphasis (%) (kHz) Nom. Max. Over 50 µs 50 µs 54.6875 54.6875 FM Deviation D/K2 D/K3 I FM 2-Carrier FM 2-Carrier FM Mono FM/NICAM L M/N AM/NICAM FM Mono FM 2-Carrier 55.069 For Chinese TV transmissions (DK-NICAM) which are subject to overmodulation, different FM deviations are proposed for sound demodulation. Sound Carrier Frequency Offset Recovery: Both Mono and Stereo IF Carrier frequencies can be adjusted independently (registers CAROFFSET1 and CAROFFSET2) within a large range (up to 120 kHz for standard mono FM deviations) while the Automatic Standard Recognition System remains active. The frequency offset estimation is written in registers DC_REMOVAL_L and DC_REMOVAL_R (Mono Left / Channel 1 and Mono Right / Channel 2, respectively) and can be used to implement the Automatic Frequency Control (AFC) via an external I²C control. Manual Mode: If required, the Automatic Standard Recognition System system can be disabled (Manual mode) and the user can control all registers including those only controlled by the Automatic Standard Recognition System function when active. Manual mode is selected in register AUTOSTD_STANDARD_DETECT (bit LDK_SCK, I_SCK, BG_SCK and MN_SCK set to 0). 24/156 STV82x7 Dedicated Digital Signal Processor (DSP) 4 Dedicated Digital Signal Processor (DSP) A dedicated Digital Signal Processor (DSP) takes charge of all audio processing features and the low frequency signal processing features of the demodulator. The internal 24-bit architecture will ensure a high quality signal treatment and an excellent dynamic. 4.1 Back-end Processing The “back-end” processing corresponds to the low frequency signal processing (32 kHz or higher frequencies) of the demodulator and other inputs (I²S, ADC). Figure 11 shows a flowchart of the back-end processing tasks. However, the figure shows that the processing is only a SINGLE SOURCE PROCESSING flow (no processing is possible with “Demod + SCART” and I²S inputs simultaneously) and that the selection of a headphone output restricts the loudspeakers configuration to 2+1 instead of 5+1. Figure 11: Back-end Audio Processing “Demod + SCART” or “SCART only” Input Modes Autostandard FM Channel1 FM Channel2 DC Removal Stereo Peak Detector: 9D, bit 7 = 1 FM De-emphasis FM Prescale FM Dematrix Stereo Peak Detector: 9D, bit 7 = 0 2 LS Digital Audio Matrix (L and R) NICAM L NICAM R DC Removal NICAM De-emphasis NICAM Prescale NICAM Dematrix 2 HP (L and R) 2 SCART (L and R) SCART L SCART R DC Removal SCART Prescale Stereo Peak Detector: 9D, bit 7 = 1 Stereo Peak Detector: 9D, bit 7 = 0 “I2S” Input Mode I2S in 1 I2S in 2 I2S in 3 2 to 6 LS (L,R,C,LFE,Ls,Rs) SRC X2/X4 I²S Prescale DownMix 2 HP (L and R) 2 SCART (L and R) 25/156 Dedicated Digital Signal Processor (DSP) The main features depend on the path: ● STV82x7 FM Channel — DC Removal — Prescaling — De-emphasis (50 or 75 us) — Stereo Dematrix ● NICAM Channel — DC Removal — Prescaling — De-emphasis (J17) — Dematrix ● Input SCART Channel — DC Removal — Prescaling ● Input I²S Channel — I²S Prescaling Digital Audio Matrix — Audio Channel Multiplexer between the different sources (IF, I²S, SCART) towards all outputs (S/PDIF, LS, HP or SCART). ● ● Autostandard management — device configuration depending on the standard to be detected — freeze the device when a standard is detected — once a standard detected, check that there is no change in the detection status — set the correct action depending on any change in the detection status (mono backup or mute setup and new standard detection) ● SCART — Downmixing: LT / RT or L0 / R0 (see AC-3 specification) — Soft Mute 4.2 Audio Processing The following software is provided for main loudspeakers (L, R, C, LS, RS, SubW): ● ● ● Downmix ST WideSurround, ST OmniSurround, SRS ST Dynamic Bass Smart Volume Control (SVC) 5-band Equalizer or Bass-Treble Loudness Volume with independent channels (Smooth Volume Control) Master Volume Control Mute/soft-mute ● ● ● ● ● ● ● 26/156 ® ® Virtual Dolby Surround and Virtual Dolby Digital) ® ® ™ ® ® ® Dolby Pro Logic II Decoder (LT, RT → L, R, C, Ls, Rs, SubW) with Bass Management WOW or SRS TruSurround XT (certified STV82x7 ● ● ● ● ● Dedicated Digital Signal Processor (DSP) Balance Beeper Pink Noise Generator (used to position the loudspeakers) Programmable Delay for each loudspeaker Adjustable Delay for “lip sync” to compensate audio/video latency up to 60 ms in SCART Only Mode (processing at 48 KHz) and up to 90 ms in Demodulator and SCART Mode (processing at 32 KHz) The following software is provided for the headphone or auxiliary output: ● ● ● ● ● ● ● ● ● ● Downmix Smart Volume Control (SVC) Bass/Treble Loudness Independent Volume for each channel (Smooth Volume Control) Soft Mute Balance Beeper Adjustable Delay for “lip sync” up to 120 ms (to compensate audio/video latency) in SCART Only Mode and up to 180 ms in Demodulator and SCART Mode The following software is provided for SCART or S/PDIF outputs: ● ● Downmix Soft Mute ™ ® SRS TruBass 27/156 IF I2S Audio Matrix for Demod/SCART input DownMix for I2S inputs L 90ms / R 60ms C LFE Ls Rs Decoder 2 to N Dolby Prologic I SCART 28/156 AutoStd L SCART FM Dematrix R SCART DC Removal FM FM Deemphasis Prescale DC Removal NICAM NICAM Deemphasis Prescale NICAM Dematrix SRC x2 x4 I2S Prescale L R C LFE Ls Rs L R C Ls Rs Virtualiser N to 2 L R C Ls Rs L HP L SRS TruSurround XT R ST Wide Surround L HP 90ms / R HP 60ms R HP DC Removal SCART Prescale Dedicated Digital Signal Processor (DSP) Figure 12: STV82x7 Audio Processing Flowchart (Front End) Peak Detector Noise Generator L R C LFE Ls Rs STV82x7 STV82x7 S/PDIF Copy Digital Soft Mute S/PDIF Output L SCART Volume Digital Balance Soft Mute SCART Output L R TruBass XT Bass / Treble or 5 bands Equalizer Volume Digital Balance Soft Mute R SCART S LS Output C Loudness Bass Mgmt Volume Volume Digital Soft Mute Center Output LFE 2/0 and 3/2 SVC Digital Soft Mute Subwoofer Output Ls Rs L HP R HP TruBass XT SVC Bass/ Treble Loudness Digital Volume Soft Balance Mute S Beeper Figure 13: STV82x7 Audio Processing Flowchart (Back End) Headphone Output Output Select I2S Out Select Dedicated Digital Signal Processor (DSP) Digital Volume Soft Balance Mute Surround Output 29/156 Dedicated Digital Signal Processor (DSP) STV82x7 4.3 ST WideSurround STV82x7 offers three preset ST WideSurround Sound effects on the Loudspeakers path: ● ● ● Music, a concert hall effect Movie, for films on TV Simulated Stereo, which generates a pseudo-stereo effect from mono source “ST WideSurround Sound” is an extension of the conventional stereo concept which improves the spatial characteristics of the sound. This could be done simply by adding more speakers and coding more channels into the source signal as is done in the cinema, but this approach is too costly for normal home use. The ST WideSurround system exploits a method of phase shifting to achieve a similar result using only two speakers. It restores spatiality by adding artificial phase differences. The Surround/Pseudo-stereo mode is automatically selected by the Automatic Standard Recognition System (Autostandard) depending on the detected stereo or mono source. By default, “Movie” is selected for Surround mode. This value may be changed to “Music” by the STSRND_MODE bit in the STSRND_CONTROL register. Additional user controls are provided to better adapt the spatial effect to the source. The ST WideSurround Gain (STSRND_LEVEL) and ST WideSurround Frequency (STSRND_FREQ) registers can be used to enhance Music Predominancy in Music mode and Theater effect and Voice Predominancy in Movie mode. 4.4 ST OmniSurround STV82x7 offers a spatial virtualizer to output any multi-channel input in stereo on the Loudspeakers path: “ST OmniSurround” will recreate a multi-channel spatial sound environment using only the Left and Right front speakers. It can be adapted to any input configuration (OMNISRND_INPUT_MODE). ST Voice will allow you to enhance the voice content of your program to increase the intellegibility and the presence of the sound. 4.5 Dolby Pro Logic II Decoder Dolby Pro Logic II is a matrix decoder that decodes the five channels of surround sound that have been encoded onto the stereo sound tracks of Dolby Surround program material such as DVD movies and TV shows. It is even possible to decode standard stereo signals like music or non encoded movies. Furthermore, it is an active process designed to enhance sound localization through the use of very high-separation decoding techniques. 4.6 Bass Management This processing will generate the subwoofer signal and adjust all loudspeakers channels gain and bandwidth. Speakers capable of reproducing the entire frequency range will be referred to as “full range speakers”, then signals sent to full range speaker will be full bandwidth (no filtering). 30/156 ® ® ® The Dolby Pro Logic II in a specific mode. decoder is also able to emulate the former Dolby ® ® ® ® Pro Logic decoder STV82x7 Dedicated Digital Signal Processor (DSP) Speakers that have limited bass handling capabilities will be referred to as “satellite speakers”, then signals sent to satellite speaker will be high-pass filtered to remove bass information below 100 Hz. In the STV82x7, five output configuration modes have been implemented according to “Dolby Digital Consumer Decoder” specifications. They are described below. 4.6.1 Bass Management Configuration 0 In some cases, the bass management filters are available in the decoder itself, so there is no need to reproduce these filters. The output configuration shown in Figure 14 offers this possibility. Figure 14: Bass Management Configuration 0 (with Pro Logic switch indicating its reset state) L L R R C Pro Logic OFF Switch Ls C Ls Rs -15 dB LFE -5 dB + Rs SubW 31/156 Dedicated Digital Signal Processor (DSP) 4.6.2 Bass Management Configuration 1 STV82x7 Configuration 1, shown in Figure 15, assumes that all five speakers are not full range and that all of the bass information will be redirected to and reproduced by a single subwoofer. This configuration is intended for use with 5 satellite speakers. To prevent signal overload, the five main channels are attenuated by 15 dB, while the LFE channel is attenuated by 5 dB to maintain the proper mixing ratio. Figure 15: Bass Management Configuration 1 (with Pro Logic switch indicating its reset state) L L R R C Pro Logic OFF Switch Ls C Ls Rs -15 dB LFE -5 dB + Rs SubW 32/156 STV82x7 4.6.3 Bass Management Configuration 2 Dedicated Digital Signal Processor (DSP) Configuration 2 assumes that the left and right speakers, are full range while the center and surround speakers are smaller speakers. Also, all bass data is redirected to the left and right speakers. This configuration include output level adjustment that allows 12 dB attenuation for the 3 smaller speakers (C, Ls, Rs). When the level adjustment will be disabled the decoder boosts by 12 dB the full range speakers (Left, Right). Figure 16: Bass Management Configuration 2 (all switches indicate their reset state) Level Adjustment OFF Switch L -12 dB + -1.5 dB C -12 dB C R +12 dB -1.5 dB -12 dB Ls + -12 dB Rs -15 dB LFE -5 dB + SubW Rs Subwoofer ON Switch Ls L +12 dB R Pro Logic OFF Switch -12 dB + 33/156 Dedicated Digital Signal Processor (DSP) 4.6.4 Bass Management Configuration 3 STV82x7 The third configuration, shown in Figure 17, assumes that all speakers except the center are full range, then all bass information will be directed to and reproduced by the front left and front right and both surround speakers. In order to provide more flexibility to this configuration, a switch will offer an option which will produce a subwoofer channel by the LFE channel. When the Subwoofer Switch is OFF, the input channels will be attenuated by 8 dB. Configuration 3 is required in certain high-end products. Figure 17: Bass Management Configuration 3 (all switches indicate their reset state) Level Adjustment OFF Switch + L L -8dB -4dB + +8dB +4dB +8dB +4dB C C -8dB -4dB -4.5 dB R -8dB -4dB + + R +8dB +4dB + +8dB +4dB + +8dB +4dB Rs Ls Ls -8dB -4dB -8dB -4dB Rs LFE -8dB -4dB Subwoofer ON Switch Subwoofer ON Switch +10dB SubW 34/156 STV82x7 4.6.5 Bass Management Configuration 4 Dedicated Digital Signal Processor (DSP) This configuration implements the Simplified Dolby configuration. The center, left surround and right surround channels are summed and then filtered by the LPF. The composite bass information is either summed back into the left and right channels or summed with the LFE channel and sent to the subwoofer output, see Figure 18. Figure 18: Implementation of the Bass Management Configuration 4 (Simplified Configuration) L + L C C R Pro Logic OFF Switch Ls + R Ls Rs -4.5dB Subwoofer ON Switch Rs + -10.5dB -5dB + LFE SubW 4.7 SRS WOW and TruSurround XT The SRS TruSurround XT is a processing system that can accept from 1 to 6 channels on input and that will generate a 2-channel output signal. SRS SRS WOW 4.7.1 SRS TruSurround The SRS TruSurround is a processing that can accept from 2 to 5 channels on input and that will generate a 2-channel output signal. SRS TruSurround uses Head-Related Transfer Function (HRTF) -based frequency tailoring of (L/R) difference signals to extend the sound image out past the physical boundaries of the speaker placements to surround channel information. These rear channel HRTF curves have much greater peak to valley differences at center frequencies. These were chosen to cause rear channel difference signals to virtualize farther behind the listener and directed to a different virtual position as compared to front channel signals. Information that is equal (L+R) in the rear surround channels ® ● TruSurround ® ® ™ ® ® ® ● (Multi-channel signal virtualizer) ® This processing system includes the latest SRS ™ ® algorithms: ® 35/156 Dedicated Digital Signal Processor (DSP) STV82x7 is processed by an identical HRTF curve but mixed in at a much lower amount. This HRTF processing of equal (L/R) signals was again used to virtualize information to the rear of the listener. 4.7.2 SRS WOW ● ● ● 4.7.2.1 SRS 3D Mono/Stereo This system is used to create a pseudo-stereo signal for mono inputs or a three-dimensional spatial signal for stereo inputs. 4.7.2.2 SRS Dialog Clarity This system is used to enhance dialog perception. 4.7.2.3 SRS TruBass The SRS TruBass audio enhancement technology provides deep, rich bass to small speaker systems without the need for a subwoofer or additional extra physical components. For systems with a subwoofer, TruBass complements and enhances bass performance. Psycho-acoustically, when the human ear is presented with a low frequency sound signal that is missing the fundamental harmonic, it will fill in the fundamental frequency based on the higher harmonics that are present. By accentuating the second and higher frequency harmonics of the bass portion of a signal, TruBass gives the perception of greatly improved bass response. 4.8 Smart Volume Control (SVC) The Smart Volume Control regulates the audio signal level before audio processing. This regulation is necessary in order for the signal level to be independent from the source (terrestrial channels, I2S or SCART), its modulation (AM, FM or NICAM) and annoying volume changes (advertising, etc.). The Smart Volume Control works as an audio compressor/expander; i.e. when the input signal exceeds the threshold level, a very rapid attenuation (-2 dB/ms) is applied to rescale the signal down to the threshold value. When the input signal is below the threshold level, the previous attenuation is reduced slowly in order to retrieve the original input level (0 dB gain). If the input signal is too low, an addition gain of 6 dB can be provided. To personalize the action of the SVC, five parameters are available: 1. Threshold: Maximum quasi-peak level that can be expected on output 2. Peak measurement mode: Select the channel on which the peak measurement must be performed (Left, Right, Center...) 3. Release time: Gain slope applied to the amplification phase 4. Expander switch: To allow a +6dB amplification of small signals in order to reduce the output dynamic range 5. Make up gain: Allows compensation of the signal amplitude limitation thanks to a 0 to 24 dB adjustable gain. 36/156 ™ ® SRS TruBass is implemented on loudspeakers path, headphone path or on both in parallel. ™ ™ ™ SRS TruBass ™ SRS Dialog Clarity ™ SRS 3D Mono/Stereo ™ ® ® ® ® The SRS WOW is an a sound processing system including: ® The SRS TruSurround is certified by Dolby Laboratories to be a Virtual Dolby Virtual Dolby Surround. Digital and ® ® ® ® ™ STV82x7 Dedicated Digital Signal Processor (DSP) The SVC is implemented on the loudspeakers path, headphone path or on both in parallel (independent settings). Also, the SVC can be applied in six-channel mode (L, R, LS, RS, C and SubW). 4.9 ST Dynamic Bass STV82x7 offers dynamic bass boost processing on the Loudspeakers path: ST Dynamic Bass is a bass boost process that can dramatically increase the bass content of any program without any output level saturation. 3 cutoff frequencies (BASS_FREQ) can be chosen, 100 Hz, 150 Hz and 200 Hz to adapt the effect to your loudspeakers. The amount of bass (BASS_LEVEL) can also be fine tuned in order to adapt the effect loudness. 4.10 5-Band Audio Equalizer The loudspeakers audio spectrum is split into 5 frequency bands and the gain of each of band can be adjusted within a range from -12 dB to +12 dB in steps of 0.25 dB. The Audio Equalizer may be used to pre-define frequency band enhancement features dedicated to various kinds of music or to attenuate frequency resonances of loudspeakers or the listening environment. The Equalizer is enabled by the LS_EQ_ON bit in the LS_EQ_BT_CTRL register. The gain value for Band X is programmed in register EQ_BANDX_GAIN. The 5-Band Audio Equalizer is exclusive with Bass-Treble control. Bit LS_EQ_BT_SW in register LS_EQ_BT_CTRL is used to select either the 5-Band Audio Equalizer or the Bass-Treble control for the Loudspeakers path. Depending on the LS Equalizer or LS Bass-Treble value, the volume level can be clamped to the LS output to prevent any possible signal clipping from occuring using the ANTICLIP_LS_VOL_CLAMP bit in the VOLUME_MODES (D7h) register. Figure 19: Equalizer f1 = 100 Hz, f2 = 330 Hz, f3 = 1 kHz, f4 = 3.3 kHz and f5 = 10 kHz 4.11 Bass/Treble Control The gain of bass and treble frequency bands for Headphone can be also tuned within a range from -12 dB to +12 dB in steps of 0.25 dB. It may be used to pre-define frequency band enhancement features dedicated to various kinds of music. The Headphone Bass/Treble feature is enabled by setting the HP_BT_ON bit in the HP_BT_CONTROL register. The Bass and Treble gain values are adjusted in registers HP_BASS_GAIN and HP_TREBLE_GAIN, respectively. Depending on the HP Bass-Treble value, the volume level can be clamped to the HP output to prevent any possible signal clipping from occuring using the ANTICLIP_HP_VOL_CLAMP bit in the VOLUME_MODES (D7h) register. 37/156 Dedicated Digital Signal Processor (DSP) STV82x7 4.12 Automatic Loudness Control As the human ear does not hear the audio frequency range the same way depending on the power of the audio source, the Loudness Control corrects this effect by sensing the volume level and then boosting bass and treble frequencies proportionally to middle frequencies at lower volume. While maintaining the amplitude of the 1 kHz components at an approximately constant value, the gain values of lower and higher frequencies are automatically progressively amplified up to +18 dB when the audio volume level decreases.The maximum treble amplification can be adjusted from 0 dB (first order loudness) to +18 dB (second order loudness) in steps of 3 dB. As the volume is proportional to the external audio amplification power, the loudness amplification threshold is programmable in order to tune the absolute level. The Loudspeakers Loudness function is enabled by setting the LS_LOUD_ON bit in register LS_LOUDNESS. The Loudspeakers Loudness Threshold and Maximum Treble Gain values are also programmed in this register. The Headphone Loudness function is enabled by setting the HP_LOUD_ON bit in register HP_LOUDNESS. The Headphone Loudness Threshold and Maximum Treble Gain values are also programmed in this register. The loudness cut-off frequency is 100 Hz. 4.13 Volume/Balance Control The STV82x7 provides a Volume/Balance Control for all output channels configuration (except for S/PDIF) with different volume level per channel (L, R, C, LS, R S, SubW, SCART). Its wide range (from +11.875 to -116 dB, in a dB linear scale with a 0.125 dB step) largely covers typical home applications (approx. 60 dB) while maintaining a good S/N ratio. Figure 20: Volume Control Output Gain +11.875 dB -116 dB Mute 00h I²C Control 3FFh An extra Master Volume Control can apply an extra gain/attenuation on L, R, C, LS, R S and SubW channels. The Volume/Balance Control can operate in one of two different modes: ● In Differential mode (default value), the volume control is a common volume value for both the Left and Right Loudspeakers or Headphone channels (see Figure 20) and complimentary balance control is used (see Figure 21). 38/156 STV82x7 ● Dedicated Digital Signal Processor (DSP) In Independent mode, the volume for the Left and Right channels for Loudspeakers or Headphone is controlled independently. Figure 21: Differential Balance Output Gain 100% nn el Le ha C ft tC ha ig h nn R el Mute 200h 000h I²C Control (10 bits) 1FFh Note: Each step is 0.25 dB 4.14 Soft Mute Control The Digital Soft Mute is applied smoothly (20 ms for 120 dB range) to avoid any switch noise on output. It is available on all output channels pairs: ● ● ● ● ● ● S/PDIF channel (Left/Right) SCART channels (Left/Right) Loudspeakers channels (Left/Right) Center Subwoofer Headphone/Surround channels (Left/Right) Another soft mute (analog) is also available on each DAC output. 4.15 Beeper The beeper is used to generate a tone on the Loudspeakers or/and Headphone outputs. The beeper sound (square wave) is added to the audio signal which is attenuated by 20 dB. The beep sound amplitude includes a smooth attack and decay to avoid any parasitic noise when starting and stopping. It can be used for various applications such as beep sounds for remote control, alarm clock or other features. The Beeper operates in one of two modes: ● Pulse mode (beep applications): A tone with a programmable short duration (0.1, 0.25, 0.5 and 1.0 s) is generated. Afterwards, the beeper is automatically disabled and the output is switched back to the audio signal, see Figure 22. Continuous mode (alarm application): A tone with a programmable long duration is generated. Its start and stop controls must be programmed by I²C, see Figure 23. ● The Beeper function is enabled by setting the BEEPER_ON bit in register BEEPER_ON. Beeper parameters are controlled in register BEEPER_MODE. 39/156 Dedicated Digital Signal Processor (DSP) STV82x7 The beeper tone level and frequency are programmed in register BEEPER_FREQ_VOL. The level (or volume) ranges between 0 dB and -93 dB in steps of 3 dB and the tone frequency ranges between 62.5 Hz and 8 kHz in steps of 1 octave. A beep generator is shared only by the Loudspeakers or Headphone outputs. Therefore, in the event of simultaneous beeps when in Pulse mode, only the first beep will define the effective duration that will be the same for both outputs. Figure 22: Pulse Mode BEEP_ON = 1 BEEP_ON = 0 0.1, 0.25, 0.5 and 1.0 s T predefined 62.5 Hz < f < 8 kHz Figure 23: Continuous Mode BEEP_ON = 1 T defined by I²C write BEEP_ON = 0 62.5 Hz < F < 8 kHz 4.16 Internal Audio/Video Delay (Lip Sync) Since increasing processing on the video signal implies more delay compared to the audio signal, there is a possibility inside the device of compensating by inserting a delay on the audio path in order to resynchronize the two signals: ● ● 60ms with 48 KHz sampling frequency (SCART only input mode) 90ms with 32 KHz sampling frequency (demodulator input mode) The same delay is available for the LS path and/or the HP path. 40/156 STV82x7 Analog Audio Matrix (In / Out) 5 Analog Audio Matrix (In / Out) The analog part of the audio matrix can be divided into two parts: the SCART input matrix and the SCART output matrix. Figure 24: SCART Input Matrix S1in S2in S3in S4in MONO_in Select Audio ADC 2 Digital Matrix The SCART input matrix is an input for the digital matrix (after the ADC) which select which source will be sent to the DSP. Figure 25: SCART1/2/3 Output Matrix S1in S2in S3in S4in Stereo DAC MONO_in 2 Soft mute S1out Select or Mute The SCART output matrix selects the sound to output, which can be directly a SCART input or the output of the DSP. A mute function is provided to switch off the outputs. A soft-mute function is provided to avoid all spurious sounds when switching from one position to another position. The SCART 2 and 3 output matrices have the same functions as the SCART 1 output matrix. The particularity of the matrix is to accept input signal of 2 VRMS and to have the capability to output such level. In this case, the power supply must be 8 V. The Mono audio input is able to accept signals with a 0.5 VRMS amplitude. 41/156 I²S Interface (In / Out) STV82x7 6 I²S Interface (In / Out) The STV82x7 offers three input/output choices: one I²S input, three I²S inputs or one I²S output. 6.1 I²S Inputs The STV82x7 can interface with a digital sound decoder. In this case, the digital data can be input at a speed of 0.384 Mbytes/s (3.072 MHz for a 48 kHz sampling frequency with 32 bits of data).In compliance with Dolby specifications, only the sampling frequency is subject to restrictions. All other requirements are extracted from other various specifications. Sampling Frequency (kHz) Data Size PCMCLK 1. means that the number is the number of effective bits but the transmission is with 32 bits. 2. 512 x fs is used by the DACs if 512 x fs is present. The PCMCLK (possible clock for upsampling) is provided by the master which is the digital sound decoder. A sample rate conversion (SRC) will be necessary in the second case (STV82x7 slave) in order to have a fixed frequency output from this block (either 32 kHz, 44.1 kHz or 48 kHz). Note: The SRC function is only available in single I²S input mode. The I²S interface is used in two ways depending on the package: 1. The interface with one I²S (I²S_DATA0) connection (only stereo or stereo-coded Dolby Logic ); Pro 2. One interface with three I²S connections connected to the DSP to allow the processing of a multi-channel signal (maximum of 6 channels). 42/156 ® ® Table 5: I²S Characteristics 8, 11.025, 12,16, 22.05, 24, 32, 44.1 and 48 16, 18*, 20*, 24*, 32 512 x fS1 2 ® STV82x7 I²S Interface (In / Out) Figure 26: I²S Block Diagram I²S_DATA0 fS Input = 8 to 48 kHz SRC x 2 SRC x 4 I²S_DATA1 fS Input = 32 to 48 kHz I²S_DATA2 fS Input = 32 to 48 kHz I2S_SCLK fS Input * 64 I2S_LR_CLK fS Input = 32 to 48 kHz Audio Processing Note: 1 The I²S input and output modes are exclusive (this means that the I2S_DATA0 can be used as input or as output). 2 Simultaneous processing of I²S inputs and SIF inputs and/or ADC inputs (SCART or MONO inputs) is NOT possible with the device. 3 I2S_PCM_CLK is not needed for the device. Table 6: I²S Frequency Configuration I²S (Max. Number of Channels) 1 (I²S_DATA0) 1 (I²S_DATA0) 3 1 (I²S_DATA0) 1 (I²S_DATA0) 3 1 (I²S_DATA0) 1 (I²S_DATA0) 3 fS Input (kHz) 8 16 32 11.025 22.05 44.1 12 24 48 fS Output (kHz) after SRC 32.0 32.0 32.0 44.1 44.1 44.1 48.0 48.0 48.0 SRC Use x4 x2 No x4 x2 No x4 x2 No Both standard and non-standard modes are available, see Figure 29. 43/156 I²S Interface (In / Out) STV82x7 6.2 I²S Output A digital stereo output (I²S compatible) is also available for routing the demodulated signal or a converted input audio signal to an external device. In this case, the I2S_DATA0 signal and all clock signals are set as outputs by setting bit D6 in register RESET to 1. The STV82x7 I²S drives the serial bus (SCLK, LR_CLK, I²S_DATA0) in master mode in 64.fs format with a sampling frequency (fs) of 32 kHz. The I²S_PCM_CLK signal can be used as a master clock in 512.fs format if required for the slave interface. Both standard and non-standard modes are available, see Figure 29. Figure 27: TQFP 80 I²S Output Block Diagram I2S_DATA0 fS Output = 32 kHz I2S_SCLK fS Output * 64 I2S_LR_CLK fS Output = 32 kHz I2S_PCM_CLK fS Output * 512 Audio Processing 48 kHz DSP Processing Note: The I²S input and output modes are exclusive (this means that the I2S_DATA0 can be used as input or as output). Figure 28: I²S Output Selection LS Output C/Sub Output I2S_DATA0 Srnd/HP Output SCART Output Register 56h: Bits[7:6] 44/156 STV82x7 I²S Interface (In / Out) Figure 29: I²S Data Format: Lch = LOW, Rch = HIGH (I²S Input or Output mode) 1/f s Lch I²S_LR_CLK Rch I²S_SCLK (= 64fs) I²S_DATAx (standard mode) 1 2 3 22 23 24 1 2 3 22 23 24 1 2 MSB I²S_DATAx (non-standard mode) 1 2 3 22 23 24 LSB 1 2 MSB 3 22 23 24 LSB 1 2 3 MSB LSB MSB LSB 45/156 S/PDIF Input/Output STV82x7 7 S/PDIF Input/Output An S/PDIF output is available for connection with an external A/V decoder/amplifier. The signal on this S/PDIF output is selected by an on chip Multiplexer between the internal signal and an external signal present on S/PDIF bypass input (Pin 44) with SPDIF_MUX bit in the DAC_CONTROL register. The outputted internal signal can be selected from: ● ● ● ● L/R C/Subwoofer HP or Surround L/R SCART L/R Digital decoder Mute facility is also provided on the S/PDIF output. Note: The S/PDIF_IN pin (Pin 44) is a CMOS digital pin and input signals on this pin must fulfill the characteristics as mentioned in Section 13.12: Digital I/Os Characteristics on page 144 (±0.5 VPP standard S/PDIF input level is not directly supported by the device and needs external circuitry). 46/156 ® The external signal is for example the signal provided by an external Dolby (STD2000). STV82x7 Power Supply Management 8 Power Supply Management A mixed supply voltage environment requires the following voltages: ● ● ● 3.3 V capable inputs/outputs for digital pins; 1.8 V digital core; 8 V capable inputs/outputs for analog audio interfaces (capability to output 2 V RMS for SCART requirements); 3.3 V for stereo ADC and DAC (analog part); 1.8 V for stereo ADC and DAC (digital part); 1.8 V for IF ADC and AGC. ● ● ● These voltages will be delivered by the application with an accuracy of ±5%. For more information, refer to Section 13.3: Power Supply Data. Other specific DC voltages or features are provided: ● ● Voltage Reference and Biasing Generation (AGC, ADCs, DACs), Bandgap reference. 8.1 Standby Mode (Loop-through mode) The STV82x7 provides a Loop-through mode configuration that bypasses IC functions via a SCART I/O pin (Full Analog Path only). In this case, only a minimum power of 200 mW is required. In Standby mode, the digital and analog power supplies are switched off, except for pins VCC_H, VCC33_LS, VCC33_SC, and VCC_NISO which are used to maintain the SCART path with the last configuration programmed by analog matrixing (register SCART1_2_OUTPUT_CTRL and SCART3_OUTPUT_CTRL). When switching back to normal Full Power mode, all I²C registers are reset except for those used in Standby mode to maintain the original configuration. In Standby mode, the I²C bus does not operate. However, the bus can still be used by other ICs since the I²C I/O pins (SDA and SCL) of the STV82x7 are forced into a high-impedance configuration. 8.2 Power on Reset The following supply voltages are involved for Power on Reset for the STV82x7: ● for 1.8 V: VDD18 on pins 38, 42, 50 and 66, VCC18_CLK1 on pin 54 and VCC18_CLK2 on pin 57. for 3.3 V: VDD33_IOI on pin 46 and VDD33_IO2 on pin 59. ● The first condition for a valid reset is that all 1.8 V supply voltages involved have reached a minimum valid voltage of 1.7 V and that all 3.3 V supply voltages involved have reached a minimum valid voltage of 3.1 V. When this is the case and starting from this point, the reset must be maintained at a low level ( 100 us Hardware Reset Pin HIGH Clock PLL programmation (Note 1) Load Patch File see Figure 32 Note 2 INIT_MEM bit ? (bit 0 in DSP_STATUS register) =1 Check Patch version (FFh register) =1 Device Input Configuration Set-up (if needed) see Figure 33 (If input configuration has to be changed, it has to be done here) (Duration of init phase < 1ms) =0 (HW_RESET bit = 1 is done by patch file at the end of patch loading) =0 HOST_RUN bit = 1 (bit 0 in DSP_RUN register) Delay 2 ms Initialization Procedure (Start DSP processing) NOTE 1: Only when the crystal frequency is not 27 MHz. NOTE 2: The customer can also set bit HW_RESET = 1 here. 52/156 STV82x7 I²C Interface 11.3 Process Flow during Patch Loading and DSP Initialization Patch loading and DSP firmware initialization are shown in Figure 32 Figure 32: Patch Loading and DSP Initialization (Software launch patch loading) Patch Loading HW_RESET bit = 0 (bit 2 in HOST_CMD register) (DSP STOP) Load patch file in memory HW_RESET bit = 1 (bit 2 in HOST_CMD register) (This action is included in the Patch load file) NOTE 1 Firmware Initialization Firmware Init phase (Duration of Firmware initialization is less than 1ms) Write patch version (reg FFh = xxh) Firmware Initialization finished (INIT_MEM = 1) (Firmware set INIT_MEM = 1 (done inside patch file) (bit 0 in DSP_STATUS register)) (Software must test INIT_MEM = 1 before continuing) NOTE 1: The customer can also set HW_RESET = 1 here. (bit 2 in HOST_CMD register) 53/156 I²C Interface STV82x7 11.4 Input Configuration Change The input configuration change must be programmed as shown in Figure 33: Figure 33: Input Configuration change Configuration Change DACs Mute & Wait 50 ms for complete mute Set bit INIT_MEM = 0 & Stop DSP Firmware (HOST_RUN bit = 0 in DSP_RUN register) & Wait 5 ms INIT_MEM bit ? (bit 0 in DSP_STATUS register) =0 =1 Change input configuration Restart DSP Firmware (HOST_RUN bit = 1 in DSP_RUN register) DACs Unmute END 54/156 STV82x7 Register List 12 Note: Register List The unused bits (defined as ‘Reserved’) in the I²C registers must be kept to zero. The system clock registers (from address 08h to 0Bh and from address 5Ah to 5Dh) do not need to be modified if a standard 27 MHz quartz crystal oscillator is used. The default values of the demodulator registers (from address 0Ch to 55h) are for optimum performances and any change is not recommended, except for: ● ● AGC_GAIN (0Fh) to adjust AGC gain for AM carrier in L/L' standard (AGC used in open loop). CAROFFSET1 (22h) and CAROFFSET2 (3Ah) to compensate IF carrier frequency with an out-of-standard offset. Soundlevel Prescaling PRESCALE_AM (94h), PRESCALE_FM (95h), PRESCALE_NICAM (96h) and PRESCALE_SCART (97h) to equalize demodulated or external audio signal before audio processing. Peak detector registers PEAK_DET_INPUT (9Dh), PEAK_DET_L (9Eh), PEAK_DET_R (9Fh), PEAK_DET_L_R (A0h) can be used to measure internal sound level. ● Sound source selection for each audio output channel Loudspeakers, Headphone and SCART to be done using AUDIO_MATRIX_INPUT (A2h). In Multi-lingual mode, AUDIO_MATRIX_LANGUAGE (A4h) selects separately the language for each audio output channel. Register AUTOSTD_CTRL (8Ah) is used to select between L/L' or D/K/K1/K2/K3 standard which can be discriminated automatically. To be used also to change maximum FM deviation (125 kHz, by default) in case of wide overmodulation. AUTOSTD_STANDARD_DETECT (8Bh) and AUTOSTD_STEREO_DETECT (8Ch) to define the list of mono and stereo standards to be recognized automatically. Note: () used in reset value column means that the bit or the byte is read-only. (S) symbol indicates that the field value is represented in signed binary format. (*) The field AGC_ERR[4:0] (AGC_GAIN) can be written by user if the bit AGC_CMD (AGC_CTRL) is set to one (by default controlled by Automatic Standard Recognition System). To be used to adjust manually the input gain of analog AGC amplifier for AM carrier (L/L'). 55/156 Register List STV82x7 12.1 I²C Register Map By default, all I²C registers controlled by Automatic Standard Recognition System (Autostandard) are forced to Read-only mode for the user. These registers and bits are shaded in Table 9. Table 9: List of I²C Registers (Sheet 1 of 6) Name IC General Control CUT_ID RESET I2S_CTRL I2S_STAT I2S_SYNC_OFFSET Addr. Reset Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 00h 01h 04h 05h 06h (0000 0001) 0000 0000 0000 0000 (0000 0000) 0000 0000 0 BUS_EXP SYNC_OFF 0 0 I²S_OUTPUT SYNC_SIGN 0 0 0 0 EN_STBY CUT_NUMBER[5:0] 0 SOFT_ LRST2 LOCK_MODE 0 SOFT_ LRST1 SOFT_RST LOCK_TH[1:0] 0 0 I2S_SFO[7:0] SYNC_CST[1:0] LR_OFF LOCK_ FLAG Clocking 1 SYS_CONFIG FS1_DIV FS1_MD FS1_PE_H FS1_PE_L 07h 08h 09h 0Ah 0Bh 0000 0000 0001 0010 0001 0001 0011 0110 0000 0000 I2S_CH_NB[1:0] EN_PROG 0 0 0 0 PE_H1[7:0] PE_L1[7:0] NDIV1[1:0] INPUT_FREQ[3:0] 0 MD1[4:0] INPUT_CONFIG[1:0] SDIV1[2:0] Demodulator DEMOD_CTRL DEMOD_STAT AGC_CTRL AGC_GAIN DC_ERR_IF 0Ch 0Dh 0Eh 0Fh 10h 0000 0110 (0000 0000) 0001 0001 (0000 0000) (0000 0000) 0 0 AGC_ CMD 0 0 0 0 FAR_MODE GAP_MODE 0 0 QPSK_LK AM_SEL FM2_CAR AGC_REF[2:0] AGC_ERR[4:0] DC_ERR[7:0] FM2_SQ DEMOD_MODE[2:0] FM1_CAR FM1_SQ AGC_CST[1:0] SIG_OVER SIG_ UNDER Demodulator Channel 1 CARFQ1H CARFQ1M CARFQ1L FIR1C0 FIR1C1 FIR1C2 FIR1C3 FIR1C4 FIR1C5 FIR1C6 FIR1C7 ACOEFF1 BCOEFF1 CRF1 CETH1 12h 13h 14h 15h 16h 17h 18h 19h 1Ah 1Bh 1Ch 1Dh 1Eh 1Fh 20h 0011 1110 1000 0000 0000 0000 0000 0000 1111 1110 1111 1100 1111 1101 0000 0010 0000 1101 0001 1000 0001 1111 0010 0011 0001 0010 (0000 0000) 0010 0000 CARFQ1[23:16] CARFQ1[15:8] CARFQ1[7:0] FIR1C0[7:0] (S) FIR1C1[7:0] (S) FIR1C2[7:0] (S) FIR1C3[7:0] (S) FIR1C4[7:0] (S) FIR1C5[7:0] (S) FIR1C6[7:0]6 (S) FIR1C7[7:0] (S) ACOEFF1[7:0] BCOEFF1[7:0] CRF1[7:0] (S) CETH1[7:0] 56/156 STV82x7 Table 9: List of I²C Registers (Sheet 2 of 6) Name SQTH1 CAROFFSET1 Register List Addr. 21h 22h Reset 0011 1100 0000 0000 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 SQTH1[7:0] CAROFFSET1[7:0] (S) Demodulator Channel 2 IAGCR IAGCC IAGCS CARFQ2H CARFQ2M CARFQ2L FIR2C0 FIR2C1 FIR2C2 FIR2C3 FIR2C4 FIR2C5 FIR2C6 FIR2C7 ACOEFF2 BCOEFF2 SCOEFF SRF CRF2 CAROFFSET2 25h 26h 27h 28h 29h 2Ah 2Bh 2Ch 2Dh 2Eh 2Fh 30h 31h 32h 33h 34h 35h 36h 37h 3Ah 1000 1000 0000 0011 (0000 0000) 0100 0100 0100 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 1111 1111 0000 0100 0001 0100 0010 0101 1001 0000 1010 1100 0001 1100 (0000 0000) (0000 0000) 0000 0000 IAGC_ OFF FAR_FLT_EN MONO_FLT _EN IAGC_REF[7:0] BG_SEL MONO_PRO G IAGC_CST[2:0] IAGC_CTRL[7:0] CARFQ2[23:16] CARFQ2[15.8] CARFQ2[7:0] FIR2C0[7:0] (S) FIR2C1[7:0] (S) FIR2C2[7:0] (S) FIR2C3[7:0] (S) FIR2C4[7:0] (S) FIR2C5[7:0] (S) FIR2C6[7:0] (S) FIR2C7[7:0] (S) ACOEFF2[7:0] BCOEFF2[7:0] SCOEFF[7:0] SRF[7:0] (S) CRF2[7:0] (S) CAROFFSET2[7:0] (S) NICAM NICAM_CTRL NICAM_BER NICAM_STAT 3Dh 3Eh 3Fh 0000 0000 (0000 0000) (0000 0000) NIC_DET F_MUTE LOA 0 0 0 0 0 ERROR[7:0] CBI[3:0] NIC_MUTE DIF_POL ECT MAE Stereo FM ZWT_CTRL ZWT_TIME ZWT_STAT 40h 41h 42h 0011 0001 0000 0100 (0000 0000) LRST_ TONE_OFF 0 0 STD_MODE 0 0 0 0 0 0 THRESH[3:0] 0 ZW_STAT_ RDY ZW_DET TSCTRL[1:0] ZWT_TIME[2:0] ZW_ST ZW_DM Analog Control ADC_CTRL SCART1_2_OUTPUT_CTRL SCART3_OUTPUT_CTRL 56h 57h 58h 0000 1000 1010 1000 0000 1011 I2S_DATA0_CTRL[1:0] SC2_MUTE 0 0 0 0 ADC_ POWER_UP SC1_MUTE 0 SC3_MUTE ADC_INPUT_SEL[2:0] SC1_OUTPUT_SEL[2:0] SC3_OUTPUT_SEL[2:0] SC2_OUTPUT_SEL[2:0] 0 Clocking 2 FS2_DIV 5Ah 0001 0001 0 NDIV2[1:0] 0 SDIV2[2:0] 57/156 Register List Table 9: List of I²C Registers (Sheet 3 of 6) Name FS2_MD FS2_PE_H FS2_PE_L STV82x7 Addr. 5Bh 5Ch 5Dh Reset 0001 0001 0101 1100 0010 1001 Bit 7 0 Bit 6 0 Bit 5 0 Bit 4 Bit 3 Bit 2 MD2[4:0] Bit 1 Bit 0 PE_H2[7:0] PE_L2[7:0] DSP Control HOST_CMD 80h 0000 0000 IT_IN_DSP 0 0 0 0 IRQ3 (HP/Srnd unmute ready) HW_RESET 0 0 IRQ_STATUS 81h 0000 0000 0 0 0 0 IRQ2 IRQ1 (HP detected) (I2S sync lost) IRQ0 (autostd) SOFT_VERSION ONCHIP_ALGOS DSP_STATUS DSP_RUN 82h 83h 84h 85h (0000 0002) (0000 0000) 0000 0000 0000 0000 0 0 0 LOCK_ MODE_EN PRO_LOGIC _SELECT 0 0 NICAM 0 0 SOFT_VERSION[7:0] I2S_INPUT 0 0 LRCLK_STA RT TRUBASS 0 0 LRCLK_ POLARITY TRU SURROUND 0 0 SCLK_ POLARITY PRO_LOGIC 0 HOST_ NO_INIT DATA_CFG MULTICHANE L INIT_MEM HOST_RUN I2S_IN_CONFIG AV_DELAY 86h 89h 1000 1110 0000 0000 0 SYNC I2S_MODE DELAY_ON DELAY_TIME[6:0] Automatic Standard Recognition System AUTOSTD_CTRL 8Ah 0000 0001 0 0 NICAM_ C4_OFF LDK_ZWT2 0 NICAM_GA P_MODE LDK_SWT1 FORCE_ SQUELCH NICAM_ MONO_IN LDK_ NICAM SINGLE_ SHOT LDK_SCK DK_DEV[1:0] LDK_SW AUTOSTD_STANDARD_DETECT 8Bh 0010 1111 0 I_SCK BG_SCK MN_SCK AUTOSTD_STEREO_DETECT AUTOSTD_TIMERS AUTOSTD_STATUS 8Ch 8Dh 8Eh 0001 1111 1010 0100 (0000 0000) LDK_ZWT3 I_NICAM BG_ZWT BG_NICAM ZWEITON_TIME[2:0] MN_ZWT FM_TIME[1:0] STEREO_ ID STEREO_ OK MONO_ OK NICAM_TIME[2:0] AUTOSTD_O N STEREO_SID[1:0] MONO_SID[1:0] Audio Preprocessing & Selection DC_REMOVAL_INPUT DC_REMOVAL_L DC_REMOVAL_R PRESCALE_SELECT PRESCALE_AM PRESCALE_FM PRESCALE_NICAM PRESCALE_SCART PRESCALE_I2S_0 PRESCALE_I2S_1 PRESCALE_I2S_2 90h 91h 92h 93h 94h 95h 96h 97h 98h 99h 9Ah 0000 0111 (0000 0000) (0000 0000) 0000 0000 0000 0000 0000 1100 0001 1010 0000 0000 0000 0000 0000 0000 0000 0000 0 0 0 0 0 0 0 0 0 0 0 0 NICAM_ DEMATRIX NICAM_ DEEMPH_ BYPASS 0 0 0 0 0 0 0 DC_SCART DC_NICAM DC_ DEMOD DC_REMOVAL_L[7:0] (S) DC_REMOVAL_R[7:0] (S) 0 0 PRESCALE_AM[6:0] (S) PRESCALE_FM[6:0] (S) PRESCALE_NICAM[6:0] (S) PRESCALE_SCART[5:0] (S) PRESCALE_I2S_0[5:0] (S) PRESCALE_I2S_1[5:0] (S) PRESCALE_I2S_2[5:0] (S) FM_DEEMPH FM_DEEMPH _BYPASS _SW 0 0 AM_FM_ SELECT DEEMPHASIS_DEMATRIX 9Bh 0000 0000 0 0 FM_DEMATRIX[1:0] PEAK_DET_INPUT 9Dh 0000 0000 PEAK_ LOCATION 0 PEAK_L_R_RANGE PEAK_DET_INPUT[1:0] 58/156 STV82x7 Table 9: List of I²C Registers (Sheet 4 of 6) Name PEAK_DET_L Register List Addr. 9Eh Reset 0(0000 0000) 0(0000 0000) 0(0000 0000) Bit 7 OVERLOAD_L [7:0] OVERLOAD_ R[7:0] OVERLOAD_L _R[7:0] Bit 6 Bit 5 Bit 4 Bit 3 PEAK_L[6:0] Bit 2 Bit 1 Bit 0 PEAK_DET_R 9Fh PEAK_R[6:0] PEAK_DET_L_R A0h PEAK_L_R[6:0 Matrixing AUDIO_MATRIX_INPUT A2h 0000 0000 0 0 0 0 0 SCART_ INPUT_ SOURCE HP_INPUT_ SOURCE LS_INPUT_ SOURCE AUDIO_MATRIX_CONFIG A3h 0000 0000 0 MUTE_ STEREO 0 0 0 0 0 MUTE_ ALL 0 0 SCART_ MATRIX DEMOD_MATRIX[3:0] AUDIO_MATRIX_LANGUAGE DOWNMIX_IN_MODE DOWNMIX_OUT_MODE DOWNMIX_DUAL_MODE DOWNMIX_CONFIG A4h A6h A7h A8h A9h 0000 0000 0000 0010 0100 1010 0000 0000 0000 0001 SCART_LANGUAGE[1:0] 0 0 HP_LANGUAGE[1:0] LFE_IN LS_LANGUAGE[1:0] MIX_IN_MODE[2:0] MIX_OUT_MODE[2:0] HP_DUAL_SELECT[1:0] LR_UPMIX NORMALIZE HP_MODE[1:0] DUAL_ON 0 SCART_MODE[1:0] LS_DUAL_SELECT[1:0] SRND_FACTOR[1:0] SCART_DUAL_SELECT [1:0] CENTER_FACTOR[1:0] Audio Processing PRO_LOGIC2_CONTROL PCM_SRND_DELAY PCM_CENTER_DELAY PRO_LOGIC2_CONFIG PRO_LOGIC2_DIMENSION PRO_LOGIC2_LEVEL NOISE_GENERATOR AAh ABh ACh ADh AEh AFh B0h 0011 1010 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 10_DB_ ATTENUATE SRIGHT_ NOISE TRUSRND_ MONO_ SRND SLEFT_ NOISE PL2_LFE 0 0 0 0 PL2_OUTPUT_DOWNMIX[2:0] 0 0 0 0 0 0 PL2_C_WIDTH 0 PL2_SRND_FILTER 0 PL2_LEVEL SUB_ NOISE CENTER_ NOISE RIGHT_ NOISE LEFT_ NOISE TRUSRND_ MODE NOISE_ON PL2_MODES[2:0] SNRD_DELAY[4:0] CENTER_DELAY[3:0] PL2_RS_ POLARITY PL2_ PANORAMA PL2_DIMENSION PL2_AUTO BALANCE PL2_ACTIVE TRUSRND_CONTROL B1h 0000 0000 0 TRUSRND_INPUT_MODE[3:0] TRUSRND_ ON TRUSRND_INPUT_GAIN TRUSRND_HP_DCL TRUSRND_DC_ELEVATION TRUBASS_LS_CONTROL TRUBASS_LS_LEVEL TRUBASS_HP_CONTROL TRUBASS_HP_LEVEL SVC_LS_CONTROL SVC_LS_TIME_TH SVC_HP_CONTROL SVC_HP_TIME_TH B6h B7h B8h BAh BBh BCh BDh BEh BFh C0h C1h 0000 0000 0000 0000 0000 1100 0000 0110 00001 1001 0000 0110 0000 1001 0000 0010 1001 1000 0000 0010 1001 1000 0 0 0 SVC_LS_TIME[2:0] 0 SVC_HP_TIME[2:0] 0 0 0 0 0 0 0 0 0 0 0 TRUSRND_INPUT_GAIN[7:0] 0 0 DIALOG_ HEADPHONE CLARITY_ON _ON 0 TRUSRND_DC_ELEVATION[7:0] TRUBASS_LS_SIZE[3:0] TRUBASS_LS_LEVEL[7:0] TRUBASS_HP_SIZE[3:0] TRUBASS_HP_LEVEL[7:0] 0 SVC_LS_INPUT[1:0] SVC_ LS_AMP SVC_ LS_ON TRUBASS_ HP_ON TRUBASS_ LS_ON SVC_LS_THRESHOLD[4:0] (S) 0 0 0 SVC_ LHP_AMP SVC_ HP_ON SVC_HP_THRESHOLD[4:0] (S) 59/156 Register List Table 9: List of I²C Registers (Sheet 5 of 6) Name SVC_LS_GAIN SVC_HP_GAIN STSRND_CONTROL STSRND_FREQ STSRND_LEVEL OMNISURROUND_CONTROL STV82x7 Addr. C2h C3h C4h C5h C6h C7h Reset 0000 0000 0000 0000 0000 0000 0001 0101 1000 0000 0000 0000 Bit 7 0 0 Bit 6 0 0 Bit 5 0 0 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 SVC_LS_MAKE_UP_GAIN[4:0] SVC_HP_MAKE_UP_GAIN[4:0] STSRND_ STEREO STSRND_ MODE STSRND_ ON 0 0 STSRND_BASS[1:0] STSRND_MEDIUM[1:0] STSRND_TREBLE[1:0] STSRND_GAIN[7:0] ST_VOICE OMNISRND_INPUT_MODE OMNISRND_ ON DYN_BASS_ ON LS_EQ_ON ST_DYNAMIC_BASS C8h 0000 0000 BASS_LEVEL BASS_FREQ LS_EQ_BT_ SW LS_EQ_BT_CTRL LS_EQ_BAND1 LS_EQ_BAND2 LS_EQ_BAND3 LS_EQ_BAND4 LS_EQ_BAND5 LS_BASS_GAIN LS_TREBLE_GAIN HP_BT_CONTROL HP_BASS_GAIN HP_TREBLE_GAIN OUTPUT_BASS_MNGT C9h CAh CBh CCh CDh CEh CFh D0h D1h D2h D3h D4h 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0 0 0 0 0 0 EQ_BAND1[7:0] (S) EQ_BAND2[7:0] (S) EQ_BAND3[7:0] (S) EQ_BAND4[7:0] (S) EQ_BAND5[7:0] (S) LS_BASS[7:0] (S) LS_TREBLE[7:0] (S) 0 0 0 0 0 0 0 HP_BT_ON HP_BASS[7:0] (S) HP_TREBLE[7:0] (S) BASS_ MANAGE_ON 0 0 SUB_ ACTIVE GAIN_ SWITCH 0 OCFG_NUM[2:0] LS_ LOUD_ON HP_ LOUD_ON LS_LOUDNESS D5h 0000 0100 LS_LOUD_THRESHOLD[2:0] LS_LOUD_GAIN_HR[2:0] HP_LOUDNESS D6h 0000 0100 0 HP_LOUD_THRESHOLD[2:0] HP_LOUD_GAIN_HR[2:0] Volume VOLUME_MODES D7h 1100 0111 ANTCLIP_HP _VOL_CLAMP ANTICLIP_ LS_VOL_ CLAMP 0 0 SCART_ VOLUME_ MODE SRND_ VOLUME_ MODE HP_ VOLUME_ MODE LS_ VOLUME_ MODE LS_L_VOLUME_MSB LS_L_VOLUME_LSB LS_R_VOLUME_MSB LS_R_VOLUME_LSB LS_C_VOLUME_MSB LS_C_VOLUME_LSB LS_SUB_VOLUME_MSB LS_SUB_VOLUME_LSB LS_SL_VOLUME_MSB LS_SL_VOLUME_LSB LS_SR_VOLUME_MSB LS_SR_VOLUME_LSB D8h D9h DAh DBh DCh DDh DEh DFh E0h E1h E2h E3h 1001 1000 0000 0000 0000 0000 0000 0000 1001 1000 0000 0000 1001 1000 0000 0000 1001 1000 0000 0000 0000 0000 0000 0000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LS_L_VOLUME_MSB[7:0] 0 0 0 LS_L_VOLUME_LSB[1:0] LS_R_VOLUME_MSB[7:0] 0 0 0 LS_R_VOLUME_LSB[1:0] LS_C_VOLUME_MSB[7:0] 0 0 0 LS_C_VOLUME_LSB[1:0] LS_SUB_VOLUME_MSB[7:0] 0 0 0 LS_SUB_VOLUME_LSB[1:0] LS_SL_VOLUME_MSB[7:0] 0 0 0 LS_SL_VOLUME_LSB[1:0] LS_SR_VOLUME_MSB[7:0] 0 0 0 LS_SR_VOLUME_LSB[1:0] 60/156 STV82x7 Table 9: List of I²C Registers (Sheet 6 of 6) Name LS_MASTER_VOLUME_MSB LS_MASTER_VOLUME_LSB HP_L_VOLUME_MSB HP_L_VOLUME_LSB HP_R_VOLUME_MSB HP_R_VOLUME_LSB SCART_L_VOLUME_MSB SCART_L_VOLUME_LSB SCART_R_VOLUME_MSB SCART_R_VOLUME_LSB Register List Addr. E4h E5h E6h E7h E8h E9h EAh EBh ECh EDh Reset 1110 1000 0000 0000 1001 1000 0000 0000 0000 0000 0000 0000 1101 1101 0000 0000 1101 1101 0000 0000 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 LS_MASTER_VOLUME_MSB[7:0] 0 0 0 0 0 0 LS_MASTER_VOLUME_ LSB[1:0] HP_L_VOLUME_MSB[7:0] 0 0 0 0 0 0 HP_L_VOLUME_LSB[1:0] HP_R_VOLUME_MSB[7:0] 0 0 0 0 0 0 HP_R_VOLUME_ LSB[1:0] SCART_L_VOLUME_MSB[7:0] 0 0 0 0 0 0 SCART_L_VOLUME_ LSB[1:0] SCART_R_VOLUME_MSB[7:0] 0 0 0 0 0 0 SCART_R_VOLUME_ LSB[1:0] Beeper BEEPER_ON EEh 0000 0000 0 0 0 0 0 0 BEEPER_ PULSE 0 BEEPER_ ON BEEPER_MODE BEEPER_FREQ_VOL EFh F0h 0000 0011 0111 0000 0 0 BEEPER_FREQ[2:0] 0 BEEPER_DURATION[1:0] BEEPER_PATH[1:0] BEEPER_VOLUME[4:0] Mute MUTE_DIGITAL F1h 1001 1111 AUTOSTD_ MUTE_ON 0 0 SCART_ D_MUTE SRND_HP_ D_MUTE SUB_ D_MUTE C_ D_MUTE LS_ D_MUTE S/PDIF S/PDIF_OUT_CONFIG F2h 0000 0100 0 0 0 0 0 SPDIF_OUT_ MUTE S/PDIF_OUT_SELECT[2:0] Headphone Configuration HEADPHONE_CONFIG F3h 0000 001(0) 0 0 0 0 HP_FORCE HP_LS_ MUTE HP_DET_ ACTIVE HP_ DETECTED DAC Control DAC_CONTROL DAC_SW_CHANNELS SPDIF_SW_CHANNELS SPDIF_CHANNEL_STATUS F4h F5h F6h F9h 0001 1111 0000 0000 0000 0000 0000 0000 0 SUR_HP_SW 0 0 0 0 S/PDIF_ MUX DAC_SCART _MUTE DAC_SHP_ MUTE DAC_CSUB_ MUTE DAC_LSLR_ MUTE POWER_ UP C_SUB_SW 0 EMPHASIS 0 LS_L_R_SW 0 COPYRIGHT SCART_SW SPFI_SW NON_AUDIO PRO_CON CHANNEL_STATUS AutoStandard Coefficients Settings AUTOSTD_COEFF_CTRL FBh 0000 0001 0 0 0 0 0 0 AUTOSTD_COEFF_ CTRL[1:0] AUTOSTD_ COEFF_ INDEX_MSB AUTOSTD_COEFF_INDEX_MSB FCh 0000 0000 0 0 0 0 0 0 0 AUTOSTD_COEFF_INDEX_LSB AUTOSTD_COEFF_VALUE PATCH_VERSION FDh FEh FFh 0000 0000 0000 0000 0000 0000 AUTOSTD_COEFF_INDEX_LSB[7:0] AUTOSTD_COEFF_VALUE[7:0] PATCH_VERSION[7:0] 61/156 Register List STV82x7 12.2 STV82x7 General Control Registers CUT_ID Version Identification Address: 00h Type: R Bit 7 0 Bit 6 0 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 CUT_NUMBER[5:0] Bit Name Bits[7:6] CUT_NUMBER[5:0] Reset 00 Reserved Function 000001 Dice Version Identification RESET Address: 01h Type: R/W Bit 7 BUS_EXP Bit 6 I²S_OUTPUT Bit 5 0 Software Reset Register Bit 4 EN_STBY Bit 3 0 Bit 2 Bit 1 Bit 0 SOFT_RST SOFT_LRST2 SOFT_LRST1 Description The built-in Automatic Standard Recognition System (Autostandard) can be disabled. In this case, the Software Reset function (bits SOFT_LRST1 and SOFT_LRST2) can be used to implement the Automatic Standard Recognition by I²C Software. This is not required if the built-in Automatic Standard Recognition System function is used (default). Bit Name BUS_EXP I²S_OUTPUT Reset 0 0 Function Static control by I2C of hardware pin BUS_EXP 0: I²S Input (I2S_DATA0 , I2S_SCLK, I2S_LR_CLK, I2S_PCM_CLK in input mode) 1: I²S Output (I2S_DATA0 , I2S_SCLK, I2S_LR_CLK, I2S_PCM_CLK in output mode, 512 x Fs will be provided on the I2S_PCM_CLK pin) Reserved. Standby mode enabling 0: Normal mode 1: To lock the digital signals before to settle the device in standby mode Bit[5] EN_STBY 0 0 Bit 3 SOFT_LRST2 SOFT_LRST1 SOFTR_RST 0 0 0 0 Reserved. Softreset (active high) of Channel 2 detectors only. Softreset (active high) of Channel 1 detectors only. General softreset (active high) to reset all hardware registers except for I²C data. 62/156 STV82x7 I2S_CTRL Address: 04h Type: R/W Bit 7 SYNC_OFF Bit 6 SYNC_SIGN Bit 5 0 Bit 4 Bit 3 Bit 2 LOCK_MODE Bit 1 Register List I2S Synchronization Control Register Bit 0 LOCK_TH[1:0] SYNC_CST[1:0] Bit Name SYNC_OFF SYNC_SIGN Bit 5 0 0 0 Reset Function Open the loop of synchronization - External PCM clock is used internally and must be equal to 512 x fSOUT Sign of the loop reversion (to be used in case of gain inversion of the Frequency Synthesizer) Reserved Lock Detector Threshold Programming LOCK_TH[ 1:0] 00 00: ±1 CLK period error of accumulation 01: ±2 CLK period error of accumulation 10: ±4 CLK period error of accumulation 11: ±8 CLK period error of accumulation Lock Detector Mode LOCK_MOD E 0 0: Lock when accumulation error within lock threshold and LR detected (period counter not saturated) 1: Lock when only accumulation error within lock threshold. Don’t care about the LR detection Synchronization Time Constant Defines the measurement period of LR SYNC_CST[ 1:0] 01 00: Half period measured (lowest accuracy) 01: One full period measured 10: Two full periods measured 11: Four full periods measured (highest accuracy) I2S_STAT Address: 05h Type: R/W Bit 7 0 Bit 6 0 Bit 5 0 I²S Synchronization Status Register Bit 4 0 Bit 3 0 Bit 2 0 Bit 1 LR_OFF Bit 0 LOCK_FLAG Bit Name Bits[7:2] LR_OFF Reset 0 0 Reserved. LR Signal Detection 0: LR signal detected and correct 1: Missing LR pulses detected Function LOCK_FLAG 0 Lock Flag allowing unmute of Audio Output 63/156 Register List I2S_SYNC_OFFSET Address: 06h Type: R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 STV82x7 I²S Synchronization Offset Frequency Register Bit 0 I2S_SFO[7:0] Bit Name I2S_SFO[7:0] Reset 0000 0000 Function I²S synchronization frequency offset (±450 ppm full scale) 12.3 Clocking 1 A low-jitter PLL Clock is integrated and can be fully reprogrammed using the registers described below. By default, the programming is defined for a 27-MHz quartz crystal frequency, which is the frequency recommended for reducing potential RF interference in the application. However, if necessary, the PLL Clock can be re-programmed for other quartz crystal frequencies within a range from 23 to 30 MHz. Other quartz crystal frequencies can be programmed on your demand. Note: A Crystal Frequency change is compatible with other default I²C programming including the built-in Automatic Standard Recognition System. SYS_CONFIG Address: 07h Type: R/W Bit 7 Bit 6 Bit 5 System Configuration Control Register Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 I2S_CH_NB[1:0] INPUT_FREQ[3:0] INPUT_CONFIG[1:0] Bit Name I2S_CH_NB[1:0] Reset 00 Number of I2S channels input 00: N/A 01: 2 channels 10: 4 channels 11: 6 channels Function INPUT_FREQ[3:0] 0000 I2S Input frequency 0000 : 32 kHz 0001: 44.1 kHz 0010: 48 kHz 0011: 8 kHz (I2S input, 2 channels only) 0100 : 11.025 kHz (I2S input, 2 channels only) 0101 : 12 kHz (I2S input, 2 channels only) 0110 : 16 kHz (I2S input, 2 channels only) 0111 : 22.05 kHz (I2S input, 2 channels only) 1000 : 24 kHz (I2S input, 2 channels only) 64/156 STV82x7 Register List Bit Name INPUT_CONFIG[1:0] Reset 0 Input stream to process 0 : SIF & SCART input (32 kHz) 1 : SCART input only (48 kHz) 2 : I2S input only Function FS1_DIV Address: 08h Type: R/W Bit 7 EN_PROG Bit 6 0 Bit 5 NDIV1[1:0] FS1 I/O Divider Programming Register Bit 4 Bit 3 0 Bit 2 Bit 1 SDIV1[2:0] Bit 0 Bit Name EN_PROG Reset 0 FS1 programmation enable Function 0: FS1 I2C registers programmation ignored by system - FS1 pre-programmed automatically by SYS-CONFIG register (normal use with standard quartz of 27 MHz) 1: FS1 I2C registers programmation used by system - FS1 pre-programmation by SYS-CONFIG desactivated (to be used in case of no standard quartz, different from 27 MHz) Bit 6 NDIV1[1:0] Bit 3 SDIV1[2:0] 0 01 0 010 Reserved. FS1 Input clock divider selection Reserved. FS1 Output clock divider selection FS1_MD Address: 09h Type: R/W Bit 7 0 Bit 6 0 Bit 5 0 FS1 Coarse Selection Register Bit 4 Bit 3 Bit 2 MD1[4:0] Bit 1 Bit 0 Bit Name Bits[7:5] MD1[4:0] Reset 000 10001 Reserved. FS1 Coarse Selection Function 65/156 Register List FS1_PE_H Address: 0Ah Type: R/W Bit 7 Bit 6 Bit 5 Bit 4 PE_H1[7:0] Bit 3 Bit 2 Bit 1 STV82x7 FS1 Fine Selection Register (MSBs) Bit 0 Bit Name PE_H1[7:0] Reset 0011 0110 FS1 Fine Selection (MSBs) Function FS1_PE_L Address: 0Bh Type: R/W Bit 7 Bit 6 Bit 5 FS1 Fine Selection Register (LSBs) Bit 4 PE_L1[7:0] Bit 3 Bit 2 Bit 1 Bit 0 Bit Name PE_L1[7:0] Reset 0000 0000 FS1 Fine Selection (LSBs) Function 12.4 Demodulator DEMOD_CTRL Demodulator Control Register Address: 0Ch Type: R/W Bit 7 0 Bit 6 0 Bit 5 FAR_MODE Bit 4 GAP_MODE Bit 3 AM_SEL Bit 2 Bit 1 DEMOD_MODE[2:0] Bit 0 Bit Name bit [7:6] FAR_MODE GAP_MODE Reset 000 0 0 Reserved 1: Farrow and Mono filter for NICAM active Function Defines the clock gapping mode of the demodulator 0: (default), the FS1 freq is controlled by stl-error (clock-pll mode) to align the instantaneous value of the internal clock with respect to the received NICAM clock 1: the FS1 freq is fixed and the mean value of the internal clock is aligned by variable gapping (src-error) with respect to the received NICAM clock 66/156 STV82x7 Register List Bit Name AM_SEL Reset 0 Demodulator Configuration Select Function 0: FM configuration of demodulator (Default) 1: AM configuration of demodulator DEMOD_MODE[2:0] 110 Demodulator Mode Select CH1 FM 000: 001: 010: 011: 100: 101: 110: 111: Normal Wide Normal Wide Normal Wide Normal Wide CH2 FM/QPSK FM Normal FM Wide QPSK System QPSK System FM Wide FM Normal QPSK System QPSK System B/G/L/D/K B/G/L/D/K I I DEMOD_STAT Address: 0Dh Type: R Bit 7 0 Bit 6 0 Bit 5 0 Demodulator Detection Status Register Bit 4 QPSK_LK Bit 3 FM2_CAR Bit 2 FM2_SQ Bit 1 FM1_CAR Bit 0 FM1_SQ Bit Name Bit [7:5] QPSK_LK Reset 000 0 Reserved. QPSK Lock Detection Flag 0: Not detected 1: Detected Function FM2_CAR 0 Channel 2 FM/AM Carrier Detection Flag 0: Not detected 1: Detected FM2_SQ 0 Channel 2 FM Squelch Detection Flag 0: Not detected 1: Detected FM1_CAR 0 Channel 1 FM/AM Carrier Detection Flag 0: Not detected 1: Detected FM1_SQ 0 Channel 1 FM Squelch Detection Flag 0: Not detected 1: Detected Note: These registers allow direct access to the demodulator signal detectors. 67/156 Register List AGC_CTRL Address: 0Eh Type: R/W Bit 7 AGC_CMD Bit 6 0 Bit 5 0 Bit 4 Bit 3 AGC_REF[2:0] Bit 2 Bit 1 STV82x7 IF AGC Control Register Bit 0 AGC_CST[1:0] Bit Name AGC_CMD Reset 0 Automatic Gain Control Command Mode Function Normally set to 0 enabling automatic mode. For L/L’ standards, the AGC should be switched off due to the presence of the AM sound carrier. In this case, a fixed gain value should be set using the AGCS register. 0: Automatic mode. AGC controlled by the Autostandard function. (Default) 1: Manual/Forced mode Bits[6:5] AGC_REF[2:0] 00 100 Reserved. This bitfield is used to defines the clipping level which adjusts the allowable proportion of samples at the input of the ADC which will be clipped. The AGC tries to maximize the use of the full scale range of the ADC. The default setting gives a ratio of 1/256. Clipping Ratio 000: 001: 010: 011: AGC_CST[1:0] 01 1/16 (Single carrier) 1/32 1/64 1/128 100: 101: 110: 111: Clipping Ratio 1/256 (Default) 1/512 1/1024 1/2048 (Multiple carriers) AGC Time Constant This is the time constant between each step of 1.5 dB by the AGC. Step Duration (ms) 00 01 10 11 1.33 2.66 5.33 10.66 AGC_GAIN Address: 0Fh Type: R/W Bit 7 0 Bit 6 Bit 5 IF AGC Control and Status Register Bit 4 AGC_ERR[4:0] Bit 3 Bit 2 Bit 1 SIG_OVER Bit 0 SIG_UNDER Bit Name Bit 7 Reset 0 Reserved. Function 68/156 STV82x7 Register List Bit Name AGC_ERR[4:0] Reset 00000 Amplifier Gain Control Function This is the Gain Control value of AGC. There are 20 steps of +1.5 dB (see Note below). 00000: Gain-min 10100: Gain-min + 30 db 11111: Gain-min + 30 db SIG_OVER 0 AGC Input SIgnal Upper Threshold 0: Normal signal 1: Signal too large and AGC is overloaded SIG_UNDER 0 AGC Input SIgnal Lower Threshold 0: Normal signal 1: Signal too small and AGC is underloaded When the AGC is in Automatic mode (AGC_CMD = 0), bits SIG_OVER and SIG_UNDER indicate if the input signal is too small/large and the AGC is under/overloaded. This is useful when setting the STV82x7 SIF input level. Note: When AGC_CMD = 0, AGC_ERR[4:0] can be read -- indicating the input level. It can also be written to -- presetting the AGC level which will then adjust itself to the final value. When AGC_CMD = 1, the AGC is off and writing to AGC_ERR[4:0] directly controls the AGC amplifier gain. Reading AGC_ERR just confirms the fixed value. DC_ERR_IF Address: 10h Type: R Bit 7 Bit 6 Bit 5 DC Offset Status for IF ADC Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 DC_ERR[7:0] Bit Name DC_ERR[7:0] Reset 00000000 DC offset error of IF ADC output Function 12.5 Demodulator Channel 1 CARFQ1H, CARFQ1M, CARFQ1L Channel 1 Carrier DCO Frequency Address: 12h to 14h Type: R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 CARFQ1[23:16], CARFQ1[15:8], CARFQ1[7:0] 69/156 Register List STV82x7 Bit Name CARFQ1[23:16] CARFQ1[15:8] CARFQ1[7:0] Reset 00111110 10000000 00000000 Function Channel 1 DCO Carrier Frequency (8 MSBs) Channel 1 DCO Carrier Frequency Channel 1 DCO Carrier Frequency (8 LSBs), see Table 10. Table 10: Mono Carrier Frequencies by System System M/N B/G I L D/K/K1/K2 Mono Carrier Freq. (MHz) 4.5 5.5 6.0 6.5 6.5 CARFQ1[23:0] (dec) 3072000 3754667 4096000 4453717 4437333 CARFQ1[23:0] 2EE000h 394AABh 3E8000h 43F555h 43B555h Note: Carrier Freq: CARFQ1(dec).fS / 224 with fS = 24.576 MHz (crystal oscillator frequency independent) FIR1C[0:7] Address: 15h to 1Ch Type: R/W Bit 7 Bit 6 Bit 5 Channel 1 FIR Coefficients Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 FIR1C0[7:0] to FIR1C7[7:0] Table 11: Channel 1 FIR Coefficients Bitfield FM 27 kHz 1 FIR1C0[7:0] FIR1C1[7:0] FIR1C2[7:0] FIR1C3[7:0] FIR1C4[7:0] FIR1C5[7:0] FIR1C6[7:0] FIR1C7[7:0] FFh FEh FEh 00h 06h 0Eh 16h 1Bh FM 50 kHz2 00h FEh FCh FDh 02h 0Dh 18h 1Fh FM 75 kHz 01h 03h 02h FCh F8h 01h 18h 2Dh Description FM 100 kHz FFh 00h 05h 02h F8h F9h 15h 35h FM 200 kHz 00h 01h 01h FCh 08h F6h F8h 4Ah FM 350 kHz 02h 01h FCh 03h 04h F2h 06h 43h FM 500 kHz 01h 00h 04h FAh 05h 00h F2h 4Dh AM 00h FEh FDh FEh 04h 0Dh 16h 1Dh 1. Default mode for M/N standard. 2. Default mode for B/G/I/D/K standards 70/156 STV82x7 ACOEFF1 Register List Channel 1 Baseband PLL Loop Filter Proportional Coefficient Address: 1Dh Type: R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ACOEFF1[7:0] Bit Name ACOEFF1[7:0] Reset 00100011 Function Used to program the Proportional Coefficient of the baseband PLL loop filter (Channel 1) Defines the damping factor of the loop. For values, refer to Table 12. BCOEFF1 C h a n n e l 1 B a s e b a n d P L L L o o p F ilt e r In t e g ra l C o e f fic ie n t & D C O G a in Address: 1Eh Type: R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 BCOEFF1[7:0] Bit Name BCOEFF1[7:0] Reset 00010010 Function Used to program the Integral Coefficient of the baseband PLL loop filter and DCO gain Defines the bandwidth of the loop. For values, refer to Table 12. Table 12: Baseband PLL Loop Filter Adjustment (FM Mode) FM Mode ACOEFF BCOEFF FM_DEV max (kHz) DCO Range (kHz) Small 10h 1Ah 62.5 96 Standard 22h 12h 125 192 Medium 2Ch 0Ah 250 384 Wide1 2Ch 0Ah 500 768 A2 Standard 10h 11h 125 192 1. Refer to DEMOD_MODE[2:0] bits in the DEMOD_CTRL register. Note: 1 FM Pre-scale has to be adjusted depending on the chosen FM Mode. 2 FM squelch threshold has to be adjusted depending on the chosen FM Mode. 71/156 Register List CRF1 Address: 1Fh Type: R Bit 7 Bit 6 Bit 5 Bit 4 CRF1[7:0] Bit 3 Bit 2 Bit 1 STV82x7 Channel 1 Baseband PLL Demodulator Offset Bit 0 Bit Name CRF1[7:0] Reset (00000000) Channel 1 Carrier Recovery Frequency Function Displays the instantaneous frequency offset of the Channel 1 Baseband PLL Demodulator. CETH1 Address: 20h Type: R/W Bit 7 Bit 6 Bit 5 Channel 1 FM/AM Carrier Level Threshold Bit 4 CETH1[7:0] Bit 3 Bit 2 Bit 1 Bit 0 Bit Name CETH1[7:0] Reset 00100000 Function This register is used to compare the carrier level in the channel and the threshold value. This level is measured after the channel filter and is relative to the full scale reference level (0 dB). This is used as part of the validation of an FM signal, if the carrier level is below the threshold, the signal is considered to be non-valid. CETH FFh 80h 40h 20h Threshold (dB) -6 -12 -18 -24 (Default) CETH 10h 08h 00h Threshold (dB) -32 (Recommended Value) -38 OFF (all carrier levels are accepted) SQTH1 Address: 21h Type: R/W Bit 7 Bit 6 Bit 5 Channel 1 FM Squelch Threshold Register Bit 4 Bit 3 SQTH1[7:0] Bit 2 Bit 1 Bit 0 72/156 STV82x7 Register List Bit Name SQTH1[7:0] Reset 00111100 Function The Squelch Detector measures the level of high frequency noise (> 40 kHz) and compares it to the threshold level (SQTH). If the level is below this value, the S/N of the FM signal is considered to be acceptable. Values are given for FM with standard deviation. SQTH FAh 77h 3Ch 23h 19h S/N (dB) 0 10 15 (Default) 20 25 Note: FM squelch threshold has to be adjusted depending on the chosen FM Mode. CAROFFSET1 Address: 22h Type: R/W Bit 7 Bit 6 Bit 5 Channel 1 DCO Carrier Offset Compensation Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 CAROFFSET1[7:0] (S) Bit Name CAROFFSET1[7:0] Reset 00000000 Function This value is used to correct the carrier frequency offset of the incoming IF signal. Automatic frequency control in FM mode can be implemented by registers DC_REMOVAL_L and DC_REMOVAL_R. A DCO frequency offset (in two’s complement format) is added to the pre-programming value by AUTOTSD in the CARFQ1 registers (corresponding to the standard IF carrier frequency). The programmable carrier offset ranges from -192 kHz to +190.5 kHz with a resolution of 1.5 kHz. For standard FM deviation, the value displays by DC_REMOVAL_L and DC_REMOVAL_R can be directly loaded in CAROFFSET1 to exactly compensate the carrier offset on Channel 1. 12.6 Demodulator Channel 2 IAGCR Channel 2 Internal AGC Reference for QPSK Address: 25h Type: R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 IAGC_REF[7:0] Bit Name IAGC_REF[7:0] Reset 10001000 Function Sets the mean value of the internal AGC, used for QPSK demodulation. The default setting corresponds to half full scale amplitude at the baseband PLL input. 73/156 Register List IAGCC Address: 26h Type: R/W Bit 7 IAGC_OFF Bit 6 FAR_FLT_EN STV82x7 Channel 2 Internal AGC Time Constant for QPSK Bit 5 MONO_FLT_EN Bit 4 BG_SEL Bit 3 MONO_PROG Bit 2 Bit 1 IAGC_CST[2:0] Bit 0 Bit Name IAGC_OFF Reset 0 AGC Disable 0: Internal AGC is active 1: Internal AGC is disabled 1: Enable Farrow filter for NICAM 1: Enable Mono filter for NICAM 1: BG NICAM Mono filter selected 1: Enable programmation of Mono filter Function FAR_FLT_EN MONO_FLT_EN BG_SEL MONO_PROG IAGC_CST[2:0] 0 0 0 0 011 Internal AGC Programmable Step Constant. These bits control the time per step (values given for QPSK mode). The default value defines the optimum trade-off between fast settling time (for the fastest NICAM identification) and the noise immunity (minimum BER degradation) Step time (us) Time Response (ms) 000 001 010 011 100 101 110 111 703 352 176 88 44 22 11 5.5 128 64 32 16 8 4 2 0.82 IAGCS Address: 27h Type: R Bit 7 Bit 6 Bit 5 Channel 2 Internal AGC Status for QPSK Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 IAGC_CTRL[7:0] Bit Name IAGC_CTRL[7:0] Reset 00000000 Function Indicates the value of the internal AGC gain control 74/156 STV82x7 CARFQ2H, CARFQ2M, CARFQ2L Address: 28H to 2Ah Type: R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Register List Channel 2 Carrier DCO Frequency Bit 0 CARFQ2[23:16], CARFQ2[15.8], CARFQ2[7:0] Bit Name CARFQ2[23:16] CARFQ2[15.8] CARFQ2[7:0] Reset 01000100 01000000 00000000 Function Channel 2 DCO Carrier Frequency (8 MSBs) Channel 2 DCO Carrier Frequency Channel 2 DCO Carrier Frequency (8 LSBs) See Table 13. Table 13: Stereo Carrier Frequencies by System System M/N A2+ B/G NICAM BG A2 I NICAM L NICAM DK NICAM DK1 A2* DK2 A2* DK3 A2* Stereo Carrier Freq. (MHz) 4.724212 5.85 5.7421875 6.552 5.85 5.85 6.258125 6.7421875 5.7421875 CARFQ2[23:0] (Dec) 3225062 3993600 3920000 4472832 3993600 3993600 4272000 4602667 3920000 CARFQ2[23:0] 3135E6h 3CF000h 3BD080h 444000h 3CF000h 3CF000h 412F80h 463B2Bh 3BD080h FIR2C[0:7] Address: 2Bh to 32h Type: R/W Bit 7 Bit 6 Bit 5 Channel 2 FIR Coefficients Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 FIR2C0[7:0] to FIR2C7[7:0] Table 14: Channel 2 FIR Coefficients Description Bitfield FM 27 kHz FIR2C0[7:0] FIR2C1[7:0] FIR2C2[7:0] FFh FEh FEh FM 50 kHz 00h FEh FCh QPSK 40% 00h 00h FFh (reset state) QPSK100% 00h 00h 00h 75/156 Register List Table 14: Channel 2 FIR Coefficients Description Bitfield FM 27 kHz FIR2C3[7:0] FIR2C4[7:0] FIR2C5[7:0] FIR2C6[7:0] FIR2C7[7:0] 00h 06h 0Eh 16h 1Bh FM 50 kHz FDh 02h 0Dh 18h 1Fh QPSK 40% 03h 00h F4h 0Ah 3Dh (reset state) QPSK100% 00h FFh 04h 14h 25h STV82x7 ACOEFF2 Channel 2 Baseband PLL Loop Filter Proportional Coefficient Address: 33h Type: R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ACOEFF2[7:0] Bit Name ACOEFF2[7:0] Reset 10010000 Function This value defines the loop clamping factor used to program the Proportional Coefficient of the baseband PLL loop filter (Channel 2). See Table 15 and Table 16. BCOEFF2 Channel 2 Baseband PLL Loop Filter Integral Coefficient & DCO Gain Address: 34h Type: R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 BCOEFF2[7:0] Bit Name BCOEFF2[7:0] Reset 10101100 Function This value defines the loop bandwidth used to program the Integral Coefficient of the Baseband PLL loop filter and DCO gain. See Table 15 and Table 16. Table 15: Baseband PLL Loop Filter Adjustments (FM Mode) FM mode ACOEFF BCOEFF Small 10h 1Ah Standard 22h 12h Mid 2Ch 0Ah Wide 2Ch 0Ah A2 standard 10h 11h 76/156 STV82x7 Table 15: Baseband PLL Loop Filter Adjustments (FM Mode) FM mode FM_DEV max (kHz) DCO Range (kHz) Register List Small 62.5 96 Standard 125 192 Mid 250 384 Wide 500 768 A2 standard 125 192 Table 16: Baseband PLL Loop Filter Adjustments (QPSK Mode) QPSK mode ACOEFF BCOEFF DCO_DEV max (kHz) Small 90h ACh 2.84375 Medium 90h A3h 5.6875 Large 90h 9Ah 11.375 Extra-large 90h 91h 22.75 SCOEFF Address: 35h Type: R/W Bit 7 Bit 6 Bit 5 Channel 2 Symbol Tracking Loop Coefficients Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 SCOEFF[7:0] Bit Name SCOEFF[7:0] Reset 00011100 Function This value is used to program the proportional and integral coefficients of the QPSK Symbol tracking loop. See Table 17 and Table 18. Table 17: QPSK System - BG/L/DK Standards (40% Roll-off) Extra-Small SCOEFF 1Eh Small 25h Medium 24h Large 26h Extra-Large 2Ah Open Loop 80h Table 18: QPSK System - I Standard (100% Roll-off) Extra-Small SCOEFF 16h Small 1Dh Medium 1Ch Large 23h Extra-Large 22h SRF Address: 36h Type: R/W Bit 7 Bit 6 Bit 5 Channel 2 Symbol Tracking Loop Frequency Bit 4 SRF[7:0] Bit 3 Bit 2 Bit 1 Bit 0 77/156 Register List STV82x7 Bit Name SRF[7:0] Reset 00000000 Function Displays in two’s complement format the frequency deviation between the incoming NICAM bitstream and the quartz clocks. The maximum error is ±250 ppm. CRF2 Address: 37h Type: R Bit 7 Bit 6 Bit 5 Channel 2 Baseband PLL Demodulator Offset Bit 4 CRF2[7:0] Bit 3 Bit 2 Bit 1 Bit 0 Bit Name CRF2[7:0] Reset 00000000 Function Channel 2 Carrier Recovery Frequency. Displays the instantaneous frequency offset of the Channel 2 Baseband PLL CAROFFSET2 Address: 3Ah Type: R/W Bit 7 Bit 6 Bit 5 Channel 2 DCO Carrier Offset Compensation Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 CAROFFSET2[7:0] (S) Bit Name Reset Function This value is used to correct the carrier frequency offset of the incoming IF signal. Automatic frequency control in FM mode can be implemented by registers DC_REMOVAL_L and DC_REMOVAL_R. A DCO frequency offset (in two’s complement format) is added to the pre-programming value by AUTOTSD in the CARFQ2 registers (corresponding to the standard IF carrier frequency). The programmable carrier offset ranges from -192 kHz to +190.5 kHz with a resolution of 1.5 kHz. For standard FM deviation, the value displayed by register DC_REMOVAL_R can be directly loaded in register CAROFFSET2 to exactly compensate the carrier offset on Channel 2. CAROFFSET2[7:0] 00000000 12.7 NICAM Registers NICAM_CTRL NICAM Decoder Control Register Address: 3Dh Type: R/W Bit 7 0 Bit 6 0 Bit 5 0 Bit 4 0 Bit 3 0 Bit 2 DIF_POL Bit 1 ECT Bit 0 MAE 78/156 STV82x7 Register List Bit Name Bits[7:3] DIF_POL ECT Reset 00000 0 0 Reserved. Function 0: No polarity inversion (Default) 1: Polarity inversion of the differential decoding Error Counter Timer: Defines the NICAM error measurement period 0: 128 ms (Default) 1: 64 ms MAE 0 Max. Allowed Errors. Defines the NICAM error decoding for mute function. 0: 511 Max (Default) 1: 255 Max NICAM_BER Address: 3Eh Type: R Bit 7 Bit 6 Bit 5 NICAM Bit Error Rate Register Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ERROR[7:0] Bit Name ERROR[7:0] Reset 00000000 NICAM Error Counter Value Function NICAM_STAT Address: 3Fh Type: R Bit 7 NIC_DET Bit 6 F_MUTE Bit 5 LOA NICAM Detection Status Register Bit 4 Bit 3 CBI[3:0] Bit 2 Bit 1 Bit 0 NIC_MUTE Bit Name NIC_DET 0 Reset NICAM Signal Detect 0: NICAM signal no detected 1: NICAM signal detected Function F_MUTE 0 Frame Mute 0: No mute 1: Mute due to Superframe Alignment Loss LOA 0 Loss of Frame Alignment Word (FAW) 0: No Alignment Lost 1: Frame Alignment Word Lost CBI[3:0] NIC_MUTE 0000 0 Indicates the received NICAM control bits Indicates the NICAM decoder mute 79/156 Register List STV82x7 12.8 Stereo Mode ZWT_CTRL Zweiton Detector Control Register Address: 40h Type: R/W Bit 7 LRST_TONE_OFF Bit 6 STD_MODE Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 THRESH[3:0] TSCTRL[1:0] Bit Name LRST_TONE_OFF Reset 0 Control of the reset of the tone detector Function 0: Periodical reset of tone detection enabled 1: Periodical reset of tone detection disabled STD_MODE_C THRESH[3:0] 0 1100 0: German standard (Default) 1: Korean standard Defines the threshold of the detector for pilot and tone frequencies. Level (% of the mid scale) 0000 0001 0010 0011 0100 0101 0110 0111 TSCTRL[1:0] 00 0 6.25 12.5 18.75 25 31.25 37.5 43.75 1000 1001 1010 1011 1100 (Default) 1101 1110 1111 Level (% of the mid scale) 50 56.25 62.5 68.75 75 81.25 87.5 93.75 Defines both the detection time and the error probability (reliability of the detection). Sample Accumulation 00 01 (Default) 10 11 1024 1024 2048 2048 Decision Count 2 3 2 3 Time (ms) 256 384 512 768 Error Probability 10-4 10-6 10-7 10-9 ZWT_TIME Address: 41h Type: R/W Bit 7 0 Bit 6 0 Bit 5 0 Zweiton Detector Timing Register Bit 4 0 Bit 3 0 Bit 2 Bit 1 ZWT_TIME[2:0] Bit 0 Bit Name Bit [7:3] Reset 00000 Reserved. Function 80/156 STV82x7 Register List Bit Name ZWT_TIME[2:0] Reset 100 Function Defines the period (duration) of the reset tone used for tone detection system reset. 000: 256 ms 001: 512 ms 010: 768 ms 011: 1024 ms 100: 1280 ms 101: 1536 ms 110: 1792 ms 111: 2040 ms ZWT_STAT Address: 42h Type: R Bit 7 LRST_TONE_ OFF Bit 6 0 Bit 5 0 Zweiton Status Register Bit 4 0 Bit 3 ZW_STAT_ RDY Bit 2 ZW_DET Bit 1 ZW_ST Bit 0 ZW_DM Bit Name LRST_TONE_OFF Reset 0 Function Indicates the status of the control bit programmed in the reg ZWT-CTRL 0: Periodical reset of tone detection enabled 1: Periodical reset of tone detection disabled Bits[6:4] ZW_STAT_RDY ZW_DET ZW_ST ZW_DM 000 0 0 0 0 Reserved. Periodic flag indicating when the tone detection flags are updated and ready to be read Pilot Detection Flag Stereo Tone Detection Flag Dual Mono Tone Detection Flag 12.9 Analog Control ADC_CTRL Address: 56h Type: R/W Bit 7 Bit 6 Bit 5 0 Bit 4 0 Bit 3 ADC_POWER _UP Bit 2 Bit 1 ADC_INPUT_SEL[2:0] Bit 0 I2S_DATA0_CTRL[1:0] Bit Name I2S_DATA0_CTRL[1:0] Reset 00 00 01 10 11 = SCART = L, R = HP or Srnd = C/Sub Function Bits[7:4] 0000 Reserved. 81/156 Register List STV82x7 Bit Name ADC_POWER_UP Reset 1 Function Control of the power up of the Audio ADC 0: ADC in power down mode 1: Wake up of the ADC ADC_INPUT_SEL [2:0] 000 Selection of the ADC input signal 000: SCART 1 (Default) 001: SCART 2 010: SCART 3 011: SCART 4 100: Mono input Other: reserved SCART1_2_OUTPUT_CTRL Address: 57h Type: R/W Bit 7 SC2_MUTE Bit 6 Bit 5 SC2_OUTPUT_SEL[2:0] Bit 4 Bit 3 SC1_MUTE Bit 2 Bit 1 SC1_OUTPUT_SEL[2:0] Bit 0 Bit Name SC2_MUTE Reset 1 Function Mute command for the output SCART 2 0: output not muted 1: output muted 010 SC2_OUTPUT_SEL[2:0] Selection of the output SCART 2 configuration: 000: DSP 001: Mono input 010: Input SCART 1 (Default) 011: Input SCART 2 100: Input SCART 3 101: Input SCART 4 Other: Reserved 1 SC1_MUTE Mute command for the output scart 1 0: output not muted 1: output muted SC1_OUTPUT_SEL[2:0] 000 Selection of the output SCART 1 configuration: 000: DSP (Default) 001: Mono input 010: Input SCART 1 011: Input SCART 2 100: Input SCART 3 101: Input SCART 4 Other: Reserved SCART3_OUTPUT_CTRL Address: 58h Type: R/W Bit 7 0 Bit 6 0 Bit 5 0 Bit 4 0 Bit 3 SC3_MUTE Bit 2 Bit 1 SC3_OUTPUT_SEL[2:0] Bit 0 82/156 STV82x7 Register List Bit Name Bits[7:4] Reset 0000 1 Reserved. Function Mute command for the output SCART 3 0: output not muted 1: output muted SC3_MUTE SC3_OUTPUT_SEL[2:0] 011 Selection of the output SCART 3 configuration: 000: DSP 001: Mono input 010: Input SCART 1 011: Input SCART 2 (Default) 100: Input SCART 3 101: Input SCART 4 Other: Reserved 12.10 Clocking 2 FS2_DIV Address: 5Ah Type: R/W Bit 7 0 Bit 6 0 Bit 5 NDIV2[1:0] Bit 4 Bit 3 Bit 2 Bit 1 SDIV2[2:0] Bit 0 FS2 I/O Divider Programming Register Bit Name Bit [7:6] NDIV2[1:0] Bit 4 SDIV2[2:0] 0 Reset Reserved. FS2 Input clock divider selection Reserved. FS2 Output clock divider selection Function 01 0 001 FS2_MD Address: 5Bh Type: R/W Bit 7 0 Bit 6 0 Bit 5 0 FS2 Coarse Selection Register Bit 4 Bit 3 Bit 2 MD2[4:0] Bit 1 Bit 0 Bit Name Bits[7:5] MD2[4:0] Reset 000 10000 Reserved. FS2 Coarse Selection Function 83/156 Register List FS2_PE_H Address: 5Ch Type: R/W Bit 7 Bit 6 Bit 5 Bit 4 PE_H2[7:0] Bit 3 Bit 2 Bit 1 STV82x7 FS2 Fine Selection Register (MSBs) Bit 0 Bit Name PE_H2[7:0] Reset 0101 1100 FS2 Fine Selection (MSBs) Function FS2_PE_L Address: 5Dh Type: R/W Bit 7 Bit 6 Bit 5 FS2 Fine Selection Register (LSBs) Bit 4 PE_L2[7:0] Bit 3 Bit 2 Bit 1 Bit 0 Bit Name PE_L2[7:0] Reset 0010 1001 FS2 Fine Selection (LSBs) Function 12.11 DSP Control HOST_CMD Address: 80h Type: R/W Bit 7 IT_IN_DSP Bit 6 0 Bit 5 0 Bit 4 0 Bit 3 0 Bit 2 HW_RESET Bit 1 Bit 0 DSP Hardware Control Register Bit Name IT_IN_DSP Bits[6:3] HW_RESET Bits[1:0] Reset 0 0000 0 00 Valid I2C table. Reserved. Function DSP Hardware run when set, see Figure 31 Reserved. 84/156 STV82x7 IRQ_STATUS Address: 81h Type: R/W Bit 7 IRQ7 Bit 6 IRQ6 Bit 5 IRQ5 Bit 4 IRQ4 Bit 3 IRQ3 Bit 2 IRQ2 Bit 1 IRQ1 Register List IRQ Status Register Bit 0 IRQ0 Bit Name Bits[7:4] IRQ3 IRQ2 IRQ1 IRQ0 Reset 0000 0 0 0 0 Reserved. Unmute HP/Srnd DAC IRQ HP connection/deconnection IRQ I2S lock lost IRQ Auto-Standard IRQ Function SOFT_VERSION Address: 82h Type: R Bit 7 Bit 6 Bit 5 Embedded Software Version Register Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 SOFT_VERSION[7:0] Bit Name SOFT_VERSION[7:0] Reset 0000 0002 Version of the Embedded software. Function ONCHIP_ALGOS Address: 83h Type: R Bit 7 0 Bit 6 PRO_LOGIC_ SELECT Bit 5 NICAM Bit 4 I2S_INPUT Bit 3 TRUBASS Bit 2 TRU SURROUND Bit 1 Bit 0 PRO_LOGIC MULTICHANNEL Bit Name Bit 7 PRO_LOGIC_SELECT NICAM Reset 0 0 0 Reserved. 0: Dolby Pro Logic I 1: Dolby Pro Logic II NICAM Demodulator is present when set. Function 85/156 Register List STV82x7 Bit Name I2S_INPUT DIALOG_CLARITY TRUBASS TRUSURROUND PRO_LOGIC MULTICHANNEL Reset 0 0 0 0 0 0 0: 1 I2S input 1: 3 I2S inputs Function SRS Dialog Clarity algorithm is present when set. SRS Trubass algorithm is present when set. SRS Trusurround algorithm is present when set. Dolby Pro Logic algorithm is present when set. Multichannels output is present when set. DSP_STATUS Address: 84h Type: R Bit 7 0 Bit 6 0 Bit 5 0 DSP Status Register Bit 4 0 Bit 3 0 Bit 2 0 Bit 1 0 Bit 0 INIT_MEM Bit Name Bits[7:1] INIT_MEM Reset 0000000 Reserved. DSP Initialization 0 0: DSP is not initialized. 1: DSP is initialized. Function DSP_RUN Address: 85h Type: R/W Bit 7 0 Bit 6 0 Bit 5 0 Bit 4 0 Bit 3 0 Bit 2 0 Bit 1 HOST_ NO_INIT Bit 0 HOST_RUN Bit Name Bits[7:6] Bits[5:4] Bits[3:2] HOST_ NO_INIT HOST_RUN Reset 00 00 00 0 0 Reserved Reserved Reserved Function 0: I2C register table is initialized when we soft reset 1: I2C register table is not initialized when we soft reset 0: soft reset DSP 1: start DSP processing 86/156 STV82x7 I2S_IN_CONFIG Address: 86h Type: R/W Bit 7 LOCK_MODE _EN Bit 6 0 Bit 5 SYNC Bit 4 LRCLK_START Bit 3 LRCLK_ POLARITY Bit 2 SCLK_ POLARITY Bit 1 DATA_CFG Register List I²S Configuration Register Bit 0 I2S_MODE Bit Name LOCK_MODE_EN Bit 6 Reset 1 0 0: Disable Lock Mode for external I2S input 1: Enable Lock Mode for external I2S input Reserved. I2S synchronisation: Function SYNC 0 0: Capture directly 1: Wait for synchro according to LRCLK POLARITY, first data take: LRCLK_START 0 0: Left 1: Right Polarity of the left data 0: Falling edge 1: Rising edge 0: LSB First 1: MSB First 0: Non standard mode 1: Standard mode (Refer to Figure 29) LRCLK_POLARITY SCLK_POLARITY DATA_CFG I2S_MODE 0 1 1 0 AV_DELAY Address: 89h Type: R/W Bit 7 Bit 6 Bit 5 Audio/Video Delay Register Bit 4 DELAY_TIME Bit 3 Bit 2 Bit 1 Bit 0 DELAY_ON Bit Name DELAY_TIME Reset Audio Delay Time (see Table 19) 0000000: 0 ms 0000000 ... 0111100: 60 ms (48 kHz) ... 1011010: 90 ms (32 kHz) Function DELAY_ON 0 Audio/video delay is enabled when set. 87/156 Register List Note: AV_DELAY acts on both LS and HP paths simultaneously (same delay) Table 19: Audio/Video Delay (LipSync) Configuration STV82x7 Register Value Input source AV_DELAY(89h) DELAY_TIME[6:0] 10110100 10110100 10110100 10110100 01111000 01111000 01111000 01111000 90 90 90 90 60 60 60 60 PCM_SRND _DELAY(ABh) PCM_CENTER _DELAY(ACh) LS_L LS_R Output HP_L/R Scart_L Scart_R CENTER DELAY Source Source Source Source Source Source Source Source Source Source SNRD_DELAY[4:0] _DELAY[3:0] _ON SIF Scart SIF Scart SIF Scart SIF Scart SIF Scart 1 1 1 1 1 1 1 1 xxx00000 xxx00000 xxx11110 xxx11110 xxx00000 xxx00000 xxx11110 xxx11110 0 0 30 30 0 0 30 30 xxxx0000 0 xxxx1010 10 xxxx0000 0 xxxx1010 10 xxxx0000 0 xxxx1010 10 xxxx0000 0 xxxx1010 10 90 60 60 60 90 60 60 60 60 30 30 30 90 60 60 60 90 60 60 60 60 30 30 30 90 60 60 60 90 60 60 60 60 30 30 30 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SIF or Scart (32Khz) Scart only (48Khz) Note: All audio delay values are in milliseconds. 12.12 Automatic Standard Recognition AUTOSTD_CTRL Address: 8Ah Type: R/W Bit 7 0 Bit 6 0 Bit 5 0 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 LDK_SW Automatic Standard Recognition Control Register FORCE_SQUE SINGLE_SHOT LCH DK_DEV[1:0] Bit Name Bits[7:5] FORCE_SQUELCH Reset 000 Reserved. Allow to force squelch detection 0 Function 0: FM squelch is taken into consideration for MONO detection 1: FM squelch is not taken into consideration for MONO detection SINGLE_SHOT 0 Single Shot Mode Selection 0: Single Shot mode is not selected 1: Single Shot mode is selected1 DK_DEV[1:0] 00 Selects FM deviation configuration to take into account of overmodulation in DK_NICAM standard. 00: FM 50 kHz (Default) 01: FM 200 kHz 10: FM 350 kHz 11: FM 500 kHz LDK_SW 1 Makes exclusive the auto search of DK/K1/K2/K3 and L/L’ standard 0: DK/K1/K2/K3 standard auto-search / L/L’ disabled 1: L/L’ standard auto-search DK/K1/K2/K3 disabled 88/156 STV82x7 Register List 1. Single_Shot mode can be used before disabling the Automatic Standard Recognition (Autostandard) to pre-program demodulator registers in a defined standard and reduce I²C programming in Manual mode Note: Only standard deviation FM 50K kHz is compatible with other D/K1/K2/K3 standards in Automatic Standard Recognition Search mode. FM deviation superior to 350 kHz will degrade strongly NICAM reception due to overlapping of FM and QPSK IF spectrum in DK-NICAM standard. L/L’ and DK/K1/K2/K3 standard cannot be discriminated in Automatic Standard Recognition Search mode because the same frequency is used for the mono IF carrier. AUTOSTD_STANDARD_DETECT Address: 8Bh Type: R/W Bit 7 0 Bit 6 Bit 5 Bit 4 Auto Standard Check Standard Register Bit 3 LDK_SCK Bit 2 I_SCK Bit 1 BG_SCK Bit 0 MN_SCK NICAM_C4_O NICAM_GAP_ NICAM_MON FF MODE O_IN Bit Name NICAM_C4_OFF NICAM_GAP_MODE NICAM_MONO_IN LDK_SCK Reset 0 1 0 Function 0: Autostandard will consider the C4 bit for MONO backup 1: Autostandard will ignore the C4 bit for MONO backup 0: NICAM, fast search 1: NICAM, slow search (no perturbations on LEFT channel in search mode) 0: the MONO backup for NICAM comes from internal demodulator 1: the MONO backup for NICAM comes from MONO input L/L’ or D/K Mono Standard Enable 1 0: Disabled 1: Enabled I Mono Standard Enable I_SCK 1 0: Disabled 1: Enabled B/G Mono Standard Enable BG_SCK 1 0: Disabled 1: Enabled M/N Mono Standard Enable MN_SCK 1 0: Disabled 1: Enabled Note: Autostandard is off when all mono standards are disabled (LDK_SCK = 0, I_SCK = 0, BG_SCK = 0 and MN_SCK = 0). 89/156 Register List AUTOSTD_STEREO_DETECT Auto Standard Check Stereo Register Address: 8Ch Type: R/W Bit 7 LDK_ZWT3 Bit 6 LDK_ZWT2 Bit 5 LDK_ZWT1 Bit 4 LDK_NIC Bit 3 I_NIC Bit 2 BG_ZWT Bit 1 BG_NIC STV82x7 Bit 0 MN_ZWT Bit Name LDK_ZWT3 Reset Function D/K3 Zweiton (A2*) Stereo Standard Enable 0 0: Disabled 1: Enabled D/K2 Zweiton (A2*) Stereo Standard Enable LDK_ZWT2 0 0: Disabled 1: Enabled D/K1 Zweiton (A2*) Stereo Standard Enable LDK_ZWT1 0 0: Disabled 1: Enabled D/K NICAM Stereo Standard Enable LDK_NIC 1 0: Disabled 1: Enabled I NICAM Stereo Standard Enable I_NIC 1 0: Disabled 1: Enabled B/G Zweiton (A2) Standard Enable BG_ZWT 1 0: Disabled 1: Enabled B/G NICAM Standard Enable BG_NIC 1 0: Disabled 1: Enabled M/N Zweiton (A2+) Standard Enable MN_ZWT 1 0: Disabled 1: Enabled Note: Stereo standard covers all transmission modes (stereo or multi-language) of the NICAM or Zweiton (A2, A2* or A2+) system. AUTOSTD_TIMERS Address: 8Dh Type: R/W Bit 7 Bit 6 Bit 5 Detection Time Out Register Bit 4 NICAM_TIME[2:0] Bit 3 Bit 2 Bit 1 ZWEITON_TIME[2:0] Bit 0 FM_TIME[1:0] 90/156 STV82x7 Register List Bit Name FM_TIME[1:0] Reset FM/AM Detection Time-out 10 00 : 16 ms 01: 32 ms 10: 48 ms (Default) 11: 64 ms Function NICAM_TIME[2:0] 100 NICAM Detection Time-out 000: 96 ms 001: 128 ms 010: 160 ms 011: 192 ms 100: 224 ms (Default) 101: 256 ms 110: 288 ms 111: 320 ms ZWEITON_TIME[2:0] 100 Zweiton Detection Time-out 000: forbidens 001: 512 ms 010: 768 ms 011: 1024 ms 100: 1280 ms (Default) 101: 1536 ms 110: 1792 ms 111: 2040 ms Note: The time-out default value is optimum and does not normally need to be changed. AUTOSTD_STATUS Address: 8Eh Type: R Bit 7 STEREO_ID Bit 6 STEREO_OK Bit 5 MONO_OK Detection Standard Status Register Bit 4 AUTOSTD_ON Bit 3 Bit 2 Bit 1 Bit 0 STEREO_SID[1:0] MONO_SID[1:0] Bit Name STEREO_ID Reset Function Stereo Mode Detection flag activated when all of the following conditions are true: 1. Stereo standard coming from the demodulator is selected on the Loudspeakers output 2. Stereo transmission modes are: - Zweiton Stereo Carrier AND Stereo Modulation (indifferently German or Korean standard) - NICAM stereo with backup (CBI = 1000) - NICAM stereo with no backup (CBI = 0000) 3. Stereo is selected for loudspeaker ouput (bit LS_LANGUAGE[1:0]) Automatic Standard Recognition System Status 0 AUTOSTD_ON 0 0: Automatic Standard Recognition System is OFF 1: Automatic Standard Recognition System is ON Identification of the detected TV sound standard. See Table 20. STEREO_SID[1:0] MONO_SID[1:0] STEREO_OK MONO_OK 00 00 0 0 STEREO STANDARD DETECTED MONO STANDARD DETECTED 91/156 Register List Table 20: TV Sound Standards System M/N B/G I L STV82x7 Mono Sound (MHz) 4.5 (FM 27k) 5.5 (FM 50k) 6.0 (FM 50k) 6.5 (AM) 6.5 (FM 50k) 6.5 (FM 200k) MONO_SID [1:0] 00 01 LDK_SW X X X DK_DEV [1:0] XX XX XX XX XX 00 01 Stereo Sound (MHz) 4.724 (Zweiton A2+) 5.85 (NICAM 40%) 5.742 (Zweiton A2) 6.552 (NICAM 100%) 5.85 (NICAM 40%) STEREO_SID [1:0] 00 00 01 00 00 10 X 1 D/K 6.5 (FM 350k) 6.5 (FM 500k) 11 0 10 11 0 XX XX XX XX 5.85 (NICAM 40%) 00 5.85 (NICAM 40%) 6.258 (Zweiton A2*) 6.742 (Zweiton A2*) 5.742 (Zweiton A2*) 00 01 10 11 D/K1/K2/ K3 0 6.5 (FM 50k) 0 0 Note: X means don’t care. 12.13 Audio Preprocessing and Selection Registers DC_REMOVAL_INPUT Address: 90h Type: R/W Bit 7 0 Bit 6 0 Bit 5 0 Bit 4 0 Bit 3 0 Bit 2 DC_SCART Bit 1 DC_NICAM Bit 0 DC_DEMOD DC Removal Register Bit Name Bits[7:3] DC_SCART Reset 00000 1 Reserved. 0: SCART input, DC removal inactive 1: SCART input, DC removal active 0: NICAM input, DC removal inactive 1: NICAM input, DC removal active 0: FM input, DC removal inactive 1: FM input, DC removal active Function DC_NICAM 1 DC_DEMOD 1 92/156 STV82x7 DC_REMOVAL_L Address: 91h Type: R Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Register List FM DC Offset Left Registerl Bit 0 DC_REMOVAL_L[7:0] Bit Name DC_REMOVAL_L[7:0] Reset Function Displays (in two’s complement format) the FM (or AM) DC offset level after demodulation on channel 1 (and removed automatically). 0000 0000 In FM mode, the DC offset value gives a direct value of the carrier frequency offset which is used to compensate the DCO with the CAROFFSET1 value in the event of an out-of-standard offset. The range and the resolution depend upon the FM bandwidth programmed defined in register BCOEFF1. See Table 21. DC_REMOVAL_R Address: 92h Type: R Bit 7 Bit 6 Bit 5 FM DC Offset Right Register Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 DC_REMOVAL_R[7:0] Bit Name DC_REMOVAL_R[7:0] Reset Function Displays (in two’s complement format) the FM (or AM) DC offset level after demodulation on channel 2 (and removed automatically). 0000 0000 In FM mode, the DC offset value gives a direct value of the carrier frequency offset which is used to compensate the DCO with the CAROFFSET2 value in the event of an out-ofstandard offset. The range and the resolution depend upon the FM bandwidth programmed defined in register BCOEFF2. See Table 21. Table 21: DC_REMOVAL_L/R Range and Resolution FM mode Small Standard & A2 Standard Medium Large Range (kHz) ± 96 ± 192 ± 384 ± 768 Resolution (kHz) 0.750 1.5 3 6 93/156 Register List PRESCALE_SELECT Address: 93h Type: R/W Bit 7 0 Bit 6 0 Bit 5 0 Bit 4 0 Bit 3 0 Bit 2 0 Bit 1 0 STV82x7 AM/FM Prescaling Select Register Bit 0 AM_FM_ SELECT Bit Name Bits[7:1] AM_FM_SELECT Reset 0000000 Reserved. 0 Function 0: FM prescale is applied to demodulator channels 1: AM prescale is applied to demodulator channels PRESCALE_AM Address: 94h Type: R/W Bit 7 0 Bit 6 Bit 5 AM Prescaling Register Bit 4 Bit 3 PRESCALE_AM Bit 2 Bit 1 Bit 0 Bit Name Bit 7 PRESCALE_AM[6:0] 0 Reset Reserved. Function 0000000 -12 to + 24 dB AM prescaling to normalize the AM demodulated signal level before audio processing. Auto level control can be implemented by I2C software using the Peak Level Detector. (Default value = 0 dB) 0110000 0101111 0101110 0101101 0101100 G (dB) +24 +23.5 +23 +22.5 +22 etc. 1101100 1101011 1101010 1101001 1101000 G (dB) -10 -10.5 -11 -11.5 -12 PRESCALE_FM Address: 95h Type: R/W Bit 7 0 Bit 6 Bit 5 FM Prescaling Register Bit 4 Bit 3 PRESCALE_FM Bit 2 Bit 1 Bit 0 94/156 STV82x7 Register List Bit Name Bit 7 0 Reset Reserved. Function PRESCALE_FM[6:0] 0001100 -12 to + 24 dB FM prescaling to normalize the FM demodulated signal level before audio processing. Auto level control can be implemented by I2C software using the Peak Level Detector. (Default value = +6 dB) 0110000 0101111 0101110 0101101 0101100 G (dB) +24 +23.5 +23 +22.5 +22 etc. 1101100 1101011 1101010 1101001 1101000 G (dB) -10 -10.5 -11 -11.5 -12 PRESCALE_NICAM Address: 96h Type: R/W Bit 7 0 Bit 6 Bit 5 NICAM Prescaling Register Bit 4 Bit 3 PRESCALE_NICAM Bit 2 Bit 1 Bit 0 Bit Name Bit 7 0 Reset Reserved. Function PRESCALE_NICAM[6:0] 011010 -6 to + 24 dB NICAM prescaling to normalize the NICAM demodulated signal level before audio processing. Auto level control can be implemented by I2C software using the Peak Level Detector. (Default value = +13 dB) 0110000 0101111 0101110 0101101 0101100 G (dB) +24 +23.5 +23 +22.5 +22 etc. 1111000 1110111 1110110 1110101 1110100 G (dB) -4 -4.5 -5 -5.5 -6 PRESCALE_SCART Address: 97h Type: R/W Bit 7 0 Bit 6 0 Bit 5 SCART Prescaling Register Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PRESCALE_SCART Bit Name Bit [7:6] Reset 00 Reserved. Function 95/156 Register List STV82x7 Bit Name PRESCALE_ SCART[5:0] Reset Function 0000000 -12 to + 12 dB SCART prescaling to normalize the SCART signal level before audio processing. Auto level control can be implemented by I2C software using the Peak Level Detector. (Default value = 0 dB) 011000 010111 010110 010101 010100 G (dB) +12 +11.5 +11 +10.5 +10 etc. 101100 101011 101010 101001 101000 G (dB) -10 -10.5 -11 -11.5 -12 PRESCALE_I2S_0 Address: 98h Type: R/W Bit 7 0 Bit 6 0 Bit 5 I2S_0 Prescaling Register Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PRESCALE_I2S_0[5:0] Bit Name Bits [7:6] PRESCALE_I2S_0[5:0] Reset 00 000000 Reserved. Function -12 to + 12 dB I2S_0 prescaling to normalize the I2S_0 signal level before audio processing. Auto level control can be implemented by I2C software using the Peak Level Detector. (Default value = 0 dB) 011000 010111 010110 010101 010100 G (dB) +12 +11.5 +11 +10.5 +10 etc. 101100 101011 101010 101001 101000 G (dB) -10 -10.5 -11 -11.5 -12 PRESCALE_I2S_1 Address: 99h Type: R/W Bit 7 0 Bit 6 0 Bit 5 I2S_1 Prescaling Register Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PRESCALE_I2S_1[5:0] Bit Name Bits [7:6] Reset 00 Reserved. Function 96/156 STV82x7 Register List Bit Name Reset Function -12 to + 12 dB I2S_1 prescaling to normalize the I2S_1 signal level before audio processing. Auto level control can be implemented by I2C software using the Peak Level Detector. (Default value = 0 dB) 011000 010111 010110 010101 010100 G (dB) +12 +11.5 +11 +10.5 +10 etc. 101100 101011 101010 101001 101000 G (dB) -10 -10.5 -11 -11.5 -12 PRESCALE_I2S_1[5:0] 000000 PRESCALE_I2S_2 Address: 9Ah Type: R/W Bit 7 0 Bit 6 0 Bit 5 I2S_2 Prescaling Register Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PRESCALE_I2S_2[5:0] Bit Name Bits [7:6] Reset 00 Reserved. Function PRESCALE_I2S_2[5:0] 000000 -12 to + 12 dB I2S_2 prescaling to normalize the I2S_2 signal level before audio processing. Auto level control can be implemented by I2C software using the Peak Level Detector. (Default value = 0 dB) 011000 010111 010110 010101 010100 G (dB) +12 +11.5 +11 +10.5 +10 etc. 101100 101011 101010 101001 101000 G (dB) -10 -10.5 -11 -11.5 -12 DEEMPHASIS_DEMATRIX Address: 9Bh Type: R/W Bit 7 0 Bit 6 0 Bit 5 NICAM_ DEMATRIX Deemphasis-Dematrix Register Bit 4 NICAM_ DEEMPH_BY PASS Bit 3 Bit 2 Bit 1 FM_DEEMPH _BYPASS Bit 0 FM_DEEMPH _SW FM_DEMATRIX Bit Name Bits [7:6] Reset 00 Reserved. Function 97/156 Register List STV82x7 Bit Name NICAM_DEMATRIX 0 Reset Dematrixing for NICAM demodulator input: 00: L=ch0, R=ch1 01: L=ch1, R=ch0 Function NICAM_DEEMPH_ 0 BYPASS FM_DEMATRIX[3:2] 00 0: NICAM deemphasis is not bypassed. 1: NICAM deepmhasis is bypassed. Dematrixing for FM demodulator input: 00: L=ch0, R=ch1 01: L=ch0+ch1, R=ch0-ch1 10: L=2ch0-ch1, R=ch1 11: L=(ch0+ch1)/2, R=(ch0-ch1)/2 FM_DEEMPH_ BYPASS FM_DEEMPH_SW 0 0 0: FM deemphasis is not bypassed. 1: FM deepmhasis is bypassed. 0: 50 µs FM deemphasis.| 1: 75 µs FM deepmhasis. PEAK_DET_INPUT Address: 9Dh Type: R Bit 7 PEAK_LOCATION Bit 6 0 Bit 5 Peak Detector Input source Register Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PEAK_L_R_RANGE PEAK_DET_INPUT[1:0] Bit Name PEAK_LOCATION 0 Reset Function Peak detector location : 0: Peak detector placed between FM/NICAM Dematrix and Audio Matrix or between I²S Prescale and DownMix 1: Peak detector placed before DC removal (For input saturation detection) Reserved. Peak L-R range. 0000 : 0 dBFS to -42 dBFS 0001 : -6 dBFS to -48 dBFS 0010 : -12 dBFS to -54 dBFS 0011 : -18 dBFS to -60 dBFS ... Peak Level Detector Source Selection 00: AM/FM or I2S 0 01: NICAM or I2S 1 10: SCART or I2S 2 Bit 6 PEAK_L_R_RANGE 0 0000 PEAK_DET_INPUT[1:0] 00 PEAK_DET_L Address: 9Eh Type: R Bit 7 OVERLOAD_L Bit 6 Bit 5 Peak Level Detector Status Register (L channel) Bit 4 Bit 3 PEAK_L[6:0] Bit 2 Bit 1 Bit 0 98/156 STV82x7 Register List Bit Name OVERLOAD_L[7] PEAK_L[6:0] 0 Reset Function Memorise overload on the peak detection. This field can be reset. Displays the Absolute Peak Level of the audio source selected. The measured value is updated continuously every 64 ms. The range varies linearly from the full scale (0 dB) down to 1/ 256 of the full scale (-48 dB). In AM/FM Mono mode, only the PEAK_L[7:0] value must be taken into account. In FM Mono mode, the audio peak level range depends upon the programmed FM bandwidth. The unique difference is that the measurement is done after Sound pre-processing (DC offset removal, Prescaling, De-emphasis and Dematrixing). In FM Stereo mode, the maximum value may be used to check if the incoming signal level is correctly adjusted by the prescaling factor or if there are no FM overmodulation problems (clipping). Programmable values are listed in Table 21. 00000000 PEAK_DET_R Address: 9Fh Type: R Bit 7 OVERLOAD_R Bit 6 Bit 5 Peak Level Detector Status Register (R channel) Bit 4 Bit 3 PEAK_R[6:0] Bit 2 Bit 1 Bit 0 Bit Name OVERLOAD_R[7] PEAK_R[7:0] 0 Reset Function Memorise overload on the peak detection. This field can be reset. Displays the Absolute Peak Level of the audio source selected. The measured value is updated continuously every 64 ms. The range varies linearly from the full scale (0 dB) down to 1/256 of the full scale (-48 dB). For more information, refer to register PEAK_DET_L. 0000000 PEAK_DET_L_R Address: A0h Type: R Bit 7 OVERLOAD_L_R Bit 6 Bit 5 Peak Level Detector Status Register (L - R) Bit 4 Bit 3 PEAK_L_R[6:0] Bit 2 Bit 1 Bit 0 Bit Name OVERLOAD_L_R[7] 0 PEAK_L_R[7:0] Reset Function Memorise overload on the peak detection. This field can be reset. Displays the Difference between L and R (L - R) channels for the audio source selected. For more information, refer to register PEAK_DET_L. 0000000 99/156 Register List STV82x7 12.14 Matrixing AUDIO_MATRIX_INPUT Address: A2h Type: R/W Bit 7 0 Bit 6 0 Bit 5 0 Bit 4 0 Bit 3 0 Bit 2 SCART_ INPUT_ SOURCE Bit 1 HP_INPUT_ SOURCE Bit 0 LS_INPUT_ SOURCE Audio Matrix Input Selection Register Bit Name Bits [7:3] SCART_INPUT_ SOURCE Reset 00000 0 Reserved. Select input source for SCART output: 0: Demod 1: SCART input 0 Select input source for HP output: 0: Demod 1: SCART input 0 Select input source for LS output: 0: Demod 1: SCART input Function HP_INPUT_ SOURCE LS_INPUT_ SOURCE AUDIO_MATRIX_CONFIG Address: A3h Type: R/W Bit 7 0 Bit 6 0 Bit 5 0 Bit 4 SCART_ MATRIX Bit 3 Bit 2 Bit 1 Bit 0 DEMOD_MATRIX[3:0] Bit Name Bits [7:5] SCART_MATRIX DEMOD_MATRIX [3:0] Reset 000 0 0000 Reserved. Function Indicates the SCART input signal matrixing (see Table 23) Indicates the demod input signal matrixing (see Table 22) 100/156 STV82x7 Table 22: Demod Matrix Input Mode Language -> demod_mx Mono AM/FM with backup Mono AM/FM no backup Zwt St Zwt Dual NICAM Mn, backup NICAM Dual backup NICAM St, backup NICAM Mn, no backup NICAM Dual, no backup NICAM St, no backup 0000 0001 0100 0101 1000 1001 1010 1100 1101 1110 FM_L FM_M1 Register List Stereo L FM FM_R FM_M2 Mono A R L FM (FM_L + FM_R)/2 FM_M1 NIC_M1 NIC_M1 (NIC_L + NIC_R)/2 NIC_M1 NIC_M1 (NIC_L + NIC_R)/2 Mono B L FM (FM_L + FM_R)/2 FM_M2 NIC_M1 NIC_M2 (NIC_L + NIC_R)/2 NIC_M1 NIC_M2 (NIC_L + NIC_R)/2 Mono C L FM FM (FM_L + FM_R)/2 (FM_M1 + FM_M2)/2 FM FM FM FM FM FM Backup mode R R R NIC_M1 NIC_M1 NIC_L NIC_M2 NIC_R Mono AM/FM with backup Mono AM/FM with backup Mono AM/FM with backup Mono AM/FM no backup Mono AM/FM no backup Mono AM/FM no backup NIC_M1 NIC_M1 NIC_L NIC_M2 NIC_R Note: Switching between Stereo and Forced Mono modes can be done using (FM_L + FM_R)/2 or (NIC_L + NIC_R)/2 configurations. Table 23: SCART Matrix Stereo SCART_MX Left 0 1 SCART_L SCART_R Mono A Left Right Left Mono B Right Left Mono C Right Right SCART_R SCART_L SCART_L SCART_R SCART_R SCART_L (SCART_L + SCART_R)/2 (SCART_L + SCART_R)/2 AUDIO_MATRIX_LANGUAGE Address: A4h Type: R/W Bit 7 MUTE_STEREO Bit 6 MUTE_ALL Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 SCART_LANGUAGE[1:0] HP_LANGUAGE[1:0] LS_LANGUAGE[1:0] 101/156 Register List STV82x7 Bit Name MUTE_STEREO MUTE_ALL SCART_ LANGUAGE[1:0] 0 0 Reset Mute outputs with stereo signal input Mute all outputs Select language for SCART output Select language for HPoutput Select language for LS output 00: stereo 01: mono A 10: mono B 11: mono C Function 00 HP_LANGUAGE[1:0] 00 00 LS_LANGUAGE[1:0] DOWNMIX_IN_MODE Address: A6h Type: R/W Bit 7 0 Bit 6 0 Bit 5 0 Bit 4 0 Bit 3 LFE_IN Bit 2 Bit 1 MIX_IN_MODE[2:0] Bit 0 Bit Name Bits[7:4] LFE_IN Reset 0000 0 Reserved Function 0: LFE signal is not inputed throught Downmix Block 1: LFE signal is inputed throught Downmix Block see Table 24 MIX_IN_MODE[2:0] 010 Table 24: DownMix IN modes Parameter Coding (Decimal Format) 0 1 2 3 4 5 6 7 Parameter Field Lebel MODE11 MODE10 MODE20 MODE30 MODE21 MODE31 MODE22 MODE32 Function Mode not used in STV82x7 1/0 (C) 2/0 (L,R) 3/0 (L,R,C) 2/1 (L,R,S) 3/1 (L,R,C,S) 2/2 (L,R,Ls,Rs) 3/2 (L,R,C,Ls,Rs) 102/156 STV82x7 DOWNMIX_OUT_MODE Address:A7h Type: R/W Bit 7 0 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Register List Bit 0 HP_MODE[1:0] SCART_MODE[1:0] LS_OUT_MODE[2:0] Bit Name Bit 7 HP_MODE[1:0] SCART_MODE[1:0] 0 Reset Reserved. see Table 25 see Table 25 see Table 26 Function 10 01 LS_OUT_MODE [2:0] 010 Table 25: DownMix SCART/HP modes Parameter Coding (Decimal Format) 0 1 2 3 Parameter Field Label MIX_VCR_OFF MIX_VCR_PROLOGIC MIX_VCR_STEREO MIX_COSTOM Function Switch off the VCR table setup VCR table setup for Tape outputs (for later decoding by a Dolby Prologic decoder - Lt,Rt) VCR table setup for Stereo and headphone listening (Lo,Ro) reserved Table 26: DownMix LS OUT modes Parameter Coding (Decimal Format) 0 1 2 3 4 5 6 7 Parameter Field Label MODE20t MODE10 MODE20 MODE30 MODE21 MODE31 MODE22 MODE32 Function 2/0 Dolby Surround (Lt,Rt) 1/0 (C) 2/0 (L,R) 3/0 (L,R,C) 2/1 (L,R,S) 3/1 (L,R,C,S) 2/2 (L,R,Ls,Rs) 3/2 (L,R,C,Ls,Rs) 103/156 Register List DOWNMIX_DUAL_MODE Address: A8h Type: R/W Bit 7 0 Bit 6 DUAL_ON Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 STV82x7 Bit 0 LS_DUAL_SELECT[1:0] SCART_DUAL_SELECT[1:0] HP_DUAL_SELECT[1:0] Bit Name Bit 7 DUAL_ON LS_DUAL_SELECT[1:0] 0 0 Reset Reserved. 0: Dual mode disable 1: Dual mode enable Dual Mono Mode on LS output 00: LS dual stereo 00: LS dual left mono Function 00 10: LS dual right mono 11: LS dual mixed SCART_DUAL_SELECT[1:0] 00 Dual Mono Mode on SCART output 00: SCART dual stereo 01: SCART dual left mono 10: SCART dual right mono 11: SCART dual mixed HP_DUAL_SELECT[1:0] 00 Dual Mono Mode on HP output 00: HP dual stereo 01: HP dual left mono 10: HP dual right mono 11: HP dual mixed DOWNMIX_CONFIG Address: A9h Type: R/W Bit 7 0 Bit 6 0 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 LR_UPMIX Bit 0 NORMALIZE SRND_FACTOR[1:0] CENTER_FACTOR[1:0] Bit Name Bits[7:6] SRND_FACTOR [1:0] Reset 00 00 00: -3 dB 01: -4.5 dB 00: -3 dB 01: -4.5 dB 10: -6 dB 11: -6 dB 10: -6 dB 11: -4.5 dB Function CENTER_FACTOR [1:0] 00 LR_UPMIX NORMALIZE 0 1 0: Disable upmixing 1: Enable upmixing (DTS specified) 0: Disable normalization 1: Enable normalization 104/156 STV82x7 Register List 12.15 Audio Processing PRO_LOGIC2_CONTROL Address: AAh Type: R/W Bit 7 PL2_LFE Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 PL2_MODES[2:0] Bit 1 Bit 0 PL2_ACTIVE PL2_OUTPUT_DOWNMIX[2:0] Bit Name PL2_LFE 0 Reset 0: Reset the LFE channel 1: Bypass the LFE channel Function PL2_OUTPUT_ DOWNMIX[2:0] 000 000: not applicable 001: not applicable 010: not applicable 011: 3/0 output mode (L,R,C) 100: 2/1 output mode (L,R,Ls - phantom) 101: 3/1 output mode (L,R,C,Ls) 110: 2/2 output mode (L,R,Ls,Rs - phantom) 111: 3/2 output mode (L,R,C,Ls,Rs) 000: Pro Logic 1 Emulation (forced if DPL version) 001: Virtual (DPL2 version only) 010: Music (DPL2 version only) 011: Movie (standard) (DPL2 version only) 100: Matrix (DPL2 version only) 101: Custom (DPL2 version only) 110: not applicable (DPL2 version only) 111: not applicable (DPL2 version only) 0: Dolby Prologic 2 is not active 1: Dolby Prologic 2 is active PL2_MODES[2:0] 000 PL2_ACTIVE 0 Table 27: Prologic II Decode Mode Configuration PL2 Mode 0 1 2 3 4 5 Decode Mode Pro Logic Emulation Virtual Music Movie/ Standard Matrix Custom Dimension Center Width AutoBalance 1 1 0 1 0 x Panorama Surround Coherence 0 1 1 0 1 x SUR Filtering 2 0 1 0 1 x 3 3 x 3 3 x 0 0 x 0 0 x 0 0 x 0 0 x 105/156 Register List Note: (x = user defined parameter) STV82x7 PCM_SRND_DELAY Address: ABh Type: R/W Bit 7 0 Bit 6 0 Bit 5 0 Bit 4 Bit 3 Bit 2 SNRD_DELAY[4:0] Bit 1 Bit 0 Bit Name Bits[7:5] Reset 000 Reserved. Surround Channel Delay range: 0 to 30 (in ms) Function SNRD_DELAY[4:0] 00000 Note: See Table 19 for audio/video delay configuration. PCM_CENTER_DELAY Address: ACh Type: R/W Bit 7 0 Bit 6 0 Bit 5 0 Bit 4 0 Bit 3 Bit 2 Bit 1 Bit 0 CENTER_DELAY[3:0] Bit Name Bits[7:4] Reset 0000 Reserved. Center Channel Delay range: 0 to 10 (in ms) Function CENTER_DELAY[3:0] 0000 Note: See Table 19 for audio/video delay configuration. PRO_LOGIC2_CONFIG Address: ADh Type: R/W Bit 7 PL2_LFE Bit 6 0 Bit 5 0 Bit 4 Bit 3 Bit 2 PL2_RS_ POLARITY Bit 1 PL2_ PANORAMA Bit 0 PL2_ AUTOBALANCE PL2_SRND_FILTER[1:0] 106/156 STV82x7 Register List Bit Name Bits[7:6] Reset 00 Reserved. Function PL2_SRND_FILTR[1:0] 00 00: 0: Off 01: 1: Shelf Filter (for music and matrix modes) 10: 2: 7 kHz LP 11: 3: not applicable 0: Rs polarity normal 1: Rs polarity inverted 0: Panorama Off 1: Panorama On 0: Autobalance Off 1: Autobalance On PL2_RS_POLARITY PL2_PANORAMA PL2_AUTOBALANCE 0 0 0 See Table 27: Prologic II Decode Mode Configuration for programmation of these bits depending on the decode mode. PRO_LOGIC2_DIMENSION Address: AEh Type: R/W Bit 7 0 Bit 6 Bit 5 PL2_C_WIDTH Bit 4 Bit 3 0 Bit 2 Bit 1 PL2_DIMENSION Bit 0 Bit Name Bit 7 0 Reset Reserved. 000: 0, No Spread = OFF 001: 20 010: 28 011: 36 Reserved. 000: -3, most surround 001: -2 010: -1 011: 0, neutral = OFF 100: 1 101: 2 110:3, most center 111: not applicable Function PL2_C_WIDTH[2:0] 000 100: 54 101: 62 110: 69 111: 90, Phantom Bit 3 0 PL2_DIMENSION[2:0] 000 See Table 27: Prologic II Decode Mode Configuration for programmation of these bits depending on the decode mode. 107/156 Register List PRO_LOGIC2_LEVEL Address: AFh Type: R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 STV82x7 Bit 0 PL2_LEVEL Bit Name Reset Input Gain attenuation: 0000 0000: 0 dB 00000000 0000 0001: -0.5 dB ... 1111 1111: -127.5 dB Function PL2_LEVEL[7:0] NOISE_GENERATOR Address: B0h Type: R/W Bit 7 10_DB_ ATTENUATE Bit 6 SRIGHT_ NOISE Bit 5 SLEFT_ NOISE Bit 4 SUB_ NOISE Bit 3 CENTER_ NOISE Bit 2 RIGHT_ NOISE Bit 1 LEFT_ NOISE Bit 0 NOISE_ON Bit Name 10_DB_ATTENUATE 0 SRIGHT_NOISE SLEFT_NOISE SUB_NOISE CENTER_NOISE RIGHT_NOISE LEFT_NOISE NOISE_ON 0 0 0 0 0 0 0 Reset Function 0: noise is outputed with full range 1: noise is outputed with a 10 dB attenuation 1: Generates noise on LS right surround output 1: Generates noise on LS left surround output 1: Generates noise on LS subwoofer output 1: Generates noise on LS center output 1: Generates noise on LS right output 1: Generates noise on LS left output 0: Noise Generation not active 1: Noise Generation is active TRUSRND_CONTROL Address: B1h Type: R/W Bit 7 0 Bit 6 TRUSRND_ MONO_SRND Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 TRUSRND_ MODE Bit 0 TRUSRND_ ON TRUSRND_INPUT_ MODE[3:0] 108/156 STV82x7 Register List Bit Name Bit 7 0 Reset Reserved. 0: Left mono Srnd mode 1: Right mono Srnd mode Function TRUSRND_MONO 0 _SRND TRUSRND_ INPUT_ MODE[3:0] 0000 0000: Mono 0001: L/R stereo (SRS mode) 0010: L/R/S (SRS mode, Prologic 1 Process) 0011: L/R/Ls/Rs (SRS mode) 0100: L/R/C (TruSurround mode) 0101: L/R/C/S (TruSurround mode, Prologic 1 Process) 0110: L/R/C/Ls/Rs (TruSurround mode) 0111: Lt/Rt (TruSurround mode) 1000: L/R/C/Ls/Rs (SRS mode, BS Digital Broadcast) 1001: L/R/C/Ls/Rs (TruSurround, Prologic 2 Music mode) 0: TruSurround mode 1: Bypass mode 0: TruSurround OFF 1: TruSurround ON TRUSRND_MODE 0 0 TRUSRND_ON Note: How to useTruSurround XT: - Implementation of TruSurround XT is done by setting the TRUSRND_ON bit to 1. - TruSurround XT mode must be selected by TRUSRND_ INPUT_ MODE[3:0] bits. - Activation or non-activation of TruSurround XT must be done by using the TRUSRND_MODE bit. TRUSRND_INPUT_GAIN Address: B6h Type: R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 TRUSRND_INPUT_GAIN[7:0] Bit Name Reset Input Gain attenuation: 0000 0000: 0 dB 0000 0001: -0.5 dB ... 1111 1111: -127.5 dB Function TRUSRND_INPUT_ 0000 GAIN[7:0] 0000 TRUSRND_HP_DCL Address: B7h Type: R/W Bit 7 0 Bit 6 0 Bit 5 0 Bit 4 0 Bit 3 0 Bit 2 Bit 1 Bit 0 0 DIALOG_ HEADPHONE CLARITY_ON _ON 109/156 Register List STV82x7 Bit Name Bits[7:2] DIALOG_ CLARITY_ON HEADPHONE_ON Reset 00000 0 0 Reserved. 0: Dialog Clarity OFF 1: Dialog Clarity ON Activate HP mode in TruSurround XT: 0: HP mode OFF 1: HP mode ON Function Bit [0] 0 Reserved. TRUSRND_DC_ELEVATION Address: B8h Type: R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 TRUSRND_DC_ELEVATION[7:0] Bit Name TRUSRND_DC_ ELEVATION[7:0] Reset 0000 1100 Dialog Calrity Elevation: 0000 0000: 0 dB 0000 0001: -0.5 dB ... 1111 1111: -127.5 dB Function TRUBASS_LS_CONTROL Address: BAh Type: R/W Bit 7 0 Bit 6 0 Bit 5 0 Bit 4 0 Bit 3 Bit 2 TRUBASS_LS_SIZE[2:0] Bit 1 Bit 0 TRUBASS_ LS_ON Bit Name Bits[7:3] TRUBASS_LS_SIZE[2:0] Reset 00000 Reserved. 000: LF response 001: LF response 010: LF response 011: LF response at 40 Hz at 60 Hz at 100 Hz at 150 Hz Function 011 100: LF 101: LF 110: LF 111: LF response at 200 response at 250 response at 300 response at 400 Hz Hz Hz Hz TRUBASS_LS_ON 0 0: LS TruBass OFF 1: LS TruBass ON 110/156 STV82x7 TRUBASS_LS_LEVEL Address: BBh Type: R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Register List Bit 0 TRUBASS_LS_LEVEL[7:0] Bit Name TRUBASS_LS_ LEVEL[7:0] Reset 0000 1001 Function Define the amount of SRS TruBass effect for LS outputs: 0000 0000: 0 dB 0000 0001: -0.5 dB ... 1111 1111: -127.5 dB TRUBASS_HP_CONTROL Address: BCh Type: R/W Bit 7 0 Bit 6 0 Bit 5 0 Bit 4 0 Bit 3 Bit 2 TRUBASS_HP_SIZE[2:0] Bit 1 Bit 0 TRUBASS_HP _ON Bit Name Bits[7:3] TRUBASS_HP_ SIZE[2:0] Reset 00000 Reserved. 000: LF response at 40 Hz 001: LF response at 60 Hz 010: LF response at 100 Hz 011: LF response at 150 Hz 0: HP TruBass OFF 1: HP TruBass ON Function 011 100: LF response at 200 Hz 101: LF response at 250 Hz 110: LF response at 300 Hz 111: LF response at 400 Hz TRUBASS_HP_ON 0 TRUBASS_HP_LEVEL Address: BDh Type: R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 TRUBASS_HP_LEVEL[7:0] 111/156 Register List STV82x7 Bit Name TRUBASS_HP_ LEVEL[7:0] Reset 0000 1001 Function Define the amount of SRS TruBass effect for HP outputs: 0000 0000: 0 dB 0000 0001: -0.5 dB ... 1111 1111: -127.5 dB SVC_LS_CONTROL Address: BEh Type: R/W Bit 7 0 Bit 6 0 Bit 5 0 Bit 4 0 Bit 3 Bit 2 Bit 1 SVC_LS_AMP Bit 0 SVC_LS_ON SVC_LS_INPUT[1:0] Bit Name Bits[7:4] SVC_LS_INPUT[1:0] Reset 0000 Reserved. Function Select input for peak detection in multichannel mode: 00 00: Left/Right 01: Center 10: Left/Right/Center 0: 0 dB amplification in auto-mode 1: +6 dB amplification in auto-mode 0: Manual mode(simple prescaler) 1: Automatic mode SVC_LS_AMP SVC_LS_ON 1 0 SVC_LS_TIME_TH Address: BFh Type: R/W Bit 7 Bit 6 SVC_LS_TIME[2:0] Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 SVC_LS_THRESHOLD[4:0] (S) Bit Name SVC_LS_TIME[2:0] Reset Function Time constant for the amplification (6 dB gain step) in automatic mode: 100 000: 30 ms 001: 200 ms 010: 500 ms 011: 1 s See Table 28 and Table 29. 100: 16 s 101: 32 s 110: 64 s 111: 128 s SVC_LS_ THRESHOLD[4:0] 11000 112/156 STV82x7 Table 28: Gain (threshold field) values in Manual mode Manual Mode 00101 00100 00011 00010 00001 00000 11111 11110 Register List Gain (dB) +15.5 +12 +9.5 +6 +3.5 0 -2.5 -6 Manual Mode 11101 11100 11011 11010 11001 11000 10111 10110 Gain (dB) -8.5 -12 -14.5 -18 -20.5 -24 -26.5 -30 Table 29: Threshold values in Automatic mode Automatic Mode 11111 11110 11101 11100 11011 Threshold (dB) -2.5 -6 -8.5 -12 -14.5 Automatic Mode 11010 11001 11000 10111 10110 Threshold (dB) -18 -20.5 -24 -26.5 -30 SVC_HP_CONTROL Address: C0h Type: R/W Bit 7 0 Bit 6 0 Bit 5 0 Bit 4 0 Bit 3 0 Bit 2 0 Bit 1 SVC_ LHP_AMP Bit 0 SVC_HP_ON Bit Name Bits[7:2] SVC_LHP_AMP SVC_HP_ON Reset 000000 1 0 Reserved. 0: 0 dB amplification in auto-mode 1: +6 dB amplification in auto-mode 0: Manual mode (simple prescaler) 1: Automatic mode Function 113/156 Register List SVC_HP_TIME_TH Address: C1h Type: R/W Bit 7 Bit 6 SVC_HP_TIME[2:0] Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 STV82x7 Bit 0 SVC_HP_THRESHOLD[4:0] (S) Bit Name Reset Function Time constant for the amplification (6 dB gain step) in automatic mode: 000: 30 ms 001: 200 ms 010: 500 ms 011: 1 s 100: 16 s 101: 32 s 110: 64 s 111: 128 s SVC_HP_TIME[2:0] 100 SVC_HP_ THRESHOLD[4:0] 11000 see Table 28 and Table 29 SVC_LS_GAIN Address: C2h Type: R/W Bit 7 0 Bit 6 Bit 5 Bit 4 Bit 3 SVC_LS_GAIN[6:0] Bit 2 Bit 1 Bit 0 Bit Name Bit 7 SVC_LS_GAIN[6:0] 0 Reset Reserved. Function Set “make-up” gain applied at SVC LS output: 0000000: +0 dB 0000001: +0.5 dB 0000000 ... 0101110: +23 dB 0101111: +23.5 dB 0110000: +24 dB SVC_HP_GAIN Address: C3h Type: R/W Bit 7 0 Bit 6 Bit 5 Bit 4 Bit 3 SVC_HP_GAIN[6:0] Bit 2 Bit 1 Bit 0 Bit Name Bit 7 0 Reset Reserved. Function 114/156 STV82x7 Register List Bit Name SVC_HP_GAIN[6:0] Reset Function Set “make-up” gain applied at SVC HP output: 0000000: +0 dB 0000001: +0.5 dB 0000000 ... 0101110: +23 dB 0101111: +23.5 dB 0110000: +24 dB STSRND_CONTROL Address: C4h Type: R/W Bit 7 0 Bit 6 0 Bit 5 0 ST WideSurround Control Register Bit 4 0 Bit 3 0 Bit 2 STSRND_ STEREO Bit 1 STSRND_ MODE Bit 0 STSRND_ON Bit Name Bits[7:3] Reset 00000 Reserved. ST WideSurround Mode Function STSRND_STEREO 0 0: ST WideSurround Sound in Mono mode (Default) 1: ST WideSurround Sound in Stereo mode STSRND_MODE 0 ST WideSurround Sound Stereo Mode 0: Movie Mode 1: Music Mode STSRND_ON 0 ST WideSurround Sound Enable 0: ST WideSurround Sound is disabled 1: ST WideSurround Sound is enabled STSRND_FREQ Address: C5h Type: R/W Bit 7 0 Bit 6 0 Bit 5 ST WideSurround Sound Frequency Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 STSRND_BASS[1:0] STSRND_MEDIUM[1:0] STSRND_TREBLE[1:0] Bit Name Bits[7:6] STSRND_BASS[1:0] Reset 00 01 Reserved. Function Defines the bass frequency effect for ST WideSurround Sound. Programmable values are listed in Table 30. Defines the medium frequency effect for ST WideSurround Sound in Movie or Mono mode (no effect in Music mode). Programmable values are listed in Table 30. STSRND_MEDIUM[1:0] 01 115/156 Register List STV82x7 Bit Name Reset Function Defines the treble frequency effect for ST WideSurround Sound in Movie or Mono mode (no effect in Music mode). Programmable values are listed in Table 30. STSRND_TREBLE[1:0] 01 Table 30: Phase Shifter Center Frequencies Phase Shifter Center Frequency BASS_FREQ[1:0] 00 01 (Default) 10 11 40 Hz 90 Hz 120 Hz 160 Hz MEDIUM_FREQ[1:0] 202 Hz 416 Hz 500 Hz 588 Hz TREBLE_FREQ[1:0] 2 kHz 4 kHz 5 kHz 6 kHz STSRND_LEVEL Address: C6h Type: R/W Bit 7 Bit 6 Bit 5 ST WideSurround Gain Register Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 STSRND_GAIN[7:0] Bit Name Reset Function Defines the ST WideSurround Sound component gain in linear scale. Level (%) 1000 0000 (Default) 0111 1111 0111 1110 0111 1101 ........ 100% 99.2% 98.4% 97.6% 0000 0100 0000 0011 0000 0010 0000 0001 0000 0000 Level (%) 3.1% 2.3% 1.6% 0.8% 0% STSRND_GAIN[7:0] 10000000 OMNISURROUND_CONTROL Address: C7h Type: R/W Bit 7 LFE Bit 6 Bit 5 Bit 4 FRONT_ BYPASS Bit 3 Bit 2 Bit 1 Bit 0 OMNISRND_ON ST_VOICE[1:0] OMNI_SURND_INPUT_MODE[3:0] Bit Name LFE 0 Reset 0: Do not use LFE channel 1: Generate LFE channel Function 116/156 STV82x7 Register List Bit Name ST_VOICE[1:0] FRONT_BYPASS OMNISRND_ INPUT_ MODE[3:0] Reset 00 0 00: OFF 01: Low Forced to 0 000: Mono 001: L/R stereo 010: L/R/S 011: L/R/Ls/Rs 0: OmniSurround OFF 1: OmniSurround ON 10: Mid 11: High Function 0000 100: L/R/C 101: L/R/C/S 110: L/R/C/Ls/Rs 111: Lt/Rt (Passive matrix) OMNISURND_ON 0 ST_DYNAMIC_BASS Address: C8h Type: R/W Bit 7 Bit 6 Bit 5 BASS_LEVEL[4:0] Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 DYN_BASS_ ON BASS_FREQ[1:0] Bit Name BASS_LEVEL[4:0] Reset 00000 Set ST Dynamic Bass effect level: 00000: +0 dB 00001: +0.5 dB ... 11101: +14.5 dB 11110: +15 dB 11111: +15.5 dB 00: 100 Hz Cut-Off frequency 01: 150 Hz Cut-Off frequency 10: 200 Hz Cut-Off frequency 11: Reserved 0: ST Dynamic Bass OFF 1: ST Dynamic Bass ON Function BASS_FREQ[1:0] 00 DYN_BASS_ON 0 12.16 5-Band Equalizer / Bass-Treble for Loudspeakers LS_EQ_BT_CTRL Address: C9h Type: R/W Bit 7 0 Bit 6 0 Bit 5 0 Bit 4 0 Bit 3 0 Bit 2 0 Bit 1 LS_EQ_BT_ SW Bit 0 LS_EQ_ON Loudspeakers Equalizer Control Register 117/156 Register List STV82x7 Bit Name Bits[7:2] LS_EQ_BT_SW Reset 000000 0 Reserved. Function 5-Band Equalizer or Bass-Treble selection 0: 5-Band Equalizer is selected for Loudspeakers. 1: Bass-Treble is selected for Loudspeakers. LS_EQ_ON 1 5-Band Equalizer/Bass-Treble for loudspeakers Enable 0: 5-Band Equalizer/Bass-Teble is disabled 1: 5-Band Equalizer/Bass-Teble is enabled (Default) EQ_BANDX_GAIN Address: CAh to CEh Type: R/W Bit 7 Bit 6 Bit 5 Loudspeakers Equalizer Gain Register for BandX Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 EQ_BANDX Bit Name EQ_BANDX[7:0] Reset 0000 0000 Function BandX gain adjustment within a range from -12 dB to +12 dB in steps of 0.25 dB. Band1: 100 Hz, Band2: 330 Hz, Band3: 1 kHz, Band4: 3.3 kHz, Band5: 10 kHz, see Table 31. Note: With positive equalizer settings, internal clipping may occur even with an overall volume of less than 0 dB. This will lead to a clipped output signal. Therefore, it is not recommended to set equalizer bands to a value that, in conjunction with volume, would result in an overall positive gain. Table 31: Loudspeakers Equalizer/Bass-Treble Gain Values (and Headphone Bass-Treble Gain Values) Value 00110000 00101111 00101110 ................ 00000000 (Default) ................ 11010010 11010001 11010000 Gain G (dB) +12 +11.75 +11.50 ..... 0 ..... -11.50 -11.75 -12 118/156 STV82x7 LS_BASS_GAIN Address: CFh Type: R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Register List Loudspeakers Bass Gain Register Bit 0 LS_BASS[7:0] Bit Name LS_BASS[7:0] Reset 0000 0000 Function Bass gain adjustment within a range from -12 dB to +12 dB in steps of 0.25 dB. Note: With positive bass/treble settings, internal clipping may occur even with an overall volume of less than 0 dB. This will lead to a clipped output signal. Therefore, it is not recommended to set bass/ treble bands to a value that, in conjunction with volume, would result in an overall positive gain. LS_TREBLE_GAIN Address: D0h Type: R/W Bit 7 Bit 6 Bit 5 Loudspeakers Treble Gain Register Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 LS_TREBLE Bit Name LS_TREBLE[7:0] Reset 0000 0000 Function Treble gain adjustment within a range from -12 dB to +12 dB in steps of 0.25 dB. Note: With positive bass/treble settings, internal clipping may occur even with an overall volume of less than 0 dB. This will lead to a clipped output signal. Therefore, it is not recommended to set bass/ treble bands to a value that, in conjunction with volume, would result in an overall positive gain. 12.17 Headphone Bass-Treble HP_BT_CONTROL Address: D1h Type: R/W Bit 7 0 Bit 6 0 Bit 5 0 Bit 4 0 Bit 3 0 Bit 2 0 Bit 1 0 Bit 0 HP_BT_ON Headphone Bass-Treble Control Register 119/156 Register List STV82x7 Bit Name Bits [7:1] HP_EQ_ON Reset 0000000 Reserved. 1 Bass-Treble for headphone Enable 0: Bass-Teble is disabled 1: Bass-Teble is enabled (Default) Function HP_BASS_GAIN Address: D2h Type: R/W Bit 7 Bit 6 Bit 5 Headphone Bass Gain Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 HP_BASS_GAIN[7:0] Bit Name HP_BASS_ GAIN[7:0] Reset Function 00000000 Gain Tuning of Headphone Bass Frequency Gain may be programmed within a range between +12 dB and -12 dB in steps of 0.25 dB. Programmable values are listed in Table 31. Note: With positive bass/treble settings, internal clipping may occur even with an overall volume of less than 0 dB. This will lead to a clipped output signal. Therefore, it is not recommended to set bass/ treble bands to a value that, in conjunction with volume, would result in an overall positive gain. HP_TREBLE_GAIN Address: D3h Type: R/W Bit 7 Bit 6 Bit 5 Headphone Treble Gain Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 HP_TREBLE_GAIN[4:0] Bit Name HP_TREBLE_ GAIN[7:0] Reset Function 00000000 Gain Tuning of Headphone Treble Frequency Gain may be programmed within a range between +12 dB and -12 dB in steps of 0.25 dB. Programmable values are listed in Table 31. Note: With positive bass/treble settings, internal clipping may occur even with an overall volume of less than 0 dB. This will lead to a clipped output signal. Therefore, it is not recommended to set bass/ treble bands to a value that, in conjunction with volume, would result in an overall positive gain. 120/156 STV82x7 OUTPUT_BASS_MNGT Address: D4h Type: R/W Bit 7 BASS_ MANAGE_ON Bit 6 0 Bit 5 SUB_ACTIVE Bit 4 GAIN_ SWITCH Bit 3 0 Bit 2 Bit 1 Register List Bit 0 OCFG_NUM[2:0] Bit Name BASS_MANAGE_ON Bit 6 SUB_ACTIVE GAIN_ SWITCH OCFG_NUM Reset 1 0 0 0 000 0: BassManagement disables 1: BassManagement enabled Reserved. Function 0: Subwoofer output is disabled (only in config 2,3,4) 1: Subwoofer output is active 0: Level adjustment ON 1: Level adjustment OFF 000: Bass Management Configuration 0 (refer to Figure 14) 001: Bass Management Configuration 1 (refer to Figure 15) 010: Bass Management Configuration 2 (refer to Figure 16) 011: Bass Management Configuration 3 (refer to Figure 17) 100: Bass Management Configuration 4 (refer to Figure 18) Reserved. Bit 3 0 LS_LOUDNESS Address: D5h Type: R/W Bit 7 0 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 LS_LOUD_GAIN_HR[2:0] Bit 1 Bit 0 LS_ LOUD_ON LS_LOUD_THRESHOLD[2:0] Bit Name Bit 7 LS_LOUD_ THRESHOLD[2:0] Reset 0 000 Reserved. Function Define the volume threshold level since which loudness effect is applied : 000: 0 dB 001: -6 dB 010: -12 dB 011: -18 dB 100: -24 dB 101: -32 dB 110: -36 dB 111: -42 dB LS_LOUD_GAIN_ HR[2:0] 010 Define the amount of Treble added by loudness effect: 000: 0 dB 001: 3 dB 010: 6 dB 011: 9 dB 100: 12 dB 101: 15 dB 110: 18 dB 111: 21 dB 121/156 Register List STV82x7 Bit Name LS_LOUD_ON Reset 0 0: Loudness is not active on LS output 1: Loudness is active on LS output Function HP_LOUDNESS Address: D6h Type: R/W Bit 7 0 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 HP_LOUD_GAIN_HR[2:0] Bit 1 Bit 0 HP_ LOUD_ON HP_LOUD_THRESHOLD[2:0] Bit Name Bit 7 HP_LOUD_ THRESHOLD[2:0] Reset 0 000 Reserved. Function Define the volume threshold level since which loudness effect is applied : 000: 0 dB 001: -6 dB 010: -12 dB 011: -18 dB 100: -24 dB 101: -32 dB 110: -36 dB 111: -42 dB HP_LOUD_GAIN_ HR[2:0] 010 Define the amount of Treble added by loudness effect: 000: 0 dB 001: 3 dB 010: 6 dB 011: 9 dB 100: 12 dB 101: 15 dB 110: 18 dB 111: 21 dB HP_LOUD_ON 0 0: Loudness is not active on HP output 1: Loudness is active on HP output 12.18 Volume VOLUME_MODES Address: D7h Type: R/W Bit 7 Bit 6 Bit 5 0 Bit 4 0 Bit 3 SCART_ VOLUME_ MODE Bit 2 SRND_ VOLUME_ MODE Bit 1 HP_ VOLUME_ MODE Bit 0 LS_ VOLUME_ MODE Set the Volume Modes ANTICLIP_HP ANTICLIP_LS _VOL_CLAMP _VOL_CLAMP Bit Name ANTICLIP_HP_VOL _CLAMP Reset 1 Function The output level is clamped depending on the HP Bass-Treble value to avoid any possible signal clipping on HP output. 0: Volume clamp on HP output is not active 1: Volume clamp on HP output is active 122/156 STV82x7 Register List Bit Name ANTICLIP_LS_VOL _CLAMP Reset 1 Function The output level is clamped depending on the LS Equalizer or LS Bass-Treble value to avoid any possible signal clipping on LS output. 0: Volume clamp on LS output is not active 1: Volume clamp on LS output is active Bits[5:4] SCART_VOLUME_ MODE 00 0 Reserved. Volume mode for SCART output: 0: independent 1: Differential SRND_VOLUME_ MODE 1 Volume mode for Headphone output: 0: independent 1: Differential HP_VOLUME_ MODE 1 Volume mode for Surround output: 0: independent 1: Differential LS_VOLUME_ MODE 1 Volume mode for LS output: 0: independent 1: Differential Note: 1 For the use of volume and balance control please refer to Figure 20 and Figure 21. 2 In differential mode the left register is used for volume control and the right register is used for balance control. LS_L_VOLUME_MSB Address: D8h Type: R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 LS_L_VOLUME_MSB[7:0] Bit Name LS_L_VOLUME_ MSB[7:0] Reset 1001 1000 Function LS 10 bits volume Left channel 8 MSB in independent mode or LS 10 bits volume Left and Right channels 8 MSB in differential mode. See Figure 20: Volume Control on page 38 for range values. LS_L_VOLUME_LSB Address: D9h Type: R/W Bit 7 0 Bit 6 0 Bit 5 0 Bit 4 0 Bit 3 0 Bit 2 0 Bit 1 Bit 0 LS_L_VOLUME_LSB[1:0] 123/156 Register List STV82x7 Bit Name Bits[7:2] LS_L_VOLUME_ LSB[1:0] Reset 000000 Reserved. 00 Function LS 10 bits volume Left channel 2 LSB in independent mode or LS 10 bits volume Left and Right channels 2 LSB in differential mode. See Figure 20: Volume Control on page 38 for range values. The volume value is defined by the following formula: Vol (dB) = Decimal value of LS_L_VOLUME_MSB x 0.5 + Decimal value of LS_L_VOLUME_LSB x 0.125 - 116 dB (each step is 0.125 dB). LS_R_VOLUME_MSB Address: DAh Type: R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 LS_R_VOLUME_MSB[7:0] Bit Name LS_R_VOLUME_ MSB[7:0] Reset Function 0000000 LS 10 bits volume Right channel 8 MSB in independent mode or LS 10 bits Left and Right balance 0 8 MSB in differential mode. See Figure 20: Volume Control on page 38 or Figure 21: Differential Balance on page 39. LS_R_VOLUME_LSB Address: DBh Type: R/W Bit 7 0 Bit 6 0 Bit 5 0 Bit 4 0 Bit 3 0 Bit 2 0 Bit 1 Bit 0 LS_R_VOLUME_LSB[1:0] Bit Name Bits[7:2] LS_R_VOLUME_ LSB[1:0] Reset 000000 Reserved. 00 Function LS 10 bits volume Right channel 2 LSB in independent mode or LS 10 bits Left and Right balance 2 LSB in differential mode. See Figure 20: Volume Control on page 38 or Figure 21: Differential Balance on page 39. 124/156 STV82x7 LS_C_VOLUME_MSB Address: DCh Type: R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Register List Bit 0 LS_C_VOLUME_MSB[7:0] Bit Name LS_C_VOLUME_ MSB[7:0] Reset 1001 1000 LS 10 bits volume Center channel 8 MSB Function See Figure 20: Volume Control on page 38 for range values. LS_C_VOLUME_LSB Address: DDh Type: R/W Bit 7 0 Bit 6 0 Bit 5 0 Bit 4 0 Bit 3 0 Bit 2 0 Bit 1 Bit 0 LS_C_VOLUME_LSB[1:0] Bit Name Bits[7:2] LS_C_VOLUME_ LSB[1:0] Reset 000000 Reserved. 00 LS 10 bits volume Center channel 2 LSB Function See Figure 20: Volume Control on page 38 for range values. The volume value is defined by the following formula: Vol (dB) = Decimal value of LS_C_VOLUME_MSB x 0.5 + Decimal value of LS_C_VOLUME_LSB x 0.125 - 116 dB (each step is 0.125 dB). LS_SUB_VOLUME_MSB Address: DEh Type: R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 LS_SUB_VOLUME_MSB[7:0] Bit Name LS_SUB_ VOLUME_MSB[7:0] Reset 1001 1000 Function LS 10 bits volume Subwoofer channel 8 MSB See Figure 20: Volume Control on page 38 for range values. 125/156 Register List LS_SUB_VOLUME_LSB Address: DFh Type: R/W Bit 7 0 Bit 6 0 Bit 5 0 Bit 4 0 Bit 3 0 Bit 2 0 Bit 1 STV82x7 Bit 0 LS_SUB_VOLUME_LSB[1:0] Bit Name Bits[7:2] LS_SUB_ VOLUME_LSB[1:0] Reset 000000 Reserved. 00 Function LS 10 bits volume Subwoofer channel 2 LSB See Figure 20: Volume Control on page 38 for range values. The volume value is defined by the following formula: Vol (dB) = Decimal value of LS_SUB_VOLUME_MSB x 0.5 + Decimal value of LS_SUB_VOLUME_LSB x 0.125 - 116 dB (each step is 0.125 dB). LS_SL_VOLUME_MSB Address: E0h Type: R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 LS_SL_VOLUME_MSB[7:0] Bit Name LS_SL_VOLUME_ MSB[7:0] Reset 1001 1000 Function LS 10 bits volume Left surround channel 8 MSB in independent mode or LS 10 bits Left and Right surround volume 8 MSB in differential mode. See Figure 20: Volume Control on page 38 or Figure 21: Differential Balance on page 39. 126/156 STV82x7 LS_SL_VOLUME_LSB Address: E1h Type: R/W Bit 7 0 Bit 6 0 Bit 5 0 Bit 4 0 Bit 3 0 Bit 2 0 Bit 1 Register List Bit 0 LS_LS_VOLUME_LSB[1:0] Bit Name Bits[7:2] LS_LS_VOLUME_ LSB[1:0] Reset 000000 Reserved. 00 Function LS 10 bits volume Left surround channel 2 LSB in independent mode or LS 10 bits Left and Right surround volume 2 LSB in differential mode. See Figure 20: Volume Control on page 38 or Figure 21: Differential Balance on page 39. The volume value is defined by the following formula: Vol (dB) = Decimal value of LS_SL_VOLUME_MSB x 0.5 + Decimal value of LS_SL_VOLUME_LSB x 0.125 - 116 dB (each step is 0.125 dB). LS_SR_VOLUME_MSB Address: E2h Type: R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 LS_SR_VOLUME_MSB[7:0] Bit Name LS_SR_VOLUME_ MSB[7:0] Reset Function 00000000 LS 10 bits volume Right channel 8 MSB in independent mode or LS 10 bits surround Left and Right balance 8 MSB in differential mode. See Figure 20: Volume Control on page 38 or Figure 21: Differential Balance on page 39. LS_SR_VOLUME_LSB Address: E3h Type: R/W Bit 7 0 Bit 6 0 Bit 5 0 Bit 4 0 Bit 3 0 Bit 2 0 Bit 1 Bit 0 LS_SR_VOLUME_LSB[1:0] Bit Name Bits[7:2] Reset 000000 Reserved. Function 127/156 Register List STV82x7 Bit Name LS_SR_VOLUME_ LSB[1:0] Reset 00 Function LS 10 bits volume Right channel 8 MSB in independent mode or LS 10 bits surround Left and Right balance 2 LSB in differential mode. See Figure 20: Volume Control on page 38 or Figure 21: Differential Balance on page 39. The volume value is defined by the following formula: Vol (dB) = Decimal value of LS_SR_VOLUME_MSB x 0.5 + Decimal value of LS_SR_VOLUME_LSB x 0.125 - 116 dB (each step is 0.125 dB). LS_MASTER_VOLUME_MSB Address: E4h Type: R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 LS_MASTER_VOLUME_MSB[7:0] Bit Name Reset Function LS_MASTER_ 1110100 LS 10 bits volume Master channel 8 MSB VOLUME_MSB[7:0] 0 See Figure 20: Volume Control on page 38 for range values. LS_MASTER_VOLUME_LSB Address: E5h Type: R/W Bit 7 0 Bit 6 0 Bit 5 0 Bit 4 0 Bit 3 0 Bit 2 0 Bit 1 Bit 0 LS_MASTER_VOLUME _LSB[1:0] Bit Name Bits[7:2] LS_MASTER_ VOLUME_LSB[1:0] Reset 000000 Reserved. 00 LS 10 bits volume Master channel 2 LSB Function See Figure 20: Volume Control on page 38 for range values. The volume value is defined by the following formula: Vol (dB) = Decimal value of LS_MASTER_VOLUME_MSB x 0.5 + Decimal value of LS_MASTER_VOLUME_LSB x 0.125 - 116 dB (each step is 0.125 dB). 128/156 STV82x7 HP_L_VOLUME_MSB Address: E6h Type: R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Register List Bit 0 HP_L_VOLUME_MSB[7:0] Bit Name HP_L_VOLUME_ MSB[7:0] Reset 1001 1000 Function HP 10 bits volume Left channel 8 MSB in independent mode or HP 10 bits Left and Right volume 8 MSB in differential mode. See Figure 20: Volume Control on page 38 or Figure 21: Differential Balance on page 39. HP_L_VOLUME_LSB Address: E7h Type: R/W Bit 7 0 Bit 6 0 Bit 5 0 Bit 4 0 Bit 3 0 Bit 2 0 Bit 1 Bit 0 HP_L_VOLUME_LSB[1:0] Bit Name Bits[7:2] HP_L_VOLUME_ LSB[1:0] Reset 000000 Reserved. 00 Function HP 10 bits volume Left channel 2 LSB in independent mode or HP 10 bits Left and Right volume 2 LSB in differential mode. See Figure 20: Volume Control on page 38 or Figure 21: Differential Balance on page 39. The volume value is defined by the following formula: Vol (dB) = Decimal value of HP_L_VOLUME_MSB x 0.5 + Decimal value of HP_L_VOLUME_LSB x 0.125 - 116 dB (each step is 0.125 dB). HP_R_VOLUME_MSB Address: E8h Type: R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 HP_R_VOLUME_MSB[7:0] Bit Name HP_R_VOLUME_ MSB[7:0] Reset Function 0000000 HP 10 bits volume Right channel 8 MSB in independent mode or HP 10 bits Left and Right balance 0 8 MSB in differential mode. See Figure 20: Volume Control on page 38 or Figure 21: Differential Balance on page 39. 129/156 Register List HP_R_VOLUME_LSB Address: E9h Type: R/W Bit 7 0 Bit 6 0 Bit 5 0 Bit 4 0 Bit 3 0 Bit 2 0 Bit 1 STV82x7 Bit 0 HP_R_VOLUME_LSB[1:0] Bit Name Bits[7:2] HP_R_VOLUME_ LSB[1:0] Reset 000000 Reserved. 00 Function HP 10 bits volume Right channel 2 LSB in independent mode or HP 10 bits Left and Right balance 2LSB in differential mode. See Figure 20: Volume Control on page 38 or Figure 21: Differential Balance on page 39. SCART_L_VOLUME_MSB Address: EAh Type: R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 SCART_L_VOLUME_MSB[7:0] Bit Name Reset Function SCART_L_ 1101110 1 SCART 10 bits volume Left channel 8 MSB in independent mode or SCART10 bits Left and Right VOLUME_MSB[7:0] volume 8 MSB in differential mode. See Figure 20: Volume Control on page 38 or Figure 21: Differential Balance on page 39. 130/156 STV82x7 SCART_L_VOLUME_LSB Address: EBh Type: R/W Bit 7 0 Bit 6 0 Bit 5 0 Bit 4 0 Bit 3 0 Bit 2 0 Bit 1 Register List Bit 0 SCART_L_VOLUME_LSB[1:0] Bit Name Bits[7:2] SCART_L_ VOLUME_LSB[1:0] Reset 000000 Reserved. 00 Function SCART 10 bits volume Left channel 2 LSB in independent mode or SCART10 bits Left and Right volume 2 LSB in differential mode. See Figure 20: Volume Control on page 38 or Figure 21: Differential Balance on page 39. The volume value is defined by the following formula: Vol (dB) = Decimal value of SCART_L_VOLUME_MSB x 0.5 + Decimal value of SCART_L_VOLUME_LSB x 0.125 116 dB (each step is 0.125 dB). SCART_R_VOLUME_MSB Address: ECh Type: R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 SCART_R_VOLUME_MSB[7:0] Bit Name Reset Function SCART_R_ 11011101 SCART 10 bits volume Right channel 8 MSB in independent mode or SCART10 bits Left and Right VOLUME_MSB[7:0] balance 8 MSB in differential mode. See Figure 20: Volume Control on page 38 or Figure 21: Differential Balance on page 39. SCART_R_VOLUME_LSB Address: EDh Type: R/W Bit 7 0 Bit 6 0 Bit 5 0 Bit 4 0 Bit 3 0 Bit 2 0 Bit 1 Bit 0 SCART_R_VOLUME_LSB[1:0] Bit Name Bits[7:2] Reset 000000 Reserved. Function 131/156 Register List STV82x7 Bit Name SCART_R_ VOLUME_LSB[1:0] Reset 00 Function SCART 10 bits volume Right channel 2 LSB in independent mode or SCART10 bits Left and Right balance 2 LSB in differential mode. See Figure 20: Volume Control on page 38 or Figure 21: Differential Balance on page 39. 12.19 Beeper BEEPER_ON Address: EEh Type: R/W Bit 7 0 Bit 6 0 Bit 5 0 Bit 4 0 Bit 3 0 Bit 2 0 Bit 1 0 Bit 0 BEEPER_ON Beeper Activation Register Bit Name Bits [7:1] BEEPER_ON Reset 0000000 Reserved. 0 Beeper Enable 0: Beeper muted (Default.) 1: Beeper enabled. Function BEEPER_MODE Address: EFh Type: R/W Bit 7 0 Bit 6 0 Bit 5 0 Beeper Control Register Bit 4 Bit 3 Bit 2 BEEPER_ PULSE Bit 1 Bit 0 BEEPER_DURATION BEEPER_PATH Bit Name Bits [7:5] BEEPER_ DURATION [4:3] BEEPER_PULSE Reset 000 00 0 Reserved. Function Define beeper duration when set to pulse mode. Set beeper pulse mode 0: Pulse mode selected. 1: Continuous mode selected. BEEPER_PATH [1:0] 11 Set the output channels when beeper is active 00: no channels. 01: Loudspeakers only. 10: Headphone only. 11: Loudspeakers and Headphone selected. 132/156 STV82x7 BEEPER_FREQ_VOL Address: F0h Type: R/W Bit 7 Bit 6 BEEP_FREQ[2:0] Bit 5 Bit 4 Bit 3 Bit 2 BEEP_VOL[4:0] Bit 1 Register List Beeper Frequency and Volume Settings Register Bit 0 Bit Name BEEP_FREQ[2:0] Reset 011 Function Defines the frequency of the beeper tone from 62.5 Hz to 8 kHz in octaves 000: 62.5 Hz 001: 125 Hz 010: 250 Hz 011: 500 Hz (Default) 100: 1 kHz 101: 2 kHz 110: 4 kHz 111: 8 kHz BEEP_VOL[4:0] 10000 Defines the Beeper volume from 0 to -93 dB in steps of 3 dB. 11111: 0 dB (1 VRMS) 11110: -3 dB 11101: -6 dB ... 10000: -48 dB (Default) ... 00011: -84 00010: -87 00001: -90 00000: -93 dB dB dB dB 12.20 Mute MUTE_DIGITAL Address: F1h Type: R/W Bit 7 AUTOSTD_ MUTE_ON Bit 6 0 Bit 5 0 Bit 4 SCART_ D_MUTE Bit 3 SRND_HP_D_ MUTE Bit 2 SUB_ D_MUTE Bit 1 C_ D_MUTE Bit 0 LS_ D_MUTE Bit Name AUTOSTD_MUTE_ON Bit s[6:5] 1 Reset Function 0: autostandard can not mute outputs 1: autostandard can mute outputs when no signal is detected 00 1 SCART left/right digital soft mute 0: signal un-muted 1: signal muted 1 LS Surround/HP left/right digital soft mute 0: signal un-muted 1: signal muted 1 LS Subwoofer digital soft mute 0: signal un-muted 1: signal muted SCART_D_MUTE SRND_HP_D_MUTE SUB_D_MUTE 133/156 Register List STV82x7 Bit Name 1 C_D_MUTE Reset LS Center digital soft mute 0: signal un-muted 1: signal muted 1 LS left/right digital soft mute 0: signal un-muted 1: signal muted Function LS_D_MUTE 12.21 S/PDIF S/PDIF_OUT_CONFIG Address: F2h Type: R/W Bit 7 0 Bit 6 0 Bit 5 0 Bit 4 0 Bit 3 0 Bit 2 S/PDIF_OUT_ MUTE Bit 1 Bit 0 S/PDIF Output Configuration Register S/PDIF_OUT_SELECT Bit Name Bits [7:3] S/PDIF_OUT_ MUTE Reset 00000 1 Reserved. S/PDIF Output Mute: 0: S/PDIF Output unmuted. 1: S/PDIF Output muted. 00 S/PDIF Output channel selection: 00: output SCART signal 01: output LS L-R signal 10: output C/SUB signal 11: ouptut Sur/HP signal Function S/PDIF_OUT_ SELECT[1:0] 12.22 Headphone Configuration HEADPHONE_CONFIG Address: F3h Type: R/W Bit 7 0 Bit 6 0 Bit 5 0 Bit 4 0 Bit 3 HP_FORCE Bit 2 HP_LS_ MUTE Bit 1 HP_DET_ ACTIVE Bit 0 HP_ DETECTED Headphone Configuration Register Bit Name Bits [7:4] Reset 0000 Reserved. Function 134/156 STV82x7 Register List Bit Name HP_FORCE HP_LS_MUTE 0 0 1 HP_DET_ACTIVE HP_DETECTED 0 Reset Function 1: force output of the HP signal (bypass surround) 0: when HP is detected and active, LS are not muted 1: when HP is detected and active, LS are muted 0: HP detection is not active 1: HP detection is active, when HP detected, Surround signal is bypassed and HP signal is output on HP 1: When a signal is detected on HP_DET pin (STATUS) 12.23 DAC Control DAC_CONTROL Address: F4h Type: R/W Bit 7 0 Bit 6 0 Bit 5 S/PDIF_MUX Bit 4 DAC_SCART_ MUTE Bit 3 DAC_SHP_ MUTE Bit 2 DAC_CSUB_ MUTE Bit 1 DAC_LSLR_ MUTE Bit 0 POWER_UP DAC Control Register Bit Name Bits [7:6] Reset 00 0 Reserved. Function redirect external or internal S/PDIF source to S/PDIF output : 0: internal S/PDIF 1: external S/PDIF S/PDIF_MUX 1 DAC_SCART_MUTE SCART left/right analog soft mute 0: signal un-muted 1: signal muted 1 DAC_SHP_MUTE Surround/HP left/right analog soft mute 0: signal un-muted 1: signal muted 1 DAC_CSUB_MUTE Center/Subwoofer analog soft mute 0: signal un-muted 1: signal muted 1 DAC_LSLR_MUTE LS left/right analog soft mute 0: signal un-muted 1: signal muted POWER_UP 1 0: DACs Power OFF 1: Power ON 135/156 Register List DAC_SW_CHANNELS Address: F5h Type: R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 STV82x7 DAC Switch Channels Register Bit 0 SUR_HP_SW C_SUB_SW LS_L_R_SW SCART_SW Bit Name Reset 00 HP/Surround DAC: 00: Left/Right channels non inverted 11: Left/Right channels inverted Center/SubDAC: Function SUR_HP_SW C_SUB_SW 00 00: Left/Right channels non inverted 11: Left/Right channels inverted LS Left-Right DAC: 00: Left/Right channels non inverted 11: Left/Right channels inverted 00 LS_L_R_SW 00 SCART_SW SCART DAC: 00: Left/Right channels non inverted 11: Left/Right channels inverted SPDIF_SW_CHANNELS Address: F6h Type: R/W Bit 7 0 Bit 6 0 Bit 5 0 SPDIF Switch Channels Register Bit 4 0 Bit 3 0 Bit 2 0 Bit 1 SPDIF_SW Bit 0 Bit Name Bits [7:2] Reset 000000 Reserved. SPDIF output: Function SPDIF_SW 00 00: Left/Right channels non inverted 11: Left/Right channels inverted SPDIF_CHANNEL_STATUS Address: F9h Type: R/W Bit 7 Bit 6 Bit 5 Bit 4 EMPHASIS Bit 3 Bit 2 COPYRIGHT Bit 1 NON_AUDIO Bit 0 PRO_CON CHANNEL_STATUS 136/156 STV82x7 Register List Bit Name Reset Channel status mode: Function CHANNEL_STATUS[7:6] 00 00: Mode zero other values: reserved Emphasis: according to IEC60958 specification Copyright: EMPHASIS[5:3] 000 COPYRIGHT 0 0: Asserted 1: Not asserted Non-audio: NON_AUDIO 0 0: Linear PCM 1: Non-audio signal Select Professional or Consumer modes: PRO_CON 0 0: Consumer 1: Professional 12.24 AutoStandard Coefficients Settings AUTOSTD_COEFF_CTRL Address: FBh Type: R/W Bit 7 0 Bit 6 0 Bit 5 0 Bit 4 0 Bit 3 0 Bit 2 0 Bit 1 Bit 0 AUTOSTD_COEFF_ CTRL[1:0] Bit Name Bits [7:2] Reset 000000 Reserved. Control the Demod filter coeff table settings Function AUTOSTD_COEFF 01 _CTRL[1:0] 00: No action 01: Init Coeffecients to ROM values 10: Update Coeffecients with I2C values (set to 0 by DSP to acknowledge) AUTOSTD_COEFF_INDEX_MSB Address: FCh Type: R/W Bit 7 0 Bit 6 0 Bit 5 0 Bit 4 0 Bit 3 0 Bit 2 0 Bit 1 0 Bit 0 AUTOSTD_ COEFF_ INDEX_MSB 137/156 Register List STV82x7 Bit Name Bits [7:2] AUTOSTD_COEFF _INDEX_MSB Reset 0000000 Reserved. 0 FIR Coefficients table index (MSB) Function AUTOSTD_COEFF_INDEX_LSB Address: FDh Type: R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 AUTOSTD_COEFF_INDEX_LSB[7:0] Bit Name AUTOSTD_COEFF _INDEX_LSB[7:0] Reset 0000 0000 FIR Coefficients table index (LSB) Function AUTOSTD_COEFF_VALUE Address: FEh Type: R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 AUTOSTD_COEFF_VALUE[7:0] Bit Name AUTOSTD_COEFF _VALUE[7:0] Reset 0000 0000 Reserved Function Note: These four registers (AUTOSTD_COEFF_CTRL, AUTOSTD_COEFF_INDEX_MSB, AUTOSTD_COEFF_INDEX_LSB and AUTOSTD_COEFF_VALUE) can be used to change parameter settings for the following parts of channel 1 or channel 2: - Channel carrier DCO frequency (register CARFQxx) - Channel filter coefficients (registers FIRxCx) - PLL baseband AM/FM demodulators proportional and integral coefficients (registers ACOEFFx or BCOEFFx) - Demodulator mode selection (register DEMOD_CTRL) - IF AGC control (AGC_CTRL) - Channel 2 symbol tracking loop parameters (register SCOEFF) - Zweiton control (register ZWT_CTRL) While keeping the AUTOSTANDARD function always active. New values for all parameters mentioned above are kept instead of the values automatically sent by the AUTOSTANDARD function. 138/156 STV82x7 Register List One application is for example to implement OVERMODULATION recovery mode for any sound standard supported by the device (B/G, I, M/N, DK1, DK2, or DK3). See Technical Note for instructions on how to update the coefficient table settings. PATCH_VERSION Address: FFh Type: R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PATCH_VERSION[7:0] Bit Name PATCH_VERSION[ 7:0] Reset 0000 0000 Function Indicate the patch version which has been loaded in the device (can be used to check if the patch has been correctly loaded) 139/156 Electrical Characteristics STV82x7 13 Electrical Characteristics Test Conditions: TOPER = 25° C, VCC_H = 8 V, VXX_18 = 1.8 V, VXX_33 = 3.3 V, Oscillator at 27 MHz, default register values for synthesizer, otherwise specified. 13.1 Absolute Maximum Ratings Parameter Analog and Digital 1.8 V Supply Voltage (V CC18_CLK1, VCC18_CLK2, VCC18_IF, VDD18, VDD18_CONV, VDD18_ADC) Analog and Digital 3.3 V Supply Voltage (V CC33_SC, V CC33_LS, V DD33_IO1, VDD33_IO2 , VDD33_CONV, VCC_NISO) Analog Supply High Voltage (VCC_H) Capacitor 100 pF discharged via 1.5 k Ω serial resistor (Human Body Model) Operating Ambient Temperature Storage Temperature 2.5 V Symbol VXX_18 Value Units VXX_33 HVCC VESD TOPER TSTG 4.0 8.8 4 0, +70 -55 to +150 V V kV °C °C 13.2 Thermal Data Parameter Junction-to-Ambient Thermal Resistance Symbol RthJA Value 42 Units °C/W 13.3 Power Supply Data Parameter Analog and Digital 1.8 V Supply Voltage (V CC18_CLK1, VCC18_CLK2, VCC18_IF, VDD18, V DD18_CONV, VDD18_ADC) Analog and Digital 3.3 V Supply Voltage (V CC33_SC, VCC33_LS, VDD33_IO1 , VDD33_IO2, VDD33_CONV, VCC_NISO) Analog Supply High Voltage (VCC_H) Current Consumption for Digital 1.8 V Supply (VCC18_CLK2, VDD18 , VDD18_CONV, VDD18_ADC ) Current Consumption for Digital 3.3 V Supply ( V DD33_IO1, V DD33_IO2) Current Consumption for Analog 1.8 V Supply (V CC18_CLK1, VCC18_IF) Current Consumption for Analog 3.3 V Supply (V CC33_SC, V CC33_LS, VDD33_CONV, VCC_NISO) Current Consumption for Analog Supply High Voltage (8 V) Total Power Dissipation 1.70 1.80 1.90 V Symbol VXX_18 Min. Typ. Max. Units VXX_33 HVCC IVDD18 IVDD33 IVCC18 IVCC33 IVCC_H PDTOT 3.13 7.6 3.30 8.0 230 10 50 65 4 780 3.47 8.4 280 12 60 78 7 965 V V mA mA mA mA mA mW 140/156 STV82x7 Electrical Characteristics 13.4 Crystal Oscillator Parameter Crystal Series Resonance Frequency (at C21 = C22 = 27 pF load capacitor) Frequency Tolerance at 25 °C Frequency Stability versus Temperature within a range from 0 to 70 °C Motional Capacitor Serial Resistance Shunt Capacitance -30 -30 Symbol fP DF/F P DF/FT C1 RS CS Min. Typ. 27 Max. Units MHz +30 +30 15 30 7 ppm ppm fF Ω pF 13.5 Analog Sound IF Signal Parameter SIF Frequency Flatness SIF Input Resistance SIF Input DC Level SIF Input Capacitance Symbol BANDSIF RINSIF DCINSIF CINSIF FM Carrier Test Conditions AGC_ERR at 0, frequency range from 4 to 7 MHz Min. Typ. 0.6 Max. 3 85 Units dB kΩ V pF 60 72 0.9 3 VSIFFM SIF Input Sensitivity SNR 40dB RMS unweighted, 20 Hz-15 kHz, Standard B/G 27 kHz FM Deviation,1 kHz FM50k (Standard) FM200k 350 µVPP ±15 Signal Lost, DK mode, FM prescale at 0 ±50 ±200 ±350 ±500 ±1 ±115 ±320 kHz ±560 ±700 ±5 ±120 kHz kHz DEVFM FM Maximum Deviation FM350k FM500k Standard (FM50k) DFSIFFM SIF Carrier Accuracy for FM Shifted Standard (FM50k with DCO compensation) NICAM mute, FAR_MODE is active, standard BG, 100 mVPP level for FM carrier RFM/QPSK AM Carrier Carrier Ratio FM/QPSK for NICAM System 40 dB VSIFAM SIF Input Sensitivity Unmodulated, -3 dB at output amplitude AGC_ERR at 21d Standard L, 54% AM Depth, 1 kHz Unmodulated, THD at 1%, 54% AM Depth, AGC_ERR at 0 THD at 1% 19 mVPP VMAX_SIFAM SIF Maximum Input Level DEVAM Modulation Depth for AM 1.3 0 100 VPP % 141/156 Electrical Characteristics STV82x7 Symbol D FSIFAM RAM/QPSK AGC AGCstep AGCdyn IF AGC Step Parameter SIF Carrier Accuracy for AM AM/QPSK Carrier Ratio for NICAM System Test Conditions Min. Typ. ±1 Max. ±5 36 Units kHz dB NICAM Mute, 100 mVPP AM carrier 1.4 Valid from step 21 to step 31 29 1.5 30 1.6 31 dB dB Relative maximum gain to step 0 13.6 SIF to I²S Output Path Characteristics Test Conditions: SIF amplitude = 10 mVpp, otherwise specified, I²S output. Symbol FM Demodulation BANDFM SNRFM THDFM SEPFM Parameter Test Conditions Min. Typ. Max. Units Frequency Response Signal to Noise Total Harmonic Distortion Stereo Channel Separation 20 Hz - 15 kHz RMS unweighted, 20 Hz-15k Hz, Standard B/G 27 kHz FM Deviation,1 kHz Standard B/G stereo A2, 27 kHz FM deviation, 1 kHz 66 ±0.7 dB dB 0.05 48 % dB NICAM Demodulation BANDNIC SNR NIC THDNIC Frequency Response Signal to Noise Total Harmonic Distortion 20 Hz - 15 kHz 200 Hz - 60 dBFS, trap filter 200 Hz RMS unweighted, 20 Hz-15 kHz, Standard B/G mono NICAM,1 kHz 74 0.04 ±0.2 dB dB % AM Demodulation BANDAM SNRAM THDAM Frequency Response Signal to Noise Total Harmonic Distortion 20 Hz - 15 kHz RMS unweighted 2 0 Hz-15 kHz, Standard L, 54% AM Depth, 1 kHz AGC: 13d 60 0.4 ±0.5 dB dB % 13.7 SCART to SCART Analog Path Characteristics Test Conditions: RloadMAX = 10kΩ, CloadMAX = 330pF, MONO_IN voltage = 0.5 VRMS Symbol Parameter Test Conditions Min. Typ. Max. Units Analog-to-Analog STEREO and MONO RINSCART ROUTSCART VDCINSCART SCART Input Resistance Output Resistance for SCARTs SCART Input DC Level 1.45 3.4 29 34 40 1.57 3.64 39 75 1.65 3.8 kΩ Ω V V VDCOUTSCART SCART Output DC Level 142/156 STV82x7 Electrical Characteristics Symbol Parameter Clipping input level from SCART input Test Conditions Min. 2.0 Typ. Max. Units VRMS VRMS CLIPSCART Clipping SCART At 1 kHz 1% THD Clipping input level from MONO_IN input THD from SCART input 1 VRMS, at 1 kHz 0.5 0.02 0.02 0.05 0.05 % % THDSCART THD SCART THD from MONO_IN input SCART input 0.25 VRMS, at 1 kHz 1 VRMS, 20 Hz to 20 kHz Bandwidth, RMS unweighted 0.25 VRMS, 20 Hz to 20 kHz Bandwidth, RMS unweighted 20 Hz to 20 kHz 20 Hz to 20 kHz 1 VRMS @ 1 kHz on ref signal, the other one grounded 82 90 dB SNRSCART Signal to Noise Ratio MONO_IN input Frequency Flatness SCART input MONO_IN input 82 -0.5 11.5 80 90 0 12 90 0.5 12.5 dB dB dB dB BANDSCART XTALKL/R XTALKIN Left/Right Crosstalk Audio Crosstalk from Input Channel n to 1 VRMS @ 1 kHz on ref signal, all Input Channel m other inputs grounded Audio Crosstalk from Output Channel n to Output Channel m 1 VRMS @ 1 kHz on reference output, signal on a single input, all other inputs grounded 80 90 dB XTALKOUT 80 90 dB 13.8 SCART and MONO IN to I²S Path Characteristics Test Conditions: Sampling Frequency = 32 kHz, Maximum MONO_IN voltage = 0.5 VRMS. Symbol Parameter THD from SCART input Test Conditions VIN = 2 VRMS at 1 kHz Min. Typ. 0.006 0.006 Max. 0.05 0.05 Units % % THDADC THD ADC THD from V = 0.5 VRMS at 1 kHz MONO_IN input IN SNRADC BANDADC XTALKADC Signal to Noise Ratio Frequency Flatness Left Right Crosstalk 20 to 15 kHz Bandwidth, RMS unweighted VIN = 200 mVRMS SCART input 20 Hz to 15 kHz at 1 kHz, VIN = 1 VRMS 62 ±0.5 95 dB dB dB 13.9 I2S to LS/HP/SUB/C Path Characteristics Test Conditions: Sampling Frequency = 32 kHz, LLOAD = 100 µH, CLOAD = 33 nF, RLOAD = 30 K Ω. Symbol ROUTDAC VDCOUTDAC Parameter Output Resistance for Main Outputs MAIN Output DC Level Test Conditions LS_L, LS_R, LS_SUB, LS_C, HP_LSS_R and HP_LSS_L pins Min. Typ. 90 Max. 140 1.8 Units Ω V 1.4 1.55 143/156 Electrical Characteristics STV82x7 Symbol THDDAC SNRDAC VOUTAMPDAC XTALKDAC Parameter Total Harmonic Distortion Signal to Noise Ratio MAIN Output Amplitude Left Right Crosstalk Test Conditions 90% Full-scale Range at 1 kHz 20 to 15 kHz Bandwidth, RMS unweighted, at -20 dB full range 100% Full-scale Range at 1 kHz at 1 kHz, -20 dBFS Min. Typ. Max. 0.06 Units % dB 75 800 87 900 1050 mVRMS dB 13.10 I²S to SCART Path Characteristics Test Conditions: Sampling Frequency = 32 kHz, CLOAD = 33nF on DAC SCART pins, DAC SCART prescale at -5.5 dB. Symbol THDDACSCART SNRDACSCART VODACSCART Parameter Total Harmonic Distortion Signal to Noise Ratio MAIN Output Amplitude Test Conditions 90% Full-scale Range at 1 kHz 20 Hz to 15 kHz Bandwidth unweighted, -20 dB Full Range 100% Full-scale Range at 1 kHz at 1 kHz, -20 dBFS Min. Typ. 0.08 Max. 0.12 Units % dB 73 1.75 80 2 2.25 VRMS dB XTALKDACSCART Left Right Crosstalk 13.11 MUTE Characteristics Symbol MUTE DAC MUTE SCART Parameter DAC Mute analog SCART Mute Test Conditions I2S to DAC at 1 kHz 2 VRMS @ 1 kHz on ref signal, all other inputs grounded Min. 90 81 Typ. Max. Units dB dB 13.12 Digital I/Os Characteristics Symbol V V IL Parameter Low Level Input Voltage High Level Input Voltage Input Current CLK_SEL Low Level Input Voltage CLK_SEL High Level Input Voltage Low Level Output Voltage High Level Output Voltage Test Conditions Except SDA, SCL and CLK_SEL, 3.3 V power supply Except SDA, SCL and CLK_SEL, 3.3 V power supply Min. Typ. Max. 0.5 Units V V IH 2.0 1 IIN VILCLK_SEL VIHCLK_SEL V V µA V 1.8 V power supply 0.3 1.8 V power supply S/PDIF_OUT, IRQ, BUS_EXP S/PDIF_OUT, IRQ, BUS_EXP 1.2 0.3 3.0 V V V OL OH 144/156 STV82x7 Electrical Characteristics 13.13 I²C Bus Characteristics Symbol SCL VIL VIH IIL fSCL tR tF CI SDA VIL VIH IIL tR tF VOL tF CL CI I²C Timing tLOW tHIGH tSU,DAT tHD,DAT tSU,STO tBUF tHD,STA tSU,STA Clock Low period Clock High period Data Set-up Time Data Hold Time Set-up Time from Clock High to Stop Start Set-up Time following a Stop Start Hold Time Start Set-up Time following Clock Low to High Transition 1.3 0.6 100 0 0.6 1.3 0.6 0.6 900 µs µs ns ns µs µs µs µs Low Level Input Voltage High Level Input Voltage Input Leakage Current Input Rise Time Input Fall Time Low Level Output Voltage Output Fall Time Load Capacitance Input Capacitance VIN = 0 to 5.0 V 1 V to 2 V 2 V to 1 V IOL = 3 mA 2 V to 1 V -0.3 2.3 -10 1.5 5.5 10 300 300 0.4 250 400 10 V V µA ns ns V ns pF pF Low Level Input Voltage High Level Input Voltage Input Leakage Current Clock Frequency Input Rise Time Input Fall Time Input Capacitance 1 V to 2 V 2 V to 1 V VIN = 0 to 5.0 V -0.3 2.3 -10 1.5 5.5 10 400 300 300 10 V V µA kHz ns ns pF Parameter Test Conditions Min. Typ Max. Unit 145/156 Electrical Characteristics Figure 34: I²C Bus Timing STV82x7 SDA t BUF t LOW t SU,DAT SCL t HD,STA tR t HD,DAT t HIGH tF t SU,STO SDA tSU,STA 13.14 I2S Bus Interface See timing for I2s on page 43. Symbol I²S Input VI2S_IL VI2S_IH ZI2S II2S_Leak tI2S_Su tI2S_Ho Input I2S Low Level Voltage Input I2S High Level Voltage Input I2S Impedance I2S Leakage Current I2S Input Setup Time before Rising Edge of Clock I2S Input Hold Time after Rising Edge of Clock I2S Left Right Strobe Input Frequency (I2S_DATA0 only) I2S Serial Clock Input Frequency (I2S_DATA0 only) I2S Left Right Strobe Input Frequency (I2S_DATA0,1 ,2) I2S Serial Clock Input Frequency (I2S_DATA0 ,1,2) I2S Serial Clock Input Ratio Deviation = ±250 ppm See Figure 35 -1 30 2 5 1 0.8 V V pF µA ns Parameter Test Conditions Min. Typ Max. Unit See Figure 35 100 ns fI2S_LR0 Deviation = ±250 ppm 8 48 kHz fI2S_SCL0 0.512 3.072 MHz fI2S_LR 32 48 kHz fI2S_SCL RI2S_SCL 2.048 0.9 3.072 1.1 MHz I2S Output (I2S_DATA0 only) VI2SOL VI2SOH fI2S_OLR Output I2S Low Level Voltage Output I2S High Level voltage I2S Left Right Strobe Output Frequency IOL = 2 mA IOH = 2 mA Deviation = ±250 ppm 2.4 8 48 0.4 V V kHz 146/156 STV82x7 Electrical Characteristics Symbol fI2S_OSCl RI2S_SCL tI2S_Del Parameter I2S Serial Clock Output Frequency I2S Serial Clock Output Ratio I2S Output Delay After Falling Edge of Clock Test Conditions Min. 0.512 0.9 Typ Max. 3.072 1.1 30 Unit MHz See Figure 35, CLOAD = 30 pF ns Figure 35: I²S Input Bus Timing I2S_SCLK tI2S_Su I2S_DATA tI2S_Su I2S_LR_CLK tI2S_Ho 147/156 Input/Output Groups STV82x7 14 Input/Output Groups Pin numbers apply to SDIP package only. VCC18_IF VCC_H VCC18_IF SIF_P73 50K 50K SC1_OUTL SC1_OUTR SC2_OUTL SC2_OUTR SC3_OUTL SC3_OUTR 1 2 5 6 18 19 50K GND_PSUB GND_PSUB VCC33_LS VCC33_LS LS_L SCR_FLT LS_C LS_L LS_R LS_SUB HP_LSS_L HP_LSS_R 25 26 27 28 29 30 31 32 150 MONO_IN 78 30K VREFA GND_PSUB GND 33_LS VCC18_IF VCC_H VCC18_IF SIF_N 74 REF SC1_IN_L SC1_IN_R SC2_IN_L SC2_IN_R SC3_IN_L SC3_IN_R SC4_IN_L SC4_IN_R 9 10 14 15 23 24 79 80 VREFA 7K5 22K5 GNDIF GND_PSUB 148/156 STV82x7 Input/Output Groups VCC33_LS VCC33_LS VB G (1.2 V) 10K VREFA 11 5K4 VB G 13 BAND-GAP=1.2 V 16K8 GND33_LS GND33_LS VDD33_I01 VDD33_I01 VDD33_I01 HP_DET ADR_SEL RST_N CLK_TST_CTRL 35 36 43 48 S/PDIF_OUT 45 VSS VSS VDD33_I02 VDD33_I02 VDD33_I01 BUS_EXD IRQ 68 69 S/PDIF_IN 44 VSS VSS 149/156 Input/Output Groups STV82x7 VDD33_I02 VDD18 I2S_PCM_CLK I2S_LR_CLK I2S_DATA0 I2S_DATA1 I2S_DATA2 60 61 62 63 64 CLK_SEL 51 VSS VSS VCC18_CLK1 XTALIN_CLKXTP 52 SCL SDA 35 40 GND18_CLK1 VCC18_CLK1 500K XTALOUT_CLKXTM VSS 53 GND18_CLK1 150/156 STV82x7 Input/Output Groups VDD33_I02 59 VCC18_CLK2 57 VCC18_CLK1 54 VDD33_I01 VDD18 46 38 42 50 66 VSS 37 41 47 49 58 67 GND18_CLK1 55 GND18_CLK2 56 GND_PSUB 21 70 151/156 Input/Output Groups STV82x7 VDD18_CONV VDD33_CONV VCC_NISO VCC33_LS VCC33_SC VCC_H VDD18_ADC VCC18_IF 34 22 20 16 7 3 71 76 GND18_IF 77 GNDPW_IF 75 VSS18_ADC 72 GND_PSUB 70 21 GND33_LS 17 GND_H 4 GND33_SC 8 GND_SA 12 VSS18_CONV 33 152/156 STV82x7 Package Mechanical Data 15 Package Mechanical Data Figure 36: 80-Pin Thin Plastic Quad Flat Package D D1 A1 A A2 b e E1 E L1 L h c Table 32: Package Mechanical Dimensions mm Dim. Min. A A1 A2 b C D D1 E E1 e K L L1 0° 0.45 0.05 1.35 0.22 0.09 16.00 14.00 16.00 14.00 0.65 3.5° 0.60 1.00 0.75° 0.75 0° 0.018 1.40 0.32 inches Max. 1.60 0.15 1.45 0.38 0.20 0.002 0.053 0.009 0.004 0.630 0.551 0.630 0.551 0.026 3.5° 0.024 0.039 0.75° 0.030 0.055 0.013 Typ. Min. Typ. Max. 0.063 0.006 0.057 0.015 0.008 153/156 STV82x7 Index A Analog-to-Digital Conversion ............................. 22 Audio Matrix Analog .......................................................... 41 Automatic Frequency Control ............................ 24 Automatic Gain Control ...................................... 22 Automatic Overmodulation Detection ................ 23 Automatic Standard Recognition System .... 23, 56 I I²C Address ........................................................ 50 I²C Protocol ........................................................ 50 I²S Interface ....................................................... 42 I2C ................................................................... 146 I2C Address ....................................................... 50 L Loudness Control Automatic ..................................................... 38 B Back-end Processing ......................................... 25 Bass-Treble Control ........................................... 37 Beeper ............................................................... 39 P Package Mechanical Data ............................... 153 Peak Detector .................................................... 23 Power Supply Management ............................... 47 C Clock Generator ................................................ 21 R D Demodulation .................................................... 23 Dolby Pro Logic II Decoder .................................... 30 Registers 5-Band Equalizer / Bass-Treble ..........116-117 Analog Control ............................................. 81 Audio Preprocessing and Selection ............. 92 Audio Processing ....................................... 105 Automatic Standard Recognition ................. 88 AutoStandard Coefficients Settings ........... 137 Beeper ....................................................... 132 Clocking 1 .................................................... 64 Clocking 2 .................................................... 83 DAC Control ............................................... 135 Demodulator ................................................ 66 Demodulator Channel 1 ............................... 69 Demodulator Channel 2 ............................... 73 DSP Control ................................................. 84 General Control ........................................... 62 Headphone Bass-Treble ............................ 119 Headphone Configuration .......................... 134 I²C Map ........................................................ 56 Matrixing .................................................... 100 Mute ........................................................... 133 NICAM ......................................................... 78 Stereo Mode ................................................ 80 Volume ....................................................... 122 E Electrical Characteristics ................................. 140 Absolute Maximum Ratings ....................... 140 Analog Sound IF Signal ............................. 141 Crystal Oscillator ........................................ 141 Digital I/Os ................................................. 144 I²C Bus ....................................................... 145 I2S to LS/HP/SW Path ............................... 143 I2S to SCART Path .................................... 144 MUTE Performance ................................... 144 SCART to LS/HP/SW Path ........................ 143 SCART to SCART Analog Path ................. 142 SIF to LS/HP/SCART Path ........................ 142 Supply Data ............................................... 140 Thermal Data ............................................. 140 Equalizer 5-Band Audio ............................................... 37 154/156 STV82x7 S SIF Signal Analog .......................................................... 22 Signal Processor Dedicated Digital .......................................... 25 Signal to Noise ................................................ 142 Smart Volume Control ....................................... 36 Soft Mute Control ............................................... 39 Software Information ......................................... 10 SRS TruBass ....................................................... 36 TruSurround ................................................. 35 WOW ........................................................... 35 SRS‚ TruSurround XT‰ ....................................... 35 ST Dynamic Bass .............................................. 37 ST OmniSurround .............................................. 30 ST WideSurround .............................................. 30 T Total Harmonic Distortion ................................ 142 V Volume/Balance Control .................................... 38 155/156 STV82x7 Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics All other names are the property of their respective owners © 2006 STMicroelectronics - All rights reserved STMicroelectronics GROUP OF COMPANIES Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan - Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America www.st.com 156/156