STV9410D

STV9410 CRT AND LCD SEMI-GRAPHIC DISPLAY PROCESSOR . . . . . . . . . . . . CMOS SINGLE CHIP CRT AND LCD DISPLAY PROCESSOR BUILT IN 6 KBYTE RAM 25 ROWS OR MORE OF 40 CHARACTERS CRT MODE : - ANALOG Y LUMINANCE OUTPUT OF 4BIT DAC - R,G,B DIGITAL COLOR OUTPUTS - FAST BLANKING OUTPUT FOR VIDEO SWITCH COMMAND - SYNCHRONIZATION INPUT AND OUTPUT - MASTER AND SLAVE SYNCHRONIZATION MODES LCD MODE : - 8 GREY LEVELS - 4 BIT DATA WITH CLOCK OUTPUT - 3 OUTPUTS FOR LCD DRIVERS SYNCHRONIZATION - CONTRAST ANALOG COMMAND WITH DAC OUTPUT 128 ALPHANUMERIC CODES AND 128 SEMI-GRAPHIC CODES IN INTERNAL ROM PARALLEL ATTRIBUTES THANKS TO 2 BYTE CODES 128 ALPHANUMERIC AND 96 SEMIGRAPHIC USER DEFINABLE CODES DOWN-LOADABLE IN RAM 3-WIRE ASYNCHRONOUS SERIAL MCU INTERFACE SQUARE WAVE OR LOGICAL PROGRAMMABLE OUTPUT FULLY PROGRAMMABLE WITH 7 16-BIT CONTROL REGISTERS 24-PIN SO OR 20-PIN DIP PACKAGES Using its 3-wire serial interface, working in both read and write mode to program 7 control registers and to access internal RAM, STV9410 is a highly flexible processor. The STV9410 provides the user an easy to use and cost effective solution to display alphanumeric and semigraphic Informationon CRT and LCD screens. DIP20 (Plastic Package) ORDER CODE : STV9410P DESCRIPTION STV9410 controller is a VLSI CMOS Display Processor. Time base generator, display control & refresh logic, interface for transparent MCU memory access, ROM character sets, memory to store display data & page codes and control registers are gathered on a single chip component packed in a short 20 DIP or SO plastic package. April 1996 SO24 (Plastic Micropackage) ORDER CODE : STV9410D 1/25 STV9410 PIN CONNECTIONS DIP20 CRT LCD SO24 CRT RESERVED LCD XTO XTI CKO POR 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 VDD SYNC IN VDD CKD FRAME LOAD DF 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 - RESERVED V DD CKD FRAME LOAD XTO XTI CKO VDD SYNC IN VSYNC C SYNC - VSYNC C SYNC NCS SDA SCK VREF VSSA VSS - POR I B G R D0 D1 NCS SDA SCK DF D0 D1 9410-01.EPS - 9410-02.EPS 9410-01.TBL I B G R D3 D2 V REF V SSA V SS RESERVED D3 D2 V EE Y VEE Y - RESERVED PIN DESCRIPTION Symbol CRT MODE XTO XTI CKO POR NCS SDA SCK VREF VSSA VSS Y R G B I C SYNC VSYNC SYNC IN VDD 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 O I O O I I/O I I S S O O O O O O O O I/O S Reserved Crystal oscillator output Crystal oscillator or clock input Clock output Programmable output port Serial interface selection Serial data input/output Serial interface clock input Reset input and ref supply of Y DAC Ref ground of Y DAC Ground Reserved Reserved Luminance output Red output Green output Blue output Fast blanking output Reserved Composite synchro output Vertical synchro output Synchro input +5v power supply Reserved Pin no DIP20 SO24 I/O Description 2/25 STV9410 PIN DESCRIPTION (continued) Symbol LCD MODE XTO XTI CKO POR NCS SDA SCK VREF VSSA VSS VEE D2 D3 D1 D0 DF LOAD FRAME CKD VDD 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 O I O O I I/O I I S S O O O O O O O O I/O S Reserved Crystal oscillator output Crystal oscillator or clock input Clock output Programmable output port Serial interface selection Serial data input/output Serial interface clock input Reset input and ref supply of contrast adjustment Ref ground of contrast adjustment Ground Reserved Reserved Constrast adjustment D2 Data output D3 Data output D1 Data output D0 Data output LCD polarity output Load output (line) Frame output Data Clock +5v power supply Reserved Pin n DIP20 o SO24 I/O Description BLOCK DIAGRAM XTI XTO CKO VDD PO R VREF S TV9410 CLOCK GENE RATOR CONTROL P ROCES SING DISPLAY LOGIC S YNC IN CRT MODE R, G, B C S YNC VSYNC I Y LCD MODE D2, D3 , D1 LOAD FRAME D0 TIME BASE DAC VEE DF CKD (SYNC IN) MCU INTERFACE 6K BYTE RAM 9410-03.EPS NCS SDA SCK VS S VS SA 3/25 9410-02.TBL STV9410 ABSOLUTE MAXIMUM RATINGS Symbol VDD* VIN* Toper Tstg Ptot Supply Voltage Input Voltage Operating Temperature Storage Temperature Power Dissipation Parameter Value -0.3, +7.0 -0.3, +7.0 0, +70 -40, +125 300 Unit V V o o C mW * with respect to VSS ELECTRICAL CHARACTERISTICS (VDD = 5V, VSS = 0V, Ta = 0 to + 70oC, fxtal = 8 to 10MHz, unless otherwise specified) Symbol VDD IDD INPUTS NCS, SDA, SCK, SYNC IN, XTI VIL VIH IIL CIN VREF Vrh Vrst RIN VSSA OUTPUTS SDA, CSYNC, VSYNC, R, G, B, I, SYNC IN, DF, XTO, CKO, POR VOL VOH Y Output voltage (VREF=5V, VSSA=0, IOUT=0) LI LD ZOUT Tp Integral linearity Differential linearity Output impedance Propagation time at VOUT 90% of V FINAL, C L=20pF, IOUT=0, VREF=5V, VSSA=0V 0.25 0.1 0.5 80 V V ns 9410-04.TBL Parameter Supply voltage Supply current * Min 4.75 - Typ 5.0 - Max 5.25 50 Unit V mA Input low voltage Input high voltage (except XTI) Input leakage current (except XTI) (0 < VIN < VDD) Input capacitance (except XTI) Voltage reference of DAC Reset level on VREF VREF to VSSA internal resistance Reference level of DAC 0 2 -10 1.5 0 0.4 0 10 - 0.8 VDD +10 VDD 0.4 1.0 VDD V V µA pF V V kΩ V Output low voltage (IOL = 1.6mA) Output high voltage (IOH = - 0.1mA ) 0 0.8 VDD - 0.4 VDD V V kΩ * no load on outputs 4/25 9410-03.TBL C STV9410 TIMINGS (VDD = 5V ±5%, VSS = 0V, Ta = 0 to + 70oC, fxtal = 8 to 10MHz, VIL = 0.8V, VIH = 2V, VOL = 0.4V, VOH = 2.4V, CL = 50pF, unless otherwise specified) Symbol Parameter Min Typ Max Unit SERIAL INTERFACE NCS, SCK, SDA (Figure 1) Tcsl Tsch Tscl fSCK Tsds Tsdh Tsdv Tsdx Tsdz Tread NCS low to SCK falling edge SCK pulse width high SCK pulse width low Serial Clock Frequency Set up time of SDA on SCK rising edge Hold time of SDA after SCK rising edge Access time in read mode Hold data in read mode Serial interface disable time Delay before Valid Data 2 0 50 20 20 50 0 80 80 4 ns ns ns MHz ns ns ns ns ns µs OSCILLATOR INPUT (XTI) (Figure 1) Twh T wl Fclk RESET (VREF) Tres Reset Low level pulse 2 µs Clock high level Clock low level Clock frequency 30 30 8 10 ns ns MHz OUTPUT SIGNALS SDA, CSYNC, VSYNC, R, G, B, I, SYNC IN, DF, XTO, CKO, POR (Figure 2) Tph,Tpl Tskew Propagation time Skew between R, G, B, I signals o CL = 30 pF CL = 100 pF 50 100 30 ns ns ns (VDD = 5V ±5%, VSS = 0V, Ta = 0 to + 70 C, fxtal = 8 to 10MHz, VOL = 0.2VDD, VOH = 0.8VDD, CL = 100pF, unless otherwise specified) LCD INTERFACE D0, D1, D2, D3, CKD, LOAD, DF, FRAME (Figure 3) tCYC tCH tCL tWLD tSU tDH tDF tSUF CKD Shift Clock Period CKD Clock High CKD Clock Low Load Pulse Width Data Set-up Time Data Hold Time DF Delay from Load Frame Set-up before Load 150 4 x Pxtal 150 150 150 150 150 100 ns ns ns ns ns ns ns 9410-05.TBL ns 5/25 STV9410 Figure 1 : Microcontroller Interface Timings NCS t csl t sch SCK t sds t scl t sdh A8 A9 A6 WRITE A7 t sdv D0 D1 t sdx D6 READ t sdz D7 9410-04.EPS 9410-06.EPS 9410-05.EPS t read SDA Figure 2 : Output Signals Delay versus Clock t wh XTI t pl t ph OUTPUT t skew OUTPUT t wl Figure 3 : LCD Interface Timings t CH CKD t CYC LOAD t SU D0, D1 D2, D3 t DF DF t SUF t DH t WLD t CL t CLD FRAME 6/25 STV9410 2. FUNCTIONAL DESCRIPTION STV9410 display processor operation is controlled by a host microcomputer via a 3-wire serial bus. It is fully programmable through seven internal read/write registers and performs all the display functions either for CRT screen or LCD passive matrix by generating pixels from data stored in its internal memory. In addition, the host microcomputer can have straightforward accesses to the on-chip 6 Kbytes RAM, even during the display operation. The following functions are integrated in the STV9410 : - Crystal oscillator, - Programmable timing generator, - Microcomputer 3-wire serial interface, - ROM character generatorincluding 128 alphanumeric and 128 semigraphic character sets, - 6 Kbytes on chip RAM to store character codes, user definable character sets, and any host microcomputer data, and in CRT mode : - Y output driven by a 4-bit DAC, - Programmable master or slave synchro modes, - R, G, B, I outputs, in LCD mode : - LCD interface for passive multiplexed matrix, - 7 grey levels plus black. 2.1 SERIAL INTERFACE This 3-wire serial interface can be used with any microcomputer. Data transfer is supported by hardware peripherals like SPI or UART and can be emulated with standard I/O port using software routine ( see application note ). NCS input enablestransfer on high to low transition and transfer stays enabled as long as NCS input remains at logical low level. NCS input disables transfer as soon as low to high transition occurs, whatever transfer state is, and transfer remains disabled as long as NCS input remains at logical high level. SCK input receives serial clock; it must be high at the beginning of the transfer; data is sampled on rising edge of SCK. SDA input (in write mode) receives data which must be stable at least tsds before and at least tsdh after SCK rising edge. In read mode, SDA receives address and read command (R/W bit) and then it switches from input state to output state to send data (see Data transfer and Application Note). Data Transfer in Write Mode The host MCU writes data into STV9410 registers or memory. The MCU sends first MSB address with R/W bit clear, it sends secondly LSB address followed by data byte(s). STV9410, then, internally increments received address, ready to store a second data byte if needed, and so on, as long as NCS remains low (see Figure 4). LSB are sent first. Data Transfer in Read Mode The host MCU reads data from STV9410 registers or memory. The MCU sends first MSB address with R/W bit set, it sends secondly LSB address, then SDA pin switches from input state to output state and provides data byte(s) at SCK MCU clock rate. Notice that a minimum delay is needed before sending the first SCK rising edge to sample the first data bit (at least 2µs). After each data byte STV9410 internally increments address and it sends next data at SCK frequency. SDA remains in output state as long as NCS remains low (see Figure 5). Address auto-incrementation allows host MCU to use 8, 16, 32-bit data words to optimize transfer rate. LSB are sent first. SCK max speed is 4MHz. 7/25 STV9410 Figure 4 : Serial Interface Write Mode NCS SCK SDA A8 A9 A10 A11 A12 A13 @ MSB W A0 A1 A2 A3 A4 A5 A6 A7 D0 D1 D2 D3 D4 D5 @ LSB Data byte 1 NCS SCK SDA D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 9410-07.EPS data byte n - 1 data byte n Figure 5 : Serial Interface Read Mode NCS 2µs min. SCK SDA A8 A9 A10 A11 A12 A13 @ MSB R A0 A1 A2 A3 A4 A5 A6 A7 D0 D1 D2 D3 D4 D5 @ LSB INPUT Data byte 1 OUTPUT SDA Pin NCS SCK SDA D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 data byte n - 1 data byte n OUTPUT INPUT 9410-08.EPS SDA Pin 8/25 STV9410 2.2. ADDRESSING SPACE STV9410 registers, RAM and ROM are mapped in a 12 kbytes addressing space. The mapping is the following : 0000 h 6144 RAM bytes 17FF h 1800 h 1FFF h 2000 h 24FF h 2500 h 27FF h 2800 h 2CFF h 2D00 h 2FEF h 2FF0 h 2FFF h Display memory DRCS Descriptor tables User memory HSYN 2FF5 2FF4 SU7 SU6 SU5 SU4 SU3 SU2 SU1 SU0 SD7 SD6 SD5 SD4 SD3 SD2 SD1 SD0 SU (7:0) : Synchro rising edge position SD (7:0) : Synchro falling edge position POR 2FF7 2FF6 VOE N7 : : : : N6 N5 N4 N3 N2 TE N1 PV N0 Empty Area 1280 slices ROM G0 Empty Area 1280 slices ROM G1 Empty Area Internal Registers VOE TE PV N (7:0) Video output enable Timer enable Port value Square wave period ADDR 2FF9 2FF8 P12 P11 P10 G12 G11 G10 P9 P8 P7 P6 A12 A11 A10 P (12:6) : Address of first descriptor of page to display G (12:10) : User definable graphic character set address A (12:10) : User definable alphanumeric character set address DISP 2FFB IMG GMG RMG BMG 2FFA FLE CCE IN1 IN2 HIC BR3 BR2 BR1 BR0 2.2.1 Register Set VERT 2FF1 2FF0 LCD ILC C/H V/P VSE HSE F (8:0) : : : : : : : LCD ILC F7 F6 C/H V/P VSE HSE F5 F4 F3 F2 F1 F8 F0 LCD/CRT mode Interlaced/non-interlaced Composite/horizontal synchro Vertical synchro/real time port Vertical synchro enable Horizontal synchro enable Number of scan line per frame IMG, GMG, : Margin value of I, G, R, B outputs RMG, BMG HIC : High contrast, forces black and white on outputs FLE : flashing enable CCE : Conceal enable IN1, IN0 : Fast blanking mode BR (3:0) : Luminosity adjustment on Y output CURS 2FFD 2FFC CEN CBL CUL C (12:1) : : : : CEN CBL CUL C8 C7 C6 C5 C12 C11 C10 C4 C3 C2 C9 C1 HORI 2FF3 2FF2 L5 L4 L3 MG2 MG1 MG0 L2 L1 L0 Cursor Cursor Cursor Cursor enable blinking underlining address MG (2:0) : Margin duration L (5:0) : Line duration 9/25 STV9410 2.2.2 Descriptor UNIFORM MSB LSB RTP FFB I C (2:0) SL (7:0) : : : : : 0 RTP FFB I C2 C1 C0 0000h Descriptor (Table 1) 0040h (for page 0) Descriptor (Table 2) 0080h (for page 0) Page 0 Row 1 2.2.4 Example of RAM Maping SL7 SL6 SL5 SL4 SL3 SL2 SL1 SL0 Real time port Field flyback Fast blanking Strip color (G, R, B) Number of scan line of the strip 64b 64b 80b 80b CHARACTER MSB LSB RTP DE ZY C (12:1) : : : : 1 C8 RTP DE C7 C6 ZY C5 C12 C11 C10 C4 C3 C2 C9 C1 07D8h 0800h 00A8h Code 0 to 39 Page 0 Row 2 Code 0 to 39 2 Kbyte Real time port Display enable Vertical zoom Address of first character to display ~ ~ Page 0 Row 24 Code 0 to 39 ~ ~ 80b 64b 64b 80b 80b ~ ~ Descriptor (Table 1) 2.2.3 Code Format ALPHANUM MSB (ODD) LSB (EVEN) 0 IV CHARACTER NUMBER DW DH FL FC2 FC1 FC0 (for page 1) Descriptor (Table 2) (for page 1) Page 1 Row 1 Code 0 to 39 Page 1 Row 2 Code 0 to 39 2 Kbyte CHARACTER NUMBER : lower than 80h in ROM from 80h to FFh in RAM IV : Inverted video DW : Double width DH : Double height FL : Flashing FC (2:0) : Foreground color (G, R, B) ~ ~ Page 1 Row 24 Code 0 to 39 ~ ~ 80b 10b 10b ~ ~ 1000h Alphanum Character 0 Alphanum Character 1 GRAPHIC MSB (ODD) LSB (EVEN) 1 CHARACTER NUMBER BC2 BC1 BC0 FL FC2 FC1 FC0 ~ ~ Alphanum Character 93 Page 0 Row 0 Code 0 to 39 Free 1400h Graphic Character 0 ~ ~ 10b 80b 4b 10b 10b ~ ~ 1 Kbyte CHARACTER NUMBER : lower than 80h in ROM from 80h to DFh in RAM BC (2:0) : Background color (G, R, B) FL : Flashing FC (2:0) : Foreground color (G, R, B) CONTROL MSB (ODD) LSB (EVEN) EOL IF, IB UL CC BC (2:0) HG FC (2:0) 10/25 : : : : : : : 1 1 1 1 EOL IF IB UL CC Graphic Character 1 ~ ~ Graphic Character 93 Page 1 Row 0 Code 0 to 39 Free ~ ~ 10b 80b 4b ~ ~ 1 Kbyte BC2 BC1 BC0 HG FC2 FC1 FC0 End of line Fast blanking foreground/background Underline Conceal Background color (G, R, B) Hold graphic Foreground color (G, R, B) 9410-09.EPS 17FFh STV9410 2.3 CLOCK AND TIMING GENERATOR The whole timing is derived from XTI input frequency which can be an external generator or a crystal signal thanks to XTO/XTI oscillator.This clock is also pixel frequency which can be chosen between 8MHz to 10MHz (pxlck). This clock is available on CKO pin. It should be use for the MCU, saving a crystal in the application. The active area of a video line is 320 pixels periods long (40 characters of 8 pixels wide). Number of lines per frame, margin width, line duration, leading and trailing edges of horizontal synchronizationare fully programmable in CRT mode using VERT, HORI, HSYN registers. A RESET, can be applied to STV9410 by pulling low VREF pin ( ≤ 0.4V). On RESET, default values are forced into configuration registers and video outputs are at low level. All unused bit of registers are always read as ”0”. Figure 6 : Vert Register Scan Lines Programmation 2FF1 2FF0 Nb of S can Lines LS B HEXA 2.3.1 Time Base Registers Vertical Time Base and Configuration Register (VERT) Internal address : 2FF1-2FF0 h RESET value :01-36 h (@ = RESET default configuration) 2FF1 h LCD ILC @ 0 0 2FF0 h @ LCD ILC C/H V/P VSE HSE F (8:0) F7 0 F6 0 C/H V/P VSE HSE 0 0 0 0 F5 1 F4 1 F3 0 F2 1 0 F1 1 F8 1 F0 0 : 1 LCD mode 0 CRT mode @ : 1 Interlaced scanning 0 non-interlaced scanning @ : 1 CSYNC is composite synchro 0 CSYNC is horizontal synchro @ : 1 VSYNC is vertical synchro 0 VSYNC is RTP bit of current descriptor @ : 1 enable vertical synchro with SYNC IN 0 disable @ : 1 enable horizontal synchro with SYNC IN 0 disable @ : scan line number per frame (@ 312) LCD ILC X X C/H X V/P VSE HSE X X X - F8 0 0 F7 0 0 F6 0 0 F5 0 0 F4 0 0 F3 0 0 F2 0 0 F1 0 0 F0 0 1 F(0:8) + 2 Not allowed 3 16 64 01 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 0 0 0 0 1 1 0 0 0 0 0 0 1 1 1 0 0 1 1 1 1 0 0 0 0 0 0 1 1 1 0 1 1 1 1 1 0 0 1 1 1 1 0 1 1 0 1 0 1 0 1 0 0 1 1 1 1 1 1 1 1 1 0 0 1 1 0 0 0 0 0 1 1 1 1 1 1 0 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 1 1 0 0 0 0 0 0 0 1 0 0 1 0 0 0 1 0E 3E 62 76 EE F8 04 100 120 240 250 262 263 05 310 312 313 320 480 512 513 34 36 37 3E DE FE FF 9410-10.EPS F[8:0] = Scan Line Number - 2 11/25 STV9410 Margin and Horizontal Time Base Register (HORI) Internal address : 2FF3-2FF2 h RESET value :03-3F h (@ = RESET default configuration) 2FF3 @ 2FF2 @ 0 0 0 0 0 L5 1 0 L4 1 0 L3 1 MG2 MG1 MG0 0 1 1 L2 1 L1 1 L0 1 Horizontal Synchronization Register (HSYN) Internal address : 2FF5-2FF4 h RESET value :E6-DC h (@ = RESET default configuration) 2FF5 @ 2FF4 @ SU7 SU6 SU5 SU4 SU3 SU2 SU1 SU0 1 1 1 0 0 1 1 0 SD7 SD6 SD5 SD4 SD3 SD2 SD1 SD0 1 1 0 1 0 1 0 0 MG(2:0) : Left and right margin duration (@ = 4µs)  MarginDuration  MG =  −1 8 pxlck   L(5:0) : Line duration (@= 64µs)  Line Duration  L=  −1  8 pxlck  SU(7:0) : SYNC rising edge position (@ = 57.75µs)  Rise Edge Position SU =  −1 2 pxlck   SD(7:0) : SYNC falling edge position (@= 53.25µs)  FallingEdge Position  SD =  −1 2 pxlck   Figure 7 : HSYN Register Synchro Pulse Programmation Qz = 8MHz REG Active area Register Value Duration Duration (µs) (nber of char.) HORI (L = 3F) 64µs 1µs 1µs 40µs 21µs 46µs 48µs 64 FIXED 1 HORI (MG = 0) 1 FIXED 40 RESULT 21 HSYN (SU = B7) 46 HSYN (SD = BF) 48 HSYN PULSE Positive Pulse HSYN (SU = BF) 48µs 46µs 48 HSYN (SD = B7) 46 9410-11.EPS HSYN PULSE Negative Pulse 12/25 STV9410 Figure 8 : Horizontal Synchronization Timing DESIGNATION PIXEL CLOCK START Y OUTPUT DAC output START ”HORT” MSB REG ”HORT” LSB REG ”HSYN” LSB REG ”HSYN” MSB REG HSYN PULSE 8pxlck Fixed = (MG +1) x 8 x pxlck = (L +1) x 8 x pxlck = (SD + 1) x 2 x pxlck = (SU + 1) x 2 x pxlck 9410-12.EPS TIMING DIAGRAM COMMENTS Crystal = 8MHz pxlck = 125ns 0 = origin 0 Start Margin Active Area (320 pixels) Margin End of line 0 Video Validation and Port Register (PORT) Internal address : 2FF7-2FF6 h RESET value :00-00 h (@ = RESET default configuration) 2FF7 @ 2FF6 @ VOE VOE 0 N7 0 0 N6 0 0 N5 0 0 N4 0 0 N3 0 0 N2 0 TE 0 N1 0 PV 0 N0 0 mode (CRT or LCD), be fulfiled : - SU ≠ SD SU + 1 SD + 1 < L and