STW10NK80Z

STP10NK80Z - STP10NK80ZFP STW10NK80Z N-CHANNEL 800V - 0.78Ω - 9A TO-220/TO-220FP/TO-247 Zener-Protected SuperMESH™Power MOSFET TYPE STP10NK80Z STP10NK80ZFP STW10NK80Z s s s s s s VDSS 800 V 800 V 800 V RDS(on) < 0.90 Ω < 0.90 Ω < 0.90 Ω ID 9A 9A 9A Pw 160 W 40 W 160 W 3 1 2 TYPICAL RDS(on) = 0.78 Ω EXTREMELY HIGH dv/dt CAPABILITY 100% AVALANCHE TESTED GATE CHARGE MINIMIZED VERY LOW INTRINSIC CAPACITANCES VERY GOOD MANUFACTURING REPEATIBILITY TO-220 TO-220FP 3 2 1 TO-247 DESCRIPTION The SuperMESH™ series is obtained through an extreme optimization of ST’s well established stripbased PowerMESH™ layout. In addition to pushing on-resistance significantly down, special care is taken to ensure a very good dv/dt capability for the most demanding applications. Such series complements ST full range of high voltage MOSFETs including revolutionary MDmesh™ products. INTERNAL SCHEMATIC DIAGRAM APPLICATIONS HIGH CURRENT, HIGH SPEED SWITCHING s SWITCH MODE POWER SUPPLIES s DC-AC CONVERTERS FOR WELDING, UPS AND MOTOR DRIVE s ORDERING INFORMATION SALES TYPE STP10NK80Z STP10NK80ZFP STW10NK80Z MARKING P10NK80Z P10NK80ZFP W10NK80Z PACKAGE TO-220 TO-220FP TO-247 PACKAGING TUBE TUBE TUBE February 2003 1/11 STP10NK80Z - STP10NK80ZFP - STW10NK80Z ABSOLUTE MAXIMUM RATINGS Symbol VDS VDGR VGS ID ID IDM ( ) PTOT VESD(G-S) dv/dt (1) VISO Tj Tstg Parameter STP10NK80Z Value STP10NK80ZFP STW10NK80Z Unit V V V 9 6 36 160 1.28 A A A W W/°C KV V/ns V °C °C Drain-source Voltage (VGS = 0) Drain-gate Voltage (RGS = 20 kΩ) Gate- source Voltage Drain Current (continuous) at TC = 25°C Drain Current (continuous) at TC = 100°C Drain Current (pulsed) Total Dissipation at TC = 25°C Derating Factor Gate source ESD(HBM-C=100pF, R=1.5KΩ) Peak Diode Recovery voltage slope Insulation Withstand Voltage (DC) Operating Junction Temperature Storage Temperature 9 6 36 160 1.28 800 800 ± 30 9 (*) 6 (*) 36 (*) 40 0.32 4 4.5 2500 -55 to 150 -55 to 150 ( ) Pulse width limited by safe operating area (1) ISD ≤9A, di/dt ≤200A/µs, VDD ≤ V(BR)DSS, Tj ≤ TJMAX. (*) Limited only by maximum temperature allowed THERMAL DATA TO-220 Rthj-case Rthj-amb Tl Thermal Resistance Junction-case Max Thermal Resistance Junction-ambient Max Maximum Lead Temperature For Soldering Purpose 0.78 62.5 300 TO-220FP 3.1 TO-247 0.78 50 °C/W °C/W °C AVALANCHE CHARACTERISTICS Symbol IAR EAS Parameter Avalanche Current, Repetitive or Not-Repetitive (pulse width limited by Tj max) Single Pulse Avalanche Energy (starting Tj = 25 °C, ID = IAR, VDD = 50 V) Max Value 9 290 Unit A mJ GATE-SOURCE ZENER DIODE Symbol BVGSO Parameter Gate-Source Breakdown Voltage Test Conditions Igs=± 1mA (Open Drain) Min. 30 Typ. Max. Unit V PROTECTION FEATURES OF GATE-TO-SOURCE ZENER DIODES The built-in back-to-back Zener diodes have specifically been designed to enhance not only the device’s ESD capability, but also to make them safely absorb possible voltage transients that may occasionally be applied from gate to source. In this respect the Zener voltage is appropriate to achieve an efficient and cost-effective intervention to protect the device’s integrity. These integrated Zener diodes thus avoid the usage of external components. 2/11 STP10NK80Z - STP10NK80ZFP - STW10NK80Z ELECTRICAL CHARACTERISTICS (TCASE =25°C UNLESS OTHERWISE SPECIFIED) ON/OFF Symbol V(BR)DSS IDSS IGSS VGS(th) RDS(on) Parameter Drain-source Breakdown Voltage Zero Gate Voltage Drain Current (VGS = 0) Gate-body Leakage Current (VDS = 0) Gate Threshold Voltage Static Drain-source On Resistance Test Conditions ID = 1 mA, VGS = 0 VDS = Max Rating VDS = Max Rating, TC = 125 °C VGS = ± 20V VDS = VGS, ID = 100µA VGS = 10V, ID = 4.5 A 3 3.75 0.78 Min. 800 1 50 ±10 4.5 0.9 Typ. Max. Unit V µA µA µA V Ω DYNAMIC Symbol gfs (1) Ciss Coss Crss Coss eq. (3) Parameter Forward Transconductance Input Capacitance Output Capacitance Reverse Transfer Capacitance Equivalent Output Capacitance Parameter Turn-on Delay Time Rise Time Total Gate Charge Gate-Source Charge Gate-Drain Charge Test Conditions VDS = 15 V, ID = 4.5 A VDS = 25V, f = 1 MHz, VGS = 0 Min. Typ. 9.6 2180 205 38 105 Max. Unit S pF pF pF pF VGS = 0V, VDS = 0V to 640V SWITCHING ON Symbol td(on) tr Qg Qgs Qgd Test Conditions VDD = 400 V, ID = 4.5 A RG = 4.7Ω VGS = 10 V (Resistive Load see, Figure 3) VDD = 640V, ID = 9 A, VGS = 10V Min. Typ. 30 20 72 12.5 37 101 Max. Unit ns ns nC nC nC SWITCHING OFF Symbol td(off) tf tr(Voff) tf tc Parameter Turn-off Delay Time Fall Time Off-voltage Rise Time Fall Time Cross-over Time Test Conditions VDD = 400 V, ID = 4.5 A RG = 4.7Ω VGS = 10 V (Resistive Load see, Figure 3) VDD = 640V, ID = 9 A, RG = 4.7Ω, VGS = 10V (Inductive Load see, Figure 5) Min. Typ. 65 17 13 10 25 Max. Unit ns ns ns ns ns SOURCE DRAIN DIODE Symbol ISD ISDM (2) VSD (1) trr Qrr IRRM Parameter Source-drain Current Source-drain Current (pulsed) Forward On Voltage Reverse Recovery Time Reverse Recovery Charge Reverse Recovery Current ISD = 9 A, VGS = 0 ISD = 9 A, di/dt = 100A/µs VDD = 45V, Tj = 150°C (see test circuit, Figure 5) 645 6.4 20 Test Conditions Min. Typ. Max. 9 36 1.6 Unit A A V ns µC A Note: 1. Pulsed: Pulse duration = 300 µs, duty cycle 1.5 %. 2. Pulse width limited by safe operating area. 3. Coss eq. is defined as a constant equivalent capacitance giving the same charging time as Coss when VDS increases from 0 to 80% VDSS. 3/11 STP10NK80Z - STP10NK80ZFP - STW10NK80Z Safe Operating Area For TO-220 Thermal Impedance For TO-220 Safe Operating Area For TO-220FP Thermal Impedance For TO-220FP Safe Operating Area For TO-247 Thermal Impedance For TO-247 4/11 STP10NK80Z - STP10NK80ZFP - STW10NK80Z Output Characteristics Transfer Characteristics Transconductance Static Drain-source On Resistance Gate Charge vs Gate-source Voltage Capacitance Variations 5/11 STP10NK80Z - STP10NK80ZFP - STW10NK80Z Normalized Gate Threshold Voltage vs Temp. Normalized On Resistance vs Temperature Source-drain Diode Forward Characteristics Normalized BVDSS vs Temperature Maximum Avalanche Energy vs Temperature 6/11 STP10NK80Z - STP10NK80ZFP - STW10NK80Z Fig. 1: Unclamped Inductive Load Test Circuit Fig. 2: Unclamped Inductive Waveform Fig. 3: Switching Times Test Circuit For Resistive Load Fig. 4: Gate Charge test Circuit Fig. 5: Test Circuit For Inductive Load Switching And Diode Recovery Times 7/11 STP10NK80Z - STP10NK80ZFP - STW10NK80Z TO-220 MECHANICAL DATA DIM. MIN. A C D D1 E F F1 F2 G G1 H2 L2 L4 L5 L6 L7 L9 DIA. 13.0 2.65 15.25 6.2 3.5 3.75 0.49 0.61 1.14 1.14 4.95 2.4 10.0 16.4 14.0 2.95 15.75 6.6 3.93 3.85 0.511 0.104 0.600 0.244 0.137 0.147 4.40 1.23 2.40 1.27 0.70 0.88 1.70 1.70 5.15 2.7 10.40 0.019 0.024 0.044 0.044 0.194 0.094 0.393 0.645 0.551 0.116 0.620 0.260 0.154 0.151 mm TYP. MAX. 4.60 1.32 2.72 MIN. 0.173 0.048 0.094 0.050 0.027 0.034 0.067 0.067 0.203 0.106 0.409 inch TYP. MAX. 0.181 0.051 0.107 A C D1 L2 D F1 G1 E Dia. L5 L7 L6 L4 P011C L9 8/11 F2 F G H2 STP10NK80Z - STP10NK80ZFP - STW10NK80Z TO-220FP MECHANICAL DATA mm. MIN. 4.4 2.5 2.5 0.45 0.75 1.15 1.15 4.95 2.4 10 16 28.6 9.8 2.9 15.9 9 3 30.6 10.6 3.6 16.4 9.3 3.2 1.126 .0385 0.114 0.626 0.354 0.118 TYP MAX. 4.6 2.7 2.75 0.7 1 1.5 1.5 5.2 2.7 10.4 MIN. 0.173 0.098 0.098 0.017 0.030 0.045 0.045 0.195 0.094 0.393 0.630 1.204 0.417 0.141 0.645 0.366 0.126 inch TYP. MAX. 0.181 0.106 0.108 0.027 0.039 0.067 0.067 0.204 0.106 0.409 DIM. A B D E F F1 F2 G G1 H L2 L3 L4 L5 L6 L7 Ø A B L3 L6 L7 ¯ F1 F D G1 H F2 L2 L5 E 123 L4 G 9/11 STP10NK80Z - STP10NK80ZFP - STW10NK80Z TO-247 MECHANICAL DATA mm. MIN. 4.85 2.20 0.40 1 3 2 2 3 10.90 15.45 19.85 3.70 18.50 14.20 34.60 5.50 2 5º 60º 3.55 3.65 0.14 3 0.07 5º 60º 0.143 14.80 0.56 1.36 0.21 0.11 15.75 20.15 4.30 0.60 0.78 0.14 0.72 0.58 2.40 3.40 0.07 0.11 0.43 0.62 0.79 0.17 TYP MAX. 5.15 2.60 0.80 1.40 MIN. 0.19 0.08 0.015 0.04 0.11 0.07 0.09 0.13 inch TYP. MAX. 0.20 0.10 0.03 0.05 DIM. A D E F F1 F2 F3 F4 G H L L1 L2 L3 L4 L5 M V V2 Dia 10/11 STP10NK80Z - STP10NK80ZFP - STW10NK80Z Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. © The ST logo is a registered trademark of STMicroelectronics © 2003 STMicroelectronics - Printed in Italy - All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - Canada - China - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan - Malaysia - Malta - Morocco Singapore - Spain - Sweden - Switzerland - United Kingdom - United States. © http://www.st.com 11/11