STW12NK80Z

N-CHANNEL 800V - 0.65Ω - 10.5A TO-247 Zener-Protected SuperMESH™Power MOSFET TYPE STW12NK80Z s s s s s s STW12NK80Z VDSS 800 V RDS(on) < 0.75 Ω ID 10.5 A Pw 190 W TYPICAL RDS(on) = 0.65 Ω EXTREMELY HIGH dv/dt CAPABILITY 100% AVALANCHE TESTED GATE CHARGE MINIMIZED VERY LOW INTRINSIC CAPACITANCES VERY GOOD MANUFACTURING REPEATIBILITY 3 2 1 TO-247 DESCRIPTION The SuperMESH™ series is obtained through an extreme optimization of ST’s well established stripbased PowerMESH™ layout. In addition to pushing on-resistance significantly down, special care is taken to ensure a very good dv/dt capability for the most demanding applications. Such series complements ST full range of high voltage MOSFETs including revolutionary MDmesh™ products. INTERNAL SCHEMATIC DIAGRAM APPLICATIONS s HIGH CURRENT, HIGH SPEED SWITCHING s IDEAL FOR OFF-LINE POWER SUPPLIES ORDERING INFORMATION SALES TYPE STW12NK80Z MARKING W12NK80Z PACKAGE TO-247 PACKAGING TUBE October 2002 1/9 STW12NK80Z ABSOLUTE MAXIMUM RATINGS Symbol VDS VDGR VGS ID ID IDM (l) PTOT VESD(G-S) dv/dt (1) Tj Tstg Parameter Drain-source Voltage (VGS = 0) Drain-gate Voltage (RGS = 20 kΩ) Gate- source Voltage Drain Current (continuous) at TC = 25°C Drain Current (continuous) at TC = 100°C Drain Current (pulsed) Total Dissipation at TC = 25°C Derating Factor Gate source ESD(HBM-C=100pF, R=1.5KΩ) Peak Diode Recovery voltage slope Operating Junction Temperature Storage Temperature Value 800 800 ± 30 10.5 6.6 42 190 1.51 6000 4.5 -55 to 150 Unit V V V A A A W W/°C V V/ns °C (l) Pulse width limited by safe operating area (1) I SD ≤10.5A, di/dt ≤200A/µs, V DD ≤ V (BR)DSS, Tj ≤ T JMAX. (*) Limited only by maximum temperature allowed THERMAL DATA Rthj-case Rthj-amb Tl Thermal Resistance Junction-case Max Thermal Resistance Junction-ambient Max Maximum Lead Temperature For Soldering Purpose 0.66 50 300 °C/W °C/W °C AVALANCHE CHARACTERISTICS Symbol IAR EAS Parameter Avalanche Current, Repetitive or Not-Repetitive (pulse width limited by Tj max) Single Pulse Avalanche Energy (starting Tj = 25 °C, ID = IAR, VDD = 50 V) Max Value 10.5 400 Unit A mJ GATE-SOURCE ZENER DIODE Symbol BVGSO Parameter Gate-Source Breakdown Voltage Test Conditions Igs=± 1mA (Open Drain) Min. 30 Typ. Max. Unit V PROTECTION FEATURES OF GATE-TO-SOURCE ZENER DIODES The built-in back-to-back Zener diodes have specifically been designed to enhance not only the device’s ESD capability, but also to make them safely absorb possible voltage transients that may occasionally be applied from gate to source. In this respect the Zener voltage is appropriate to achieve an efficient and cost-effective intervention to protect the device’s integrity. These integrated Zener diodes thus avoid the usage of external components. 2/9 STW12NK80Z ELECTRICAL CHARACTERISTICS (TCASE =25°C UNLESS OTHERWISE SPECIFIED) ON/OFF Symbol V(BR)DSS IDSS IGSS VGS(th) RDS(on) Parameter Drain-source Breakdown Voltage Zero Gate Voltage Drain Current (VGS = 0) Gate-body Leakage Current (VDS = 0) Gate Threshold Voltage Static Drain-source On Resistance Test Conditions ID = 1 mA, VGS = 0 VDS = Max Rating VDS = Max Rating, TC = 125 °C VGS = ± 20V VDS = VGS, ID = 100 µA VGS = 10V, ID = 5.25 A 3 3.75 0.65 Min. 800 1 50 ±10 4.5 0.75 Typ. Max. Unit V µA µA µA V Ω DYNAMIC Symbol gfs (1) Ciss Coss Crss Coss eq. (3) Parameter Forward Transconductance Input Capacitance Output Capacitance Reverse Transfer Capacitance Equivalent Output Capacitance Parameter Turn-on Delay Time Rise Time Total Gate Charge Gate-Source Charge Gate-Drain Charge Test Conditions VDS = 15 V, ID = 5.25 A VDS = 25V, f = 1 MHz, VGS = 0 Min. Typ. 12 2620 250 53 100 Max. Unit S pF pF pF pF VGS = 0V, VDS = 0V to 640V SWITCHING ON Symbol td(on) tr Qg Qgs Qgd Test Conditions VDD = 400 V, ID = 5.25 A RG = 4.7Ω VGS = 10 V (Resistive Load see, Figure 3) VDD = 640V, ID = 10.5 A, VGS = 10V Min. Typ. 30 18 87 14 44 Max. Unit ns ns nC nC nC SWITCHING OFF Symbol td(off) tf tr(Voff) tf tc Parameter Turn-off Delay Time Fall Time Off-voltage Rise Time Fall Time Cross-over Time Test Conditions VDD = 400 V, ID = 5.25 A RG = 4.7Ω VGS = 10 V (Resistive Load see, Figure 3) VDD = 640 V, ID = 10.5 A, RG = 4.7Ω, VGS = 10V (Inductive Load see, Figure 5) Min. Typ. 70 20 16 15 28 Max. Unit ns ns ns ns ns SOURCE DRAIN DIODE Symbol ISD ISDM (2) VSD (1) trr Qrr IRRM Parameter Source-drain Current Source-drain Current (pulsed) Forward On Voltage Reverse Recovery Time Reverse Recovery Charge Reverse Recovery Current ISD = 10.5 A, VGS = 0 ISD = 10.5 A, di/dt = 100A/µs VDD = 100 V, Tj = 150°C (see test circuit, Figure 5) 635 5.9 18.5 Test Conditions Min. Typ. Max. 10.5 42 1.6 Unit A A V ns µC A Note: 1. Pulsed: Pulse duration = 300 µs, duty cycle 1.5 %. 2. Pulse width limited by safe operating area. 3. Coss eq. is defined as a constant equivalent capacitance giving the same charging time as Coss when VDS increases from 0 to 80% VDSS. 3/9 STW12NK80Z Safe Operating Area For TO-247 Thermal Impedance For TO-247 Output Characteristics Transfer Characteristics Transconductance Static Drain-source On Resistance 4/9 STW12NK80Z Gate Charge vs Gate-source Voltage Capacitance Variations Normalized Gate Threshold Voltage vs Temp. Normalized On Resistance vs Temperature Source-drain Diode Forward Characteristics Normalized BVDSS vs Temperature 5/9 STW12NK80Z Maximum Avalanche Energy vs Temperature 6/9 STW12NK80Z Fig. 1: Unclamped Inductive Load Test Circuit Fig. 2: Unclamped Inductive Waveform Fig. 3: Switching Times Test Circuit For Resistive Load Fig. 4: Gate Charge test Circuit Fig. 5: Test Circuit For Inductive Load Switching And Diode Recovery Times 7/9 STW12NK80Z TO-247 MECHANICAL DATA mm. MIN. 4.85 2.20 0.40 1 3 2 2 3 10.90 15.45 19.85 3.70 18.50 14.20 34.60 5.50 2 5º 60º 3.55 3.65 0.14 3 0.07 5º 60º 0.143 14.80 0.56 1.36 0.21 0.11 15.75 20.15 4.30 0.60 0.78 0.14 0.72 0.58 2.40 3.40 0.07 0.11 0.43 0.62 0.79 0.17 TYP MAX. 5.15 2.60 0.80 1.40 MIN. 0.19 0.08 0.015 0.04 0.11 0.07 0.09 0.13 inch TYP. MAX. 0.20 0.10 0.03 0.05 DIM. A D E F F1 F2 F3 F4 G H L L1 L2 L3 L4 L5 M V V2 Dia 8/9 STW12NK80Z Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. © The ST logo is a registered trademark of STMicroelectronics © 2002 STMicroelectronics - Printed in Italy - All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - Canada - China - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan - Malaysia - Malta - Morocco Singapore - Spain - Sweden - Switzerland - United Kingdom - United States. © http://www.st.com 9/9