STW14NM50

STW14NM50 N-CHANNEL 550V @ Tjmax - 0.32Ω - 14A TO-247 MDmesh™ MOSFET Table 1: General Features TYPE VDSS (@Tjmax) RDS(on) ID 550 V < 0.35 Ω 14 A STW14NM50 ■ ■ ■ ■ ■ ■ Figure 1: Package TYPICAL RDS(on) = 0.32 Ω HIGH dv/dt AND AVALANCHE CAPABILITIES 100% AVALANCHE RATED LOW INPUT CAPACITANCE AND GATE CHARGE LOW GATE INPUT RESISTANCE TIGHT PROCESS CONTROL AND HIGH MANUFACTORING YIELDS DESCRIPTION The MDmesh™ is a new revolutionary MOSFET technology that associates the Multiple Drain process with the Company’s PowerMESH™ horizontal layout. The resulting product has an outstanding low on-resistance, impressively high dv/dt and excellent avalanche characteristics. The adoption of the Company’s proprierati strip technique yields overall dynamic performance that is significantly better than that of similar completition’s products. ) s ( ct c u d TO-247 e t le ) s t( o r P Figure 2: Internal Schematic Diagram o s b O - u d o APPLICATIONS The MDmesh™ family is very suitablr for increase the power density of high voltage converters allowing system miniaturization and higher efficiencies. r P e t e l o Table 2: Order Codes bs O SALES TYPE MARKING PACKAGE PACKAGING STW14NM50 W14NM50 TO-247 TUBE Rev. 5 July 2004 1/9 STW14NM50 Table 3: Absolute Maximum ratings Symbol VGS Parameter Gate- source Voltage Value Unit ±30 V ID Drain Current (continuous) at TC = 25°C 14 A ID Drain Current (continuous) at TC = 100°C 8.8 A IDM (1) Drain Current (pulsed) 56 A PTOT Total Dissipation at TC = 25°C 175 W Derating Factor 1.28 W/°C dv/dt Peak Diode Recovery voltage slope Tstg Storage Temperature Tj 6 V/ns –65 to 150 °C 150 °C Max. Operating Junction Temperature (•)Pulse width limited by safe operating area (*)Limited only by maximum temperature allowed (1)ISD ≤14A, di/dt ≤100A/µs, VDD ≤ V(BR)DSS, Tj ≤ TJMAX. Table 4: Thermal Data Rthj-case Thermal Resistance Junction-case Max Rthj-amb Thermal Resistance Junction-ambient Max 30 Maximum Lead Temperature For Soldering Purpose 300 Tl r P e t le Table 5: Avalanche Characteristics Symbol Parameter IAR Avalanche Current, Repetitive or Not-Repetitive (pulse width limited by Tj max) EAS Single Pulse Avalanche Energy (starting Tj = 25 °C, ID = IAR, VDD = 50 V) ) s ( ct uc 0.715 ) s t( od °C/W °C/W °C Max Value Unit 12 A 400 mJ so b O - ELECTRICAL CHARACTERISTICS (TCASE =25°C UNLESS OTHERWISE SPECIFIED) Table 6: On /Off Symbol Parameter du V(BR)DSS Drain-source Breakdown Voltage IDSS Zero Gate Voltage Drain Current (VGS = 0) o r P e t e l o VGS = ± 30 V VGS(th) Gate Threshold Voltage VDS = VGS, ID = 250 µA RDS(on Static Drain-source On Resistance VGS = 10 V, ID = 6 A s b O Min. Typ. Max. 500 3 Unit V VDS = Max Rating VDS = Max Rating, TC = 125°C Gate-body Leakage Current (VDS = 0) IGSS 2/9 Test Conditions ID = 250 µA, VGS = 0 1 10 µA µA ± 100 nA 4 5 V 0.32 0.35 Ω STW14NM50 ELECTRICAL CHARACTERISTICS (CONTINUED) Table 7: Dynamic Symbol gfs (1) Parameter Test Conditions Forward Transconductance VDS > ID(on) x RDS(on)max, ID = 6A Input Capacitance Output Capacitance Reverse Transfer Capacitance VDS = 25 V, f = 1 MHz, VGS = 0 Equivalent Output Capacitance Min. Typ. Max. Unit 5.2 S 1000 180 25 pF pF pF VGS = 0 V, VDS = 0 to 400 V 90 pF Gate Input Resistance f=1 MHz Gate DC Bias = 0 Test Signal Level = 20mV Open Drain 1.6 Ω td(on) tr td(off) tf Turn-on Delay Time Rise Time Turn-off-Delay Time Fall Time VDD = 250 V, ID = 6 A, RG = 4.7 Ω, VGS = 10 V (see Figure 15) 20 10 19 8 ns ns ns ns Qg Qgs Qgd Total Gate Charge Gate-Source Charge Gate-Drain Charge VDD = 400 V, ID = 12 A, VGS = 10 V (see Figure 18) 28 8 15 Ciss Coss Crss COSS eq (3). RG nC nC nC Max. Unit 14 56 A A 1.5 V c u d Table 8: Source Drain Diode Parameter ISD ISDM (2) Source-drain Current Source-drain Current (pulsed) VSD (1) Forward On Voltage ISD = 12 A, VGS = 0 Reverse Recovery Time Reverse Recovery Charge Reverse Recovery Current ISD = 12 A, di/dt = 100 A/µs VDD = 100V (see Figure 16) 270 2.23 16.5 ns µC A ISD = 12 A, di/dt = 100 A/µs VDD = 100V, Tj = 150°C (see Figure 16) 340 3 18 ns µC A IRRM trr Qrr IRRM Reverse Recovery Time Reverse Recovery Charge Reverse Recovery Current c u d (t s) Min. o r P Symbol trr Qrr Test Conditions o s b O - e t le Typ. ) s t( 38 (1) Pulsed: Pulse duration = 300 µs, duty cycle 1.5 %. (2) Pulse width limited by safe operating area. (3) Coss eq. is defined as a constant equivalent capacitance giving the same charging time as Coss when VDS increases from 0 to 80% VDSS. o r P e t e l o s b O 3/9 STW14NM50 Figure 3: Safe Operating Area Figure 6: Thermal Impedance Figure 4: Output Characteristics Figure 7: Transfer Characteristics c u d e t le Figure 5: Transconductance u d o ) s ( ct r P e t e l o s b O 4/9 ) s t( o r P o s b O - Figure 8: Static Drain-source On Resistance STW14NM50 Figure 9: Gate Charge vs Gate-source Voltage Figure 12: Capacitance Variations Figure 10: Normalized Gate Thereshold Voltage vs Temperature Figure 13: Normalized On Resistance vs Temperature c u d e t le ) s ( ct ) s t( o r P o s b O - Figure 11: Dource-Drain Diode Forward Characteristics u d o r P e t e l o s b O 5/9 STW14NM50 Figure 14: Unclamped Inductive Load Test Circuit Figure 17: Unclamped Inductive Wafeform Figure 15: Switching Times Test Circuit For Resistive Load Figure 18: Gate Charge Test Circuit c u d e t le ) s ( ct u d o r P e o s b O - Figure 16: Test Circuit For Inductive Load Switching and Diode Recovery Times t e l o s b O 6/9 o r P ) s t( STW14NM50 TO-247 MECHANICAL DATA mm. DIM. MIN. TYP inch MAX. MIN. TYP. MAX. A 4.85 5.15 0.19 0.20 A1 2.20 2.60 0.086 0.102 b 1.0 1.40 0.039 0.055 b1 2.0 2.40 0.079 0.094 0.134 b2 3.0 3.40 0.118 c 0.40 0.80 0.015 0.03 D 19.85 20.15 0.781 0.793 E 15.45 15.75 0.608 e 5.45 L 14.20 L1 3.70 L2 14.80 0.560 4.30 0.14 18.50 øP 3.55 øR 4.50 S 0.582 c u d 0.17 0.728 3.65 0.140 5.50 0.177 5.50 o r P ) s t( 0.143 0.216 0.216 e t le ) s ( ct 0.620 0.214 o s b O - u d o r P e t e l o s b O 7/9 STW14NM50 Table 9: Revision History Date Revision 05-July-2004 5 Description of Changes The document change from “PRELIMINARY” to “COMPLETE”. New Stylesheet. c u d e t le ) s ( ct u d o r P e t e l o s b O 8/9 o s b O - o r P ) s t( STW14NM50 c u d e t le ) s ( ct ) s t( o r P o s b O - u d o r P e t e l o Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. 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