STW16NB60
N-CHANNEL 600V - 0.3Ω - 16A TO-247 PowerMesh™ MOSFET
TYPE STW16NB60
s s s s s
VDSS 600V
RDS(on) < 0.35 Ω
ID 16 A
TYPICAL RDS(on) = 0.3Ω EXTREMELY HIGH dv/dt CAPABILITY 100% AVALANCHE TESTED VERY LOW INTRINSIC CAPACITANCES GATE CHARGE MINIMIZED
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3 2
DESCRIPTION Using the latest high voltage MESH OVERLAY™ process, STMicroelectronics has designed an advanced family of power MOSFETs with outstanding performances. The new patent pending strip layout coupled with the Company’s proprieraty edge termination structure, gives the lowest RDS(on) per area, exceptional avalanche and dv/dt capabilities and unrivalled gate charge and switching characteristics.
TO-247
INTERNAL SCHEMATIC DIAGRAM
APPLICATIONS SWITCH MODE POWER SUPPLIES (SMPS) s DC-AC CONVERTERS FOR WELDING EQUIPMENT AND UNINTERRUPTIBLE POWER SUPPLIES AND MOTOR DRIVE
s
ABSOLUTE MAXIMUM RATINGS
Symbol VDS VDGR VGS ID ID IDM ( ) PTOT dv/dt(1) Tstg Tj Parameter Drain-source Voltage (VGS = 0) Drain-gate Voltage (RGS = 20 kΩ) Gate- source Voltage Drain Current (continuos) at TC = 25°C Drain Current (continuos) at TC = 100°C Drain Current (pulsed) Total Dissipation at TC = 25°C Derating Factor Peak Diode Recovery voltage slope Storage Temperature Max. Operating Junction Temperature Value 600 600 ±30 16 10 64 220 1.76 4 –65 to 150 150
(1)ISD ≤16A, di/dt ≤100A/µs, VDD ≤ V(BR)DSS, T j ≤ T JMAX.
Unit V V V A A A W W/°C V/ns °C °C
(•)Pulse width limited by safe operating area
April 2003
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THERMAL DATA
Rthj-case Rthj-amb Tl Thermal Resistance Junction-case Max Thermal Resistance Junction-ambient Max Maximum Lead Temperature For Soldering Purpose 0.567 30 300 °C/W °C/W °C
AVALANCHE CHARACTERISTICS
Symbol IAR EAS Parameter Avalanche Current, Repetitive or Not-Repetitive (pulse width limited by Tj max) Single Pulse Avalanche Energy (starting Tj = 25 °C, ID = IAR, VDD = 50 V) Max Value 16 600 Unit A mJ
ELECTRICAL CHARACTERISTICS (TCASE = 25 °C UNLESS OTHERWISE SPECIFIED) OFF
Symbol V(BR)DSS IDSS IGSS Parameter Drain-source Breakdown Voltage Zero Gate Voltage Drain Current (VGS = 0) Gate-body Leakage Current (VDS = 0) Test Conditions ID = 250 µA, VGS = 0 VDS = Max Rating VDS = Max Rating, TC = 125 °C VGS = ±30V Min. 600 1 50 ±100 Typ. Max. Unit V µA µA nA
ON (1)
Symbol VGS(th) RDS(on) Parameter Gate Threshold Voltage Static Drain-source On Resistance Test Conditions VDS = VGS, ID = 250 µA VGS = 10V, ID = 8A Min. 3 Typ. 4 0.3 Max. 5 0.35 Unit V Ω
DYNAMIC
Symbol gfs Ciss Coss Crss Parameter Forward Transconductance Input Capacitance Output Capacitance Reverse Transfer Capacitance Test Conditions VDS > ID(on) x RDS(on)max, ID = 8A VDS = 25V, f = 1 MHz, VGS = 0 Min. Typ. 14.5 3300 465 45 Max. Unit S pF pF pF
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ELECTRICAL CHARACTERISTICS (CONTINUED) SWITCHING ON
Symbol td(on) tr Qg Qgs Qgd Parameter Turn-on Delay Time Rise Time Total Gate Charge Gate-Source Charge Gate-Drain Charge Test Conditions VDD = 300V, ID = 8 A RG = 4.7Ω, VGS = 10V (see test circuit, Figure 3) VDD = 480V, ID = 16 A, VGS = 10V, RG = 4.7Ω Min. Typ. 35 16 80 19.5 35 105 Max. Unit ns ns nC nC nC
SWITCHING OFF
Symbol tr(Voff) tf tc Parameter Off-voltage Rise Time Fall Time Cross-over Time Test Conditions VDD = 480V, ID = 16 A, RG = 4.7Ω, VGS = 10V (see test circuit, Figure 5) Min. Typ. 15 12 30 Max. Unit ns ns ns
SOURCE DRAIN DIODE
Symbol ISD ISDM (2) VSD (1) trr Qrr IRRM Parameter Source-drain Current Source-drain Current (pulsed) Forward On Voltage Reverse Recovery Time Reverse Recovery Charge Reverse Recovery Current ISD = 16 A, VGS = 0 ISD = 16 A, di/dt = 100 A/µs, VDD = 100V, Tj = 150°C (see test circuit, Figure 5) 800 11 27 Test Conditions Min. Typ. Max. 16 64 1.6 Unit A A V ns µC A
Note: 1. Pulsed: Pulse duration = 300 µs, duty cycle 1.5 %. 2. Pulse width limited by safe operating area.
Safe Operating Area
Thermal Impedance
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Output Characteristics Transfer Characteristics
Transconductance
Static Drain-source On Resistance
Gate Charge vs Gate-source Voltage
Capacitance Variations
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Normalized Gate Thereshold Voltage vs Temp. Normalized On Resistance vs Temperature
Source-drain Diode Forward Characteristics
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Fig. 1: Unclamped Inductive Load Test Circuit Fig. 2: Unclamped Inductive Waveform
Fig. 3: Switching Times Test Circuit For Resistive Load
Fig. 4: Gate Charge test Circuit
Fig. 5: Test Circuit For Inductive Load Switching And Diode Recovery Times
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TO-247 MECHANICAL DATA
mm. MIN. 4.85 2.20 0.40 1 3 2 2 3 10.90 15.45 19.85 3.70 18.50 14.20 34.60 5.50 2 5º 60º 3.55 3.65 0.14 3 0.07 5º 60º 0.143 14.80 0.56 1.36 0.21 0.11 15.75 20.15 4.30 0.60 0.78 0.14 0.72 0.58 2.40 3.40 0.07 0.11 0.43 0.62 0.79 0.17 TYP MAX. 5.15 2.60 0.80 1.40 MIN. 0.19 0.08 0.015 0.04 0.11 0.07 0.09 0.13 inch TYP. MAX. 0.20 0.10 0.03 0.05
DIM. A D E F F1 F2 F3 F4 G H L L1 L2 L3 L4 L5 M V V2 Dia
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Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specification mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a trademark of STMicroelectronics © 2000 STMicroelectronics – Printed in Italy – All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - China - Finland - France - Germany - Hong Kong - India - Italy - Japan - Malaysia - Malta - Morocco Singapore - Spain - Sweden - Switzerland - United Kingdom - U.S.A. http://www.st.com
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