STW20N90K5

STW20N90K5 Datasheet N-channel 900 V, 0.21 Ω typ., 20 A MDmesh™ K5 Power MOSFET in a TO‑247 package Features 2 1 3 TO-247 Order code VDS RDS(on ) max. ID STW20N90K5 900 V 0.25 Ω 20 A • Industry’s lowest RDS(on) x area • • • • Industry’s best FoM (figure of merit) Ultra-low gate charge 100% avalanche tested Zener-protected D(2, TAB) Applications • G(1) Switching applications Description S(3) AM01475V1 This very high voltage N-channel Power MOSFET is designed using MDmesh™ K5 technology based on an innovative proprietary vertical structure. The result is a dramatic reduction in on-resistance and ultra-low gate charge for applications requiring superior power density and high efficiency. Product status link STW20N90K5 Product summary Order code STW20N90K5 Marking 20N90K5 Package TO-247 Packing Tube DS11570 - Rev 3 - October 2018 For further information contact your local STMicroelectronics sales office. www.st.com STW20N90K5 Electrical ratings 1 Electrical ratings Table 1. Absolute maximum ratings Symbol Value Unit Gate-source voltage ±30 V ID Drain current (continuous) at TC = 25 °C 20 A ID Drain current (continuous) at TC = 100 °C 13 A ID (1) Drain current (pulsed) 80 A PTOT Total dissipation at TC = 25 °C 250 W dv/dt (2) Peak diode recovery voltage slope 4.5 dv/dt (3) MOSFET dv/dt ruggedness 50 VGS Tj Tstg Parameter Operating junction temperature range Storage temperature range V/ns -55 to 150 °C Value Unit 1. Pulse width limited by safe operating area 2. ISD ≤ 20 A, di/dt ≤ 100 A/μs; VDS peak ≤ V(BR)DSS, VDD= 450 V 3. VDS ≤ 720 V Table 2. Thermal data Symbol Parameter Rthj-case Thermal resistance junction-case 0.5 °C/W Rthj-amb Thermal resistance junction-ambient 50 °C/W Value Unit Table 3. Avalanche characteristics Symbol DS11570 - Rev 3 Parameter IAR Avalanche current, repetitive or not repetitive (pulse width limited by Tjmax) 6.5 A EAS Single pulse avalanche energy (starting Tj = 25 °C, ID = IAR, VDD = 50 V) 500 mJ page 2/13 STW20N90K5 Electrical characteristics 2 Electrical characteristics TC = 25 °C unless otherwise specified Table 4. On/off-state Symbol Parameter Test conditions Min. V(BR)DSS Drain-source breakdown voltage VGS = 0 V, ID = 1 mA 900 Typ. IDSS 1 µA 50 µA ±10 µA 4 5 V 0.21 0.25 Ω Min. Typ. Max. Unit - 1500 - pF - 120 - pF - 1 - pF - 78 - pF 220 - pF VGS = 0 V, VDS = 900 V TC = 125 °C (1) IGSS Gate body leakage current VDS = 0 V, VGS = ±20 V VGS(th) Gate threshold voltage VDS = VGS, ID = 100 µA RDS(on) Static drain-source on-resistance VGS = 10 V, ID = 10 A Unit V VGS = 0 V, VDS = 900 V Zero gate voltage drain current Max. 3 1. Defined by design, not subject to production test Table 5. Dynamic Symbol Ciss Parameter Input capacitance Coss Output capacitance Crss Reverse transfer capacitance Co(er) (1) Co(tr) (2) Test conditions Equivalent capacitance energy related Equivalent capacitance time related VDS = 100 V, f = 1 MHz, VGS = 0 V VGS = 0 V, VDS = 0 to 720 V Rg Intrinsic gate resistance f = 1 MHz , ID = 0 A - 3.7 - Ω Qg Total gate charge VDD = 720 V, ID = 20 A - 40 - nC Qgs Gate-source charge - 14 - nC Qgd Gate-drain charge VGS= 0 to 10 V (see Figure 14. Test circuit for gate charge behavior) - 17 - nC 1. Co(er) is a constant capacitance value that gives the same stored energy as Coss while VDS is rising from 0 to 80% VDSS. 2. Co(tr) is a constant capacitance value that gives the same charging time as Coss while VDS is rising from 0 to 80% VDSS. Table 6. Switching times Symbol td(on) tr td(off) tf DS11570 - Rev 3 Parameter Test conditions Turn-on delay time Rise time Turn-off delay time Fall time Min. Typ. Max. Unit VDD= 450 V, ID = 10 A, - 20.2 - ns RG = 4.7 Ω, VGS = 10 V (see Figure 13. Test circuit for resistive load switching times and Figure 18. Switching time waveform) - 13.5 - ns - 64.7 - ns - 16 - ns page 3/13 STW20N90K5 Electrical characteristics Table 7. Source-drain diode Symbol ISD ISDM (1) (2) Parameter Test conditions Min. Typ. Max. Unit Source-drain current - 20 A Source-drain current (pulsed) - 80 A 1.5 V Forward on voltage ISD = 20 A, VGS = 0 V - trr Reverse recovery time ISD = 20 A, di/dt = 100 A/µs, - 517 ns Qrr Reverse recovery charge - 11.4 µC IRRM Reverse recovery current VDD = 60 V (see Figure 15. Test circuit for inductive load switching and diode recovery times) - 44 A VSD trr Reverse recovery time ISD = 20 A, di/dt = 100 A/µs - 674 ns Qrr Reverse recovery charge - 14 µC IRRM Reverse recovery current VDD = 60 V, Tj = 150 °C (see Figure 15. Test circuit for inductive load switching and diode recovery times) - 41.6 A Min Typ Max. Unit 30 - - V 1. Pulse width limited by safe operating area 2. Pulsed: pulse duration = 300 µs, duty cycle 1.5% Table 8. Gate-source Zener diode Symbol V(BR) GSO Parameter Test conditions Gate-source breakdown voltage IGS = ± 1 mA, ID = 0 A The built-in back-to-back Zener diodes are specifically designed to enhance the ESD performance of the device. The Zener voltage facilitates efficient and cost-effective device integrity protection, thus eliminating the need for additional external componentry. DS11570 - Rev 3 page 4/13 STW20N90K5 Electrical characteristics curves 2.1 Electrical characteristics curves Figure 2. Thermal impedance Figure 1. Safe operating area ID (A) GIPG291120161130SOA t p =10 µs t p =100 µs 10 1 t p =1 ms Operation in this area is limited by R DS(on) t p =10 ms 10 0 10 -1 10 -1 T j ≤150 °C T c = 25°C single pulse 10 0 10 1 10 2 V DS (V) Figure 3. Output characteristics ID (A) GIPG291120161015OCH V GS =10, 11 V 50 40 GIPG291120161014TCH V DS = 20 V 40 V GS =9 V 30 V GS =8 V 20 10 20 10 V GS =7 V V GS =6 V 4 8 12 16 V DS (V) Figure 5. Normalized V(BR)DSS vs temperature V (BR)DSS (norm.) 1.12 ID (A) 50 30 0 0 Figure 4. Transfer characteristics GIPG291120161015BDV 0 5 1.08 7 8 9 10 V GS (V) Figure 6. Static drain-source on-resistance R DS(on) (Ω) 0.23 I D = 1 mA 6 GIPG291120161014RID V GS =10 V 0.22 1.04 0.21 1.00 0.20 0.96 0.19 0.92 0.88 -50 DS11570 - Rev 3 0 50 100 T j (°C) 0.18 0 5 10 15 I D (A) page 5/13 STW20N90K5 Electrical characteristics curves Figure 7. Gate charge vs gate-source voltage V GS (V) GIPG291120161013QVG V DS (V) V DS 14 600 10 500 8 400 6 300 4 200 2 100 0 0 10 20 30 40 0 Q g (nC) Figure 9. Normalized gate threshold voltage vs temperature V GS(th) (norm.) GIPG291120161016VTH GIPG291120161011CVR 10 4 C ISS 10 3 10 2 C OSS f = 1 MHz 10 1 C RSS 10 0 10 -1 10 0 10 1 10 2 V DS (V) Figure 10. Normalized on-resistance vs temperature R DS(on) (norm.) GIPG291120161017RON 2.6 I D = 100 µA 1.2 C (pF) 700 V DD = 720 V I D = 20 A 12 Figure 8. Capacitance variation V GS = 10 V 2.2 1.0 1.8 0.8 1.4 0.6 1.0 0.4 0.6 0.2 -50 0 50 100 T j (°C) Figure 11. Maximum avalanche energy vs. starting TJ E AS (mJ) GIPG291120161018EAS 0.2 -50 0 50 100 T j (°C) Figure 12. Source-drain diode forward characteristics VSD (V) GIPD280920181027SDF 1.1 500 1 Single pulse I D = 6.5 A V DD = 50 V 400 300 0.8 0.7 200 Tj = -50 °C 0.9 Tj = 25 °C Tj = 150 °C 0.6 100 0 -50 -25 DS11570 - Rev 3 0.5 0 25 50 75 100 125 T J (°C) 0.4 5 10 15 ISD (A) page 6/13 STW20N90K5 Test circuits 3 Test circuits Figure 13. Test circuit for resistive load switching times Figure 14. Test circuit for gate charge behavior VDD RL RL 2200 + μF 3.3 μF VDD VD RG VGS IG= CONST VGS + pulse width D.U.T. 2.7 kΩ 2200 μF pulse width D.U.T. 100 Ω VG 47 kΩ 1 kΩ AM01469v10 AM01468v1 Figure 15. Test circuit for inductive load switching and diode recovery times D G A D.U.T. S 25 Ω A L A VD 100 µH fast diode B B B 3.3 µF D G + Figure 16. Unclamped inductive load test circuit RG 1000 + µF 2200 + µF VDD 3.3 µF VDD ID D.U.T. S D.U.T. Vi _ pulse width AM01471v1 AM01470v1 Figure 18. Switching time waveform Figure 17. Unclamped inductive waveform ton V(BR)DSS td(on) toff td(off) tr tf VD 90% 90% IDM VDD 10% 0 ID VDD AM01472v1 VGS 0 VDS 10% 90% 10% AM01473v1 DS11570 - Rev 3 page 7/13 STW20N90K5 Package information 4 Package information In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. DS11570 - Rev 3 page 8/13 STW20N90K5 TO-247 package information 4.1 TO-247 package information Figure 19. TO-247 package outline 0075325_9 DS11570 - Rev 3 page 9/13 STW20N90K5 TO-247 package information Table 9. TO-247 package mechanical data Dim. mm Min. Max. A 4.85 5.15 A1 2.20 2.60 b 1.0 1.40 b1 2.0 2.40 b2 3.0 3.40 c 0.40 0.80 D 19.85 20.15 E 15.45 15.75 e 5.30 L 14.20 14.80 L1 3.70 4.30 L2 DS11570 - Rev 3 Typ. 5.45 5.60 18.50 ØP 3.55 3.65 ØR 4.50 5.50 S 5.30 5.50 5.70 page 10/13 STW20N90K5 Revision history Table 10. Document revision history Date Revision 19-May-2016 1 Changes First release. Modified: title and RDS(on) value in cover page Modified: Table 5. Avalanche characteristics Table 6. On/off-state, Table 7. Dynamic, Table 8. Switching times and Table 9. Source-drain diode 01-Dec-2016 2 Added Section 2.1 Electrical characteristics curves Modified: Section 3 Test circuits Datasheet promoted from preliminary data to production data Minor text changes Removed maturity status indication from cover page. 01-Oct-2018 3 Updated Figure 12. Source-drain diode forward characteristics. Minor text changes. DS11570 - Rev 3 page 11/13 STW20N90K5 Contents Contents 1 Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2 2 Electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2.1 Electrical characteristics (curves) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3 Test circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 4 Package information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 4.1 TO-247 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 DS11570 - Rev 3 page 12/13 STW20N90K5 IMPORTANT NOTICE – PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement. Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers’ products. No license, express or implied, to any intellectual property right is granted by ST herein. Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners. Information in this document supersedes and replaces information previously supplied in any prior versions of this document. © 2018 STMicroelectronics – All rights reserved DS11570 - Rev 3 page 13/13