STW21N150K5

STW21N150K5 N-channel 1500 V, 0.7 Ω typ.,14 A MDmesh™ K5 Power MOSFET in a TO-247 package Datasheet - production data Features Order code VDS RDS(on) max. ID PTOT STW21N150K5 1500 V 0.9 Ω 14 A 446 W      3 2 1 TO-247 Industry’s lowest RDS(on) * area Industry’s best figure of merit (FoM) Ultra low gate charge 100% avalanche tested Zener-protected Applications  Figure 1: Internal schematic diagram Switching applications Description This very high voltage N-channel Power MOSFET is designed using MDmesh™ K5 technology based on an innovative proprietary vertical structure. The result is a dramatic reduction in on-resistance and ultra-low gate charge for applications requiring superior power density and high efficiency. Table 1: Device summary Order code Marking Package Packing STW21N150K5 21N150K5 TO-247 Tube October 2015 DocID026818 Rev 3 This is information on a product in full production. 1/12 www.st.com Contents STW21N150K5 Contents 1 Electrical ratings ............................................................................. 3 2 Electrical characteristics ................................................................ 4 2.1 Electrical characteristics (curves) ...................................................... 6 3 Test circuits ..................................................................................... 8 4 Package information ....................................................................... 9 4.1 5 2/12 TO-247 package information ............................................................. 9 Revision history ............................................................................ 11 DocID026818 Rev 3 STW21N150K5 1 Electrical ratings Electrical ratings Table 2: Absolute maximum ratings Symbol VGS Parameter Gate-source voltage Value Unit ± 30 V ID Drain current at TC = 25 °C 14 A ID Drain current at TC = 100 °C 8.7 A IDM(1) Drain current (pulsed) 56 A PTOT Total dissipation at TC = 25 °C 446 W dv/dt (2) Peak diode recovery voltage slope 4.5 V/ns dv/dt (3) MOSFET dv/dt ruggedness 50 V/ns - 55 to 150 °C Value Unit Tj Operating junction temperature Tstg Storage temperature Notes: (1)Pulse (2)I SD (3)V width limited by safe operating area ≤ 14 A, di/dt ≤ 100 A/µs, VPeak ≤ V(BR)DSS DS ≤ 1200 V Table 3: Thermal data Symbol Parameter Rthj-case Thermal resistance junction-case 0.28 °C/W Rthj-amb Thermal resistance junction-amb 50 °C/W Value Unit 5 A 1100 mJ Table 4: Avalanche characteristics Symbol Parameter IAR(1) Max current during repetitive or single pulse avalanche EAS(2) Single pulse avalanche energy Notes: (1)Pulse width limited by TJmax (2)Starting TJ = 25 °C, ID = IAS, VDD = 50 V DocID026818 Rev 3 3/12 Electrical characteristics 2 STW21N150K5 Electrical characteristics (TCASE = 25 °C unless otherwise specified) Table 5: Static Symbol V(BR)DSS Parameter Test conditions Drain-source breakdown voltage VGS = 0 V, ID = 1 mA Min. Typ. Max. Unit 1500 V VGS = 0 V, VDS = 1500 V 1 µA VGS = 0 V, VDS = 1500 V, Tc = 125 °C 50 µA Gate body leakage current VDS = 0, VGS = ± 20 V ±10 µA VGS(th) Gate threshold voltage VDS = VGS, ID = 100 µA 4 5 V RDS(on) Static drain-source onresistance VGS = 10 V, ID = 7 A 0.7 0.9 Ω IDSS Zero gate voltage drain current IGSS 3 Table 6: Dynamic Symbol Parameter Ciss Input capacitance Coss Output capacitance Crss Reverse transfer capacitance Co(tr)(1) Test conditions VGS = 0 V, VDS = 100 V, f = 1 MHz Equivalent capacitance time related Min. Typ. Max. Unit - 3145 - pF - 172 - pF - 1 - pF - 161 - pF - 65 - pF VDS = 0 V to 1200 V, VGS = 0 V Co(er)(2) Equivalent capacitance energy related RG Intrinsic gate resistance f = 1 MHz, ID = 0 A - 2.4 - Ω VDD = 1200 V, ID = 7 A VGS = 10 V (see Figure 15: "Test circuit for gate charge behavior") - 89 - nC - 16 - nC - 59 - nC Qg Total gate charge Qgs Gate-source charge Qgd Gate-drain charge Notes: (1)Time related is defined as a constant equivalent capacitance giving the same charging time as Coss when VDS increases from 0 to 80% VDSS (2)Energy related is defined as a constant equivalent capacitance giving the same stored energy as Coss when VDS increases from 0 to 80% VDSS Table 7: Switching times Symbol td(on) tr td(off) tf 4/12 Parameter Turn-on delay time Rise time Turn-off delay time Fall time Test conditions VDD = 750 V, ID = 3.5 A, RG = 4.7 Ω VGS = 10 V (see Figure 17: "Unclamped inductive load test circuit") DocID026818 Rev 3 Min. Typ. Max. Unit - 34 - ns - 14 - ns - 134 - ns - 26 - ns STW21N150K5 Electrical characteristics Table 8: Source drain diode Symbol Parameter Test conditions Min. Typ. Max. Unit ISD Source-drain current - 7 A ISDM Source-drain current (pulsed) - 28 A VSD(1) Forward on voltage ISD = 7 A, VGS = 0 V - 1.5 V trr Reverse recovery time - 448 ns Qrr Reverse recovery charge - 8.24 µC IRRM Reverse recovery current ISD = 7 A, VDD = 60 V di/dt = 100 A/µs, (see Figure 16: "Test circuit for inductive load switching and diode recovery times") - 36.8 A ISD = 7 A,VDD = 60 V di/dt = 100 A/µs, Tj = 150 °C (see Figure 16: "Test circuit for inductive load switching and diode recovery times") - 564 ns - 9.48 µC - 33.6 A trr Reverse recovery time Qrr Reverse recovery charge IRRM Reverse recovery current Notes: (1)Pulsed: pulse duration = 300µs, duty cycle 1.5% Table 9: Gate-source Zener diode Symbol V(BR)GSO Parameter Test conditions Gate-source breakdown voltage IGS = ±1 mA, ID = 0 A Min. 30 Typ. Max. - Unit V The built-in back-to-back Zener diodes are specifically designed to enhance the ESD performance of the device. The Zener voltage facilitates efficient and cost-effective device integrity protection, thus eliminating the need for additional external componentry. DocID026818 Rev 3 5/12 Electrical characteristics 2.1 6/12 STW21N150K5 Electrical characteristics (curves) Figure 2: Safe operating area Figure 3: Thermal impedance Figure 4: Output characteristics Figure 5: Transfer characteristics Figure 6: Gate charge vs gate-source voltage Figure 7: Static drain-source on-resistance DocID026818 Rev 3 STW21N150K5 Electrical characteristics Figure 8: Capacitance variations Figure 9: Normalized gate threshold voltage vs temperature Figure 10: Normalized on-resistance vs temperature Figure 11: Normalized V(BR)DSS vs temperature Figure 12: Maximum avalanche energy vs temperature Figure 13: Source-drain diode forward characteristics DocID026818 Rev 3 7/12 Test circuits 3 8/12 STW21N150K5 Test circuits Figure 14: Test circuit for resistive load switching times Figure 15: Test circuit for gate charge behavior Figure 16: Test circuit for inductive load switching and diode recovery times Figure 17: Unclamped inductive load test circuit Figure 18: Unclamped inductive waveform Figure 19: Switching time waveform DocID026818 Rev 3 STW21N150K5 4 Package information Package information In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK ® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. 4.1 TO-247 package information Figure 20: TO-247 package outline DocID026818 Rev 3 9/12 Package information STW21N150K5 Table 10: TO-247 package mechanical data mm. Dim. Min. Max. A 4.85 5.15 A1 2.20 2.60 b 1.0 1.40 b1 2.0 2.40 b2 3.0 3.40 c 0.40 0.80 D 19.85 20.15 E 15.45 15.75 e 5.30 L 14.20 14.80 L1 3.70 4.30 L2 10/12 Typ. 5.45 5.60 18.50 ØP 3.55 ØR 4.50 S 5.30 DocID026818 Rev 3 3.65 5.50 5.50 5.70 STW21N150K5 5 Revision history Revision history Table 11: Document revision history Date Revision 26-Aug-2015 1 First release. 2 Text and formatting changes throughout document. Updated features on cover page. Updated sections Electrical ratings and Electrical characteristics. Added section Electrical characteristics (curves). Updated section TO-247 package information. 3 On cover page: - updated figure Internal schematic diagram In section Electrical characteristics: - updated and renamed table Static (was On/off states). 10-Sep-2015 01-Oct-2015 Changes DocID026818 Rev 3 11/12 STW21N150K5 IMPORTANT NOTICE – PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement. Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers’ products. No license, express or implied, to any intellectual property right is granted by ST herein. Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners. Information in this document supersedes and replaces information previously supplied in any prior versions of this document. © 2015 STMicroelectronics – All rights reserved 12/12 DocID026818 Rev 3