STW23N85K5

STW23N85K5 N-channel 850 V, 0.2 Ω typ., 19 A MDmesh™ K5 Power MOSFET in a TO-247 package Datasheet - production data Features Order code VDS RDS(on) max. ID PTOT STW23N85K5 850 V 0.275 Ω 19 A 250 W • • • • • 3 2 1 TO-247 Industry’s lowest RDS(on) x area Industry’s best figure of merit (FoM) Ultra low gate charge 100% avalanche tested Zener-protected Applications • Figure 1: Internal schematic diagram Switching applications Description This very high voltage N-channel Power MOSFET is designed using MDmesh™ K5 technology based on an innovative proprietary vertical structure. The result is a dramatic reduction in on-resistance and ultra-low gate charge for applications requiring superior power density and high efficiency. Table 1: Device summary Order code Marking Package Packing STW23N85K5 23N85K5 TO-247 Tube August 2015 DocID023547 Rev 3 This is information on a product in full production. 1/13 www.st.com Contents STW23N85K5 Contents 1 Electrical ratings ............................................................................. 3 2 Electrical characteristics ................................................................ 4 2.1 Electrical characteristics (curves) ...................................................... 6 3 Test circuits ..................................................................................... 9 4 Package information ..................................................................... 10 4.1 5 2/13 TO-247 package information ........................................................... 10 Revision history ............................................................................ 12 DocID023547 Rev 3 STW23N85K5 1 Electrical ratings Electrical ratings Table 2: Absolute maximum ratings Symbol VGS ID (1) IDM PTOT dv/dt (2) Tstg Tj Parameter Value Unit Gate-source voltage ±30 V Drain current (continuous) at Tcase = 25 °C 19 Drain current (continuous) at Tcase = 100 °C 12.4 Drain current (pulsed) 250 A Total dissipation at Tcase = 25 °C 250 W 6 V/ns -55 to 150 °C Value Unit Peak diode recovery voltage slope Storage temperature Operating junction temperature A Notes: (1) (2) Pulse width is limited by safe operating area. ISD ≤ 19 A, di/dt=100 A/μs; VDS peak < V(BR)DSS, VDD = 80% V(BR)DSS. Table 3: Thermal data Symbol Parameter Rthj-case Thermal resistance junction-case 0.5 Rthj-amb Thermal resistance junction-ambient 45 °C/W Table 4: Avalanche characteristics Symbol Parameter (1) IAR Avalanche current, repetitive or not repetitive (2) EAS Single pulse avalanche energy Value Unit 6 A 200 mJ Notes: (1) (2) Pulse width limited by Tjmax. starting Tj = 25 °C, ID = IAR, VDD = 50 V. DocID023547 Rev 3 3/13 Electrical characteristics 2 STW23N85K5 Electrical characteristics (Tcase = 25 °C unless otherwise specified) Table 5: Static Symbol V(BR)DSS Parameter Test conditions Drain-source breakdown voltage VGS = 0 V, ID = 1 mA Min. Typ. Max. 850 Unit V VGS = 0 V, VDS = 850 V 10 VGS = 0 V, VDS = 850 V, Tcase = 125 °C 50 ±10 µA 4 5 V 0.2 0.275 Ω Min. Typ. Max. Unit - 1650 - - 115 - - 2 - IDSS Zero gate voltage drain current IGSS Gate-body leakage current VDS = 0 V, VGS = ±20 V VGS(th) Gate threshold voltage VDS = VGS, ID = 100 µA RDS(on) Static drain-source on-resistance VGS = 10 V, ID = 9.5 A 3 µA Table 6: Dynamic Symbol Parameter Test conditions Ciss Input capacitance Coss Output capacitance Crss Reverse transfer capacitance VDS = 100 V, f = 1 MHz, VGS = 0 V pF Equivalent output capacitance VDS = 0 to 680 V, VGS = 0 V - 185 - pF RG Intrinsic gate resistance f = 1 MHz, ID = 0 A - 3.5 - Ω Qg Total gate charge - 38 - Qgs Gate-source charge - 11 - Qgd Gate-drain charge VDD = 520 V, ID = 60 A, VGS = 10 V (see Figure 17: "Gate charge test circuit") - 20 - Coss eq. (1) nC Notes: (1) Coss eq. is defined as a constant equivalent capacitance giving the same charging time as Coss when VDS increases from 0 to 80% VDSS. Table 7: Switching times Symbol td(on) tr td(off) tf 4/13 Parameter Turn-on delay time Rise time Turn-off delay time Fall time Test conditions Min. Typ. Max. VDD = 400 V, ID = 9.5 A RG = 4.7 Ω, VGS = 10 V (see Figure 16: "Switching times test circuit for resistive load" and Figure 21: "Switching time waveform") - 22 - - 14 - - 55 - - 8 - DocID023547 Rev 3 Unit ns STW23N85K5 Electrical characteristics Table 8: Source-drain diode Symbol ISD Parameter Test conditions Min. Typ. Max. Unit Source-drain current - 19 A (1) Source-drain current (pulsed) - 76 A (2) Forward on voltage - 1.5 V ISDM VSD trr Reverse recovery time Qrr Reverse recovery charge IRRM Reverse recovery current trr Reverse recovery time Qrr Reverse recovery charge IRRM Reverse recovery current VGS = 0 V, ISD = 19 A ISD = 19 A, di/dt = 100 A/µs, VDD = 60 V (see Figure 18: "Test circuit for inductive load switching and diode recovery times") ISD = 19 A, di/dt = 100 A/µs, VDD = 60 V, Tj = 150 °C (see Figure 18: "Test circuit for inductive load switching and diode recovery times") - 510 ns - 11 µC - 43 A - 684 ns - 14 µC - 41 A Notes: (1) (2) Pulse width is limited by safe operating area. Pulse test: pulse duration = 300 µs, duty cycle 1.5%. DocID023547 Rev 3 5/13 Electrical characteristics 2.1 6/13 STW23N85K5 Electrical characteristics (curves) Figure 2: Safe operating area Figure 3: Thermal impedance Figure 4: Output characteristics Figure 5: Transfer characteristics Figure 6: Gate charge vs gate-source voltage Figure 7: Static drain-source on-resistance DocID023547 Rev 3 STW23N85K5 Electrical characteristics Figure 8: Capacitance variations Figure 9: Normalized gate threshold voltage vs temperature Figure 10: Normalized on-resistance vs temperature Figure 11: Normalized V(BR)DSS vs temperature Figure 12: Output capacitance stored energy Figure 13: Source- drain diode forward characteristics DocID023547 Rev 3 7/13 Electrical characteristics STW23N85K5 Figure 14: Maximum avalanche energy vs temperature (ID = 3.5 A) 8/13 Figure 15: Maximum avalanche energy vs temperature (ID = 5.0 A) DocID023547 Rev 3 STW23N85K5 3 Test circuits Test circuits Figure 16: Switching times test circuit for resistive load Figure 17: Gate charge test circuit Figure 18: Test circuit for inductive load switching and diode recovery times Figure 19: Unclamped inductive load test circuit Figure 20: Unclamped inductive waveform Figure 21: Switching time waveform DocID023547 Rev 3 9/13 Package information 4 STW23N85K5 Package information In order to meet environmental requirements, ST offers these devices in different grades of ® ® ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com. ® ECOPACK is an ST trademark. 4.1 TO-247 package information Figure 22: TO-247 package outline 0075325_H 10/13 DocID023547 Rev 3 STW23N85K5 Package information Table 9: TO-247 package mechanical data mm. Dim. Min. Typ. Max. A 4.85 5.15 A1 2.20 2.60 b 1.0 1.40 b1 2.0 2.40 b2 3.0 3.40 c 0.40 0.80 D 19.85 20.15 E 15.45 15.75 e 5.30 L 14.20 14.80 L1 3.70 4.30 L2 5.45 5.60 18.50 ØP 3.55 ØR 4.50 S 5.30 DocID023547 Rev 3 3.65 5.50 5.50 5.70 11/13 Revision history 5 STW23N85K5 Revision history Table 10: Document revision history Date Revision 06-Aug-2012 1 First release. 21-Jan-2014 2 Document status promoted from preliminary to production data. Added Figure 12: Maximum avalanche energy vs temperature. 3 Text and formatting changes throughout document. On cover page: - updated Title, Features and Description Updated Section Electrical characteristics Updated Section Electrical characteristics (curves) Updated and renamed Section Package information (was Package mechanical data) 13-Aug-2015 12/13 Changes DocID023547 Rev 3 STW23N85K5 IMPORTANT NOTICE – PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement. Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers’ products. No license, express or implied, to any intellectual property right is granted by ST herein. Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners. Information in this document supersedes and replaces information previously supplied in any prior versions of this document. © 2015 STMicroelectronics – All rights reserved DocID023547 Rev 3 13/13