STW40N65M2

STW40N65M2 N-channel 650 V, 0.087 Ω typ., 32 A MDmesh™ M2 Power MOSFET in a TO-247 package Datasheet - production data Features • • • • 3 2 1 Order code VDS RDS(on) max. ID STW40N65M2 650 V 0.099 Ω 32 A Extremely low gate charge Excellent output capacitance (COSS) profile 100% avalanche tested Zener-protected Applications TO-247 • Figure 1: Internal schematic diagram Switching applications Description This device is an N-channel Power MOSFET developed using MDmesh™ M2 technology. Thanks to its strip layout and an improved vertical structure, the device exhibits low on-resistance and optimized switching characteristics, rendering it suitable for the most demanding high efficiency converters. Table 1: Device summary Order code Marking Package Packaging STW40N65M2 40N65M2 TO-247 Tube February 2015 DocID027443 Rev 1 This is information on a product in full production. 1/12 www.st.com Contents STW40N65M2 Contents 1 Electrical ratings ............................................................................. 3 2 Electrical characteristics ................................................................ 4 2.2 Electrical characteristics (curves) ...................................................... 6 3 Test circuits ..................................................................................... 8 4 Package information ....................................................................... 9 4.1 5 2/12 TO-247 package information ............................................................. 9 Revision history ............................................................................ 11 DocID027443 Rev 1 STW40N65M2 1 Electrical ratings Electrical ratings Table 2: Absolute maximum ratings Symbol VGS Parameter Gate-source voltage Value Unit ± 25 V ID Drain current (continuous) at TC = 25 °C 32 A ID Drain current (continuous) at TC= 100 °C 20 A Drain current (pulsed) 128 A IDM (1) Total dissipation at TC = 25 °C 250 W dv/dt (2) Peak diode recovery voltage slope 15 V/ns dv/dt (3) MOSFET dv/dt ruggedness 50 V/ns PTOT Tstg Tj Storage temperature - 55 to 150 Max. operating junction temperature 150 °C Notes: (1) Pulse width limited by safe operating area. (2) ISD ≤ 32 A, di/dt ≤ 400 A/µs; VDS peak < V(BR)DSS, VDD = 400 V (3) VDS ≤ 520 V Table 3: Thermal data Symbol Parameter Value Unit Rthj-case Thermal resistance junction-case max 0.5 °C/W Rthj-amb Thermal resistance junction-ambient max 50 °C/W Table 4: Avalanche characteristics Symbol Parameter Value Unit IAR Avalanche current, repetitive or not repetitive (pulse width limited by Tjmax) 3 A EAS Single pulse avalanche energy (starting Tj = 25 °C, ID = IAR, VDD = 50 V) 820 mJ DocID027443 Rev 1 3/12 Electrical characteristics 2 STW40N65M2 Electrical characteristics (TC= 25 °C unless otherwise specified) Table 5: On/off states Symbol Parameter Test conditions V(BR)DSS Drain-source breakdown voltage IDSS Zero gate voltage Drain current IGSS VGS = 0 V, ID = 1 mA Min. Typ. Max. 650 Unit V VGS = 0 V, VDS = 650 V 1 µA VGS = 0 V, VDS = 650 V, TC = 125 °C 100 µA Gate-body leakage current VDS = 0 V, VGS = ± 25 V ±10 µA VGS(th) Gate threshold voltage VDS = VGS, ID = 250 µA 3 4 V RDS(on) Static drain-source onresistance VGS = 10 V, ID = 16 A 0.087 0.099 Ω Min. Typ. Max. Unit - 2355 - pF - 102 - pF - 2.7 - pF 2 Table 6: Dynamic Symbol Parameter Ciss Input capacitance Coss Output capacitance Crss Reverse transfer capacitance Test conditions VDS= 100 V, f = 1 MHz, VGS = 0 V Equivalent output capacitance VDS = 0 V to 520 V, VGS = 0 V - 380 - pF RG Intrinsic gate resistance f = 1 MHz open drain - 4.5 - Ω Qg Total gate charge - 56.5 - nC Qgs Gate-source charge - 8 - nC Qgd Gate-drain charge - 24 - nC Coss eq. (1) VDD = 520 V, ID = 32 A, VGS = 10 V (see Figure 15: "Gate charge test circuit") Notes: (1) Coss eq. is defined as a constant equivalent capacitance giving the same charging time as Coss when VDS increases from 0 to 80% VDSS Table 7: Switching times Symbol td(on) tr td(off) tf 4/12 Parameter Turn-on delay time Rise time Turn-off-delay time Fall time Test conditions Min. VDD = 325 V, ID = 16 A RG = 4.7 Ω, VGS = 10 V (see Figure 14: "Switching times test circuit for resistive load" and Figure 19: "Switching time waveform") - DocID027443 Rev 1 Typ. 15 Max. Unit - ns - 10 - ns - 96.5 - ns - 12 - ns STW40N65M2 Electrical characteristics Table 8: Source drain diode Symbol ISD (1) ISDM VSD (2) Parameter Test conditions Min. Typ. Max. Unit Source-drain current - 32 A Source-drain current (pulsed) - 128 A - 1.6 V Forward on voltage trr Reverse recovery time Qrr Reverse recovery charge IRRM VGS = 0 V, ISD = 32 A - 468 ns - 8.7 µC Reverse recovery current - 37.5 A trr Reverse recovery time - 610 ns Qrr Reverse recovery charge - 11.7 µC IRRM Reverse recovery current - 39 A ISD = 32 A, di/dt = 100 A/µs, VDD = 60 V (see Figure 16: " Test circuit for inductive load switching and diode recovery times") ISD = 32 A, di/dt = 100 A/µs, VDD = 60 V, Tj = 150 °C (see Figure 16: " Test circuit for inductive load switching and diode recovery times") Notes: (1) (2) Pulse width is limited by safe operating area Pulse test: pulse duration = 300 µs, duty cycle 1.5% DocID027443 Rev 1 5/12 Electrical characteristics 2.2 STW40N65M2 Electrical characteristics (curves) Figure 2: Safe operating area ID (A) Figure 3: Thermal impedance GIPD030220151540ALS δ=0.5 0.2 100 10µs is 1 DS (o n) O p lim era ite tio d ni by n m this ax a R r ea 10 0.1 0.1 10-1 1ms 10-2 10ms Tj = 150 °C Tc = 25 °C Single pulse Zth = K*Rthj-c δ= tp/Ƭ tp 10-3 10-5 VDS(V) 100 10 -4 10 -3 10 -2 Ƭ 10-1 tp (s) Figure 5: Transfer characteristics ID (A) GIPG300120151500ALS VGS = 6,7,8,9,10 V GIPG300120151715ALS 70 VGS = 5 V 60 0.01 Single pulse Figure 4: Output characteristics 60 50 50 40 40 30 VGS = 20 V 30 VGS = 4 V 20 20 10 10 4 8 12 16 20 0 0 24 VDS (V) Figure 6: Normalized gate threshold voltage vs temperature 6/12 0.1 0.05 0.02 100µs 10 1 ID (A) 70 0 0 GC18460 K 2 4 6 8 VGS (V) Figure 7: Normalized V(BR)DSS vs temperature DocID027443 Rev 1 STW40N65M2 Electrical characteristics Figure 8: Static drain-source on-resistance Figure 9: Normalized on-resistance vs. temperature Figure 10: Gate charge vs. gate-source voltage Figure 11: Capacitance variations Figure 12: Output capacitance stored energy DocID027443 Rev 1 Figure 13: Source-drain diode forward characteristics 7/12 Test circuits 3 STW40N65M2 Test circuits Figure 14: Switching times test circuit for resistive load Figure 15: Gate charge test circuit VDD 47 k Ω 12 V 1 kΩ 100 nF I G = CONST Vi ≤ V GS 100 Ω D.U.T. 2.7 k Ω 2200 μ F VG 47 k Ω PW 1 kΩ AM01469v 1 Figure 16: Test circuit for inductive load switching and diode recovery times A A D.U.T. FAST DIODE B B Figure 17: Unclamped inductive load test circuit A D G S 25 Ω L=100 µH 3.3 µF B 1000 µF D G RG VDD D.U.T. S AM01470v1 Figure 18: Unclamped inductive waveform Figure 19: Switching time waveform toff t on V(BR)DSS t d(on) VD tr t d(off) tf 90% 90% I DM 10% ID VDD 10% 0 VDD VGS AM01472v 1 8/12 DocID027443 Rev 1 0 10% VDS 90% AM01473v 1 STW40N65M2 4 Package information Package information In order to meet environmental requirements, ST offers these devices in different grades of ® ® ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com. ® ECOPACK is an ST trademark. 4.1 TO-247 package information Figure 20: TO-247 drawing 0075325_H DocID027443 Rev 1 9/12 Package information STW40N65M2 Table 9: TO-247 mechanical data mm. Dim. Min. Max. A 4.85 5.15 A1 2.20 2.60 b 1.0 1.40 b1 2.0 2.40 b2 3.0 3.40 c 0.40 0.80 D 19.85 20.15 E 15.45 15.75 e 5.30 L 14.20 14.80 L1 3.70 4.30 L2 10/12 Typ. 5.45 5.60 18.50 ØP 3.55 3.65 ØR 4.50 5.50 S 5.30 DocID027443 Rev 1 5.50 5.70 STW40N65M2 5 Revision history Revision history Table 10: Document revision history Date Revision 09-Feb-2014 1 DocID027443 Rev 1 Changes First release. 11/12 STW40N65M2 IMPORTANT NOTICE – PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement. Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers’ products. No license, express or implied, to any intellectual property right is granted by ST herein. Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners. Information in this document supersedes and replaces information previously supplied in any prior versions of this document. © 2015 STMicroelectronics – All rights reserved 12/12 DocID027443 Rev 1