STW40N90K5

STW40N90K5, STWA40N90K5 N-channel 900 V, 0.088 Ω typ., 40 A MDmesh™ K5 Power MOSFETs in TO-247 and TO-247 long leads packages Datasheet - production data Features Order code STW40N90K5 STWA40N90K5      Figure 1: Internal schematic diagram VDS RDS(on) max ID 900 V 0.099 Ω 40 A Industry’s lowest RDS(on) x area Industry’s best FoM (figure of merit) Ultra-low gate charge 100% avalanche tested Zener-protected Applications  Switching applications Description These very high voltage N-channel Power MOSFETs are designed using MDmesh™ K5 technology based on an innovative proprietary vertical structure. The result is a dramatic reduction in on-resistance and ultra-low gate charge for applications requiring superior power density and high efficiency. Table 1: Device summary Order code STW40N90K5 STWA40N90K5 November 2016 Marking 40N90K5 Package TO-247 TO-247 long leads DocID028929 Rev 2 This is information on a product in full production. Packaging Tube 1/14 www.st.com Contents STW40N90K5, STWA40N90K5 Contents 1 Electrical ratings ............................................................................. 3 2 Electrical characteristics ................................................................ 4 2.1 Electrical characteristics (curves) ...................................................... 6 3 Test circuits ..................................................................................... 8 4 Package mechanical data ............................................................... 9 5 2/14 4.1 TO-247 package information ............................................................. 9 4.2 TO-247 long leads package information ......................................... 11 Revision history ............................................................................ 13 DocID028929 Rev 2 STW40N90K5, STWA40N90K5 1 Electrical ratings Electrical ratings Table 2: Absolute maximum ratings Symbol Parameter VGS Value Unit Gate- source voltage ±30 V ID Drain current (continuous) at TC = 25 °C 40 A ID Drain current (continuous) at TC = 100 °C 25 A Drain current (pulsed) 160 A ID(1) PTOT Total dissipation at TC = 25 °C 446 W dv/dt (2) Peak diode recovery voltage slope 4.5 V/ns dv/dt (3) MOSFET dv/dt ruggedness 50 V/ns -55 to 150 °C Operating junction temperature range Tj Storage temperature range Tstg Notes: (1)Pulse (2)I SD (3)V width limited by safe operating area ≤ 40 A, di/dt ≤ 100 A/µs, VDS(peak) ≤ V(BR)DSS., VDD=450 V DS ≤ 720 V Table 3: Thermal data Symbol Parameter Rthj-case Thermal resistance junction-case max Rthj-amb Thermal resistance junction-amb Value Unit 0.28 °C/W 50 °C/W Table 4: Avalanche characteristics Symbol Parameter Value Unit IAR Avalanche current, repetitive or not repetitive (pulse width limited by T jmax) 13.5 A EAS Single pulse avalanche energy (starting TJ = 25 °C, ID= IAR, VDD= 50 V) 750 mJ DocID028929 Rev 2 3/14 Electrical characteristics 2 STW40N90K5, STWA40N90K5 Electrical characteristics (Tcase =25 °C unless otherwise specified) Table 5: On /off states Symbol V(BR)DSS Parameter Test conditions Drain-source breakdown voltage VGS = 0 V, ID = 1 mA Min. Typ. Max. 900 Unit V VGS = 0 V, VDS = 900 V 1 µA VGS = 0 V, VDS = 900 V, TC=125 °C(1) 50 µA Gate-body leakage current VDS=0 V, VGS = ± 20 V ±10 µA VGS(th) Gate threshold voltage VDS = VGS, ID = 100 µA 4 5 V RDS(on) Static drain-source onresistance VGS = 10 V, ID = 20 A 0.088 0.099 Ω Min. Typ. Max. Unit - 3263 - pF - 212 - pF - 1.3 - pF - 429 - pF - 159 - pF IDSS Zero gate voltage drain current IGSS 3 Notes: (1)Defined by design, not subject to production test. Table 6: Dynamic Symbol Parameter Ciss Input capacitance Coss Output capacitance Crss Reverse transfer capacitance Co(tr)(1) Test conditions VGS=0 V, VDS =100 V, f=1 MHz Equivalent capacitance time related VGS = 0 V, VDS = 0 V to 720 V Co(er)(2) Equivalent capacitance energy related RG Intrinsic gate resistance f = 1 MHz, ID=0 A - 1.9 - Ω Qg Total gate charge - 89 - nC Qgs Gate-source charge - 25 - nC Qgd Gate-drain charge VDD = 720 V, ID = 40 A VGS =10 V (see Figure 15: "Test circuit for gate charge behavior") - 37.5 - nC Notes: (1)Time related is defined as a constant equivalent capacitance giving the same charging time as Coss when VDS increases from 0 to 80% VDSS (2)energy related is defined as a constant equivalent capacitance giving the same stored energy as C oss when VDS increases from 0 to 80% VDSS 4/14 DocID028929 Rev 2 STW40N90K5, STWA40N90K5 Electrical characteristics Table 7: Switching times Symbol td(on) Parameter Test conditions Turn-on delay time tr Turn-off-delay time tf Typ. Max Unit - 30.4 - ns - 15.5 - ns - 84.5 - ns - 13.4 - ns Min. Typ. Max Unit VDD = 450 V, ID = 40 A, RG = 4.7 Ω, VGS = 10 V (see Figure 14: "Test circuit for resistive load switching times") Rise time td(off) Min. Fall time Table 8: Source drain diode Symbol Parameter ISD Source-drain current - 40 A ISDM (1) Source-drain current (pulsed) - 160 A VSD (2) Forward on voltage - 1.5 V trr Reverse recovery time Qrr Reverse recovery charge IRRM Reverse recovery current trr Reverse recovery time Qrr Reverse recovery charge IRRM Reverse recovery current Test conditions ISD = 40 A, VGS = 0 V ISD = 40 A, di/dt = 100 A/µs VDD= 60 V (see Figure 17: "Unclamped inductive load test circuit") ISD = 40 A, di/dt = 100 A/µs VDD= 60 V, TJ = 150 °C (see Figure 17: "Unclamped inductive load test circuit") - 693 ns - 22 µC - 63 A - 884 ns - 29 µC - 65.5 A Notes: (1)Pulse width limited by safe operating area. (2)Pulsed: pulse duration = 300 µs, duty cycle 1.5% Table 9: Gate-source Zener diode Symbol V(BR)GSO Parameter Gate-source breakdown voltage Test conditions IGS = ± 1mA, ID=0 A Min Typ. Max. Unit 30 - - V The built-in back-to-back Zener diodes are specifically designed to enhance the ESD performance of the device. The Zener voltage facilitates efficient and cost-effective device integrity protection, thus eliminating the need for additional external componentry. DocID028929 Rev 2 5/14 Electrical characteristics 2.1 STW40N90K5, STWA40N90K5 Electrical characteristics (curves) Figure 2: Safe operating area Figure 3: Thermal impedance d d t Figure 4: Output characteristics Figure 5: Transfer characteristics Figure 6: Gate charge vs gate-source voltage Figure 7: Static drain-source on-resistance 6/14 DocID028929 Rev 2 STW40N90K5, STWA40N90K5 Electrical characteristics Figure 8: Capacitance variations Figure 9: Normalized gate threshold voltage vs temperature Figure 10: Normalized on-resistance vs temperature Figure 11: Normalized V(BR)DSS vs temperature Figure 12: Source-drain diode forward characteristics Figure 13: Maximum avalanche energy vs starting TJ DocID028929 Rev 2 7/14 Test circuits 3 STW40N90K5, STWA40N90K5 Test circuits Figure 14: Test circuit for resistive load switching times Figure 15: Test circuit for gate charge behavior VDD RL IG= CONST VGS + pulse width 2200 μF 100 Ω D.U.T. 2.7 kΩ VG 47 kΩ 1 kΩ AM01469v10 Figure 16: Test circuit for inductive load switching and diode recovery times Figure 17: Unclamped inductive load test circuit Figure 18: Unclamped inductive waveform 8/14 DocID028929 Rev 2 Figure 19: Switching time waveform STW40N90K5, STWA40N90K5 4 Package mechanical data Package mechanical data In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. 4.1 TO-247 package information Figure 20: TO-247 package outline DocID028929 Rev 2 9/14 Package mechanical data STW40N90K5, STWA40N90K5 Table 10: TO-247 package mechanical data mm Dim. Min. Max. A 4.85 5.15 A1 2.20 2.60 b 1.0 1.40 b1 2.0 2.40 b2 3.0 3.40 c 0.40 0.80 D 19.85 20.15 E 15.45 15.75 e 5.30 L 14.20 14.80 L1 3.70 4.30 L2 10/14 Typ. 5.45 5.60 18.50 ØP 3.55 ØR 4.50 S 5.30 DocID028929 Rev 2 3.65 5.50 5.50 5.70 STW40N90K5, STWA40N90K5 4.2 Package mechanical data TO-247 long leads package information Figure 21: TO-247 long lead package outline DocID028929 Rev 2 11/14 Package mechanical data STW40N90K5, STWA40N90K5 Table 11: TO-247 long lead package mechanical data mm Dim. Min. Typ. Max. A 4.90 5.00 5.10 A1 2.31 2.41 2.51 A2 1.90 2.00 2.10 b 1.16 1.26 b2 3.25 b3 2.25 c 0.59 0.66 D 20.90 21.00 21.10 E 15.70 15.80 15.90 E2 4.90 5.00 5.10 E3 2.40 2.50 2.60 e 5.34 5.44 5.54 L 19.80 19.92 20.10 P 3.50 3.60 Q 5.60 S 6.05 L1 12/14 4.30 DocID028929 Rev 2 3.70 6.00 6.15 6.25 STW40N90K5, STWA40N90K5 5 Revision history Revision history Table 12: Document revision history Date Revision 26-Jan-2016 1 First release. 2 Updated Section 1: "Electrical ratings" and Section 2: "Electrical characteristics" Added Section 2.1: "Electrical characteristics (curves)". Document status changed from preliminary to production data. Minor text changes. 25-Nov-2016 Changes DocID028929 Rev 2 13/14 STW40N90K5, STWA40N90K5 IMPORTANT NOTICE – PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement. Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers’ products. No license, express or implied, to any intellectual property right is granted by ST herein. Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners. Information in this document supersedes and replaces information previously supplied in any prior versions of this document. © 2016 STMicroelectronics – All rights reserved 14/14 DocID028929 Rev 2