STW40N95K5

STW40N95K5 N-channel 950 V, 0.110 Ω typ., 38 A MDmesh™ K5 Power MOSFET in a TO-247 package Datasheet - production data Features Order code VDS RDS(on) max ID PTOT STW40N95K5 950 V 0.130 Ω 38 A 450 W      3 2 1 TO-247 Industry’s lowest RDS(on) x area Industry’s best figure of merit (FoM) Ultra low gate charge 100% avalanche tested Zener-protected Applications Figure 1: Internal schematic diagram  Switching applications Description This very high voltage N-channel Power MOSFET is designed using MDmesh™ K5 technology based on an innovative proprietary vertical structure. The result is a dramatic reduction in on-resistance and ultra-low gate charge for applications requiring superior power density and high efficiency. Table 1: Device summary Order code Marking Package Packaging STW40N95K5 40N95K5 TO-247 Tube November 2014 DocID026447 Rev 2 This is information on a product in full production. 1/13 www.st.com Contents STW40N95K5 Contents 1 Electrical ratings ............................................................................. 3 2 Electrical characteristics ................................................................ 4 2.1 Electrical characteristics (curves) ...................................................... 6 3 Test circuits ..................................................................................... 9 4 Package mechanical data ............................................................. 10 4.1 5 2/13 TO-247 package information ........................................................... 10 Revision history ............................................................................ 12 DocID026447 Rev 2 STW40N95K5 1 Electrical ratings Electrical ratings Table 2: Absolute maximum ratings Symbol VGS Parameter Gate- source voltage Value Unit ± 30 V ID Drain current (continuous) at TC = 25 °C 38 A ID Drain current (continuous) at TC = 100 °C 24 A Drain current (pulsed) 152 A Total dissipation at TC = 25 °C 450 W IAR Max current during repetitive or single pulse avalanche 13 A EAS Single pulse avalanche energy (starting TJ = 25 °C, ID= 13 A, VDD= 50 V) 700 mJ dv/dt (2) Peak diode recovery voltage slope 4.5 V/ns dv/dt (3) MOSFET dv/dt ruggedness 50 V/ns -55 to 150 °C IDM (1) PTOT Tj Tstg Operating junction temperature Storage temperature Notes: (1)Pulse (2)I SD (3)V width limited by safe operating area. ≤ 19 A, di/dt ≤ 100 A/µs, VDS(peak) ≤ V(BR)DSS. DS ≤ 760 V Table 3: Thermal data Symbol Parameter Value Unit Rthj-case Thermal resistance junction-case max 0.28 °C/W Rthj-amb Thermal resistance junction-amb max 50 °C/W DocID026447 Rev 2 3/13 Electrical characteristics 2 STW40N95K5 Electrical characteristics (Tcase =25 °C unless otherwise specified) Table 4: On /off states Symbol V(BR)DSS Parameter Test conditions Drain-source breakdown voltage VGS = 0, ID = 1 mA Min. Typ. Max. 950 Unit V VGS = 0, VDS = 950 V 1 µA VGS = 0, VDS = 950 V, TC=125 °C 50 µA ±10 µA 4 5 V 0.110 0.130 Ω Min. Typ. Max. Unit IDSS Zero gate voltage drain current IGSS Gate-body leakage current VDS=0, VGS = ± 20 V VGS(th) Gate threshold voltage VDS = VGS, ID = 100 µA RDS(on) Static drain-source onresistance VGS = 10 V, ID = 19 A 3 Table 5: Dynamic Symbol Parameter Test conditions Ciss Input capacitance - 3300 - pF Coss Output capacitance - 250 - pF Crss Reverse transfer capacitance - 2 - pF Co(tr)(1) Equivalent capacitance time related - 398 - pF Co(er)(2) Equivalent capacitance energy related - 142 - pF RG Intrinsic gate resistance f = 1 MHz, ID=0 - 5 - Ω Qg Total gate charge - 93 - nC Qgs Gate-source charge - 18.7 - nC Qgd Gate-drain charge VDD = 760 V, ID = 38 A VGS =10 V (see Figure 16: "Gate charge test circuit") - 63.4 - nC VGS=0, VDS =100 V, f=1 MHz VGS = 0, VDS = 0 to 760 V Notes: (1)Time related is defined as a constant equivalent capacitance giving the same charging time as Coss when VDS increases from 0 to 80% VDSS (2)energy related is defined as a constant equivalent capacitance giving the same stored energy as C oss when VDS increases from 0 to 80% VDSS Table 6: Switching times Symbol td(on) tr td(off) tf 4/13 Parameter Turn-on delay time Rise time Turn-off-delay time Test conditions VDD = 475 V, ID = 19 A, RG = 4.7 Ω, VGS = 10 V (see Figure 15: "Switching times test circuit for resistive load") Fall time DocID026447 Rev 2 Min. Typ. Max Unit - 33.5 - ns - 51 - ns - 91.5 - ns - 10 - ns STW40N95K5 Electrical characteristics Table 7: Source drain diode Symbol Parameter ISD Source-drain current ISDM (1) Source-drain current (pulsed) VSD (2) Forward on voltage trr Reverse recovery time Qrr Reverse recovery charge IRRM Reverse recovery current trr Reverse recovery time Qrr Reverse recovery charge IRRM Reverse recovery current Test conditions Min. ISD = 38 A, VGS = 0 ISD = 38 A, di/dt = 100 A/µs VDD= 60 V (see Figure 18: " Unclamped inductive load test circuit") ISD = 38 A, di/dt = 100 A/µs VDD= 60 V TJ = 150 °C (see Figure 18: " Unclamped inductive load test circuit") Typ. Max Unit - 38 A - 152 A - 1.5 V - 706 ns - 22 µC - 62 A - 886 ns - 28.2 µC - 64 A Notes: (1)Pulse width limited by safe operating area. (2)Pulsed: pulse duration = 300 µs, duty cycle 1.5% Table 8: Gate-source Zener diode Symbol V(BR)GSO Parameter Gate-source breakdown voltage Test conditions IGS = ± 1mA, ID=0 Min Typ. Max. Unit 30 - - V The built-in back-to-back Zener diodes have specifically been designed to enhance the device's ESD capability. In this respect the Zener voltage is appropriate to achieve an efficient and cost-effective intervention to protect the device's integrity. These integrated Zener diodes thus avoid the usage of external components. DocID026447 Rev 2 5/13 Electrical characteristics 2.1 STW40N95K5 Electrical characteristics (curves) Figure 2: Safe operating area Figure 3: Thermal impedance AM09125v1 K δ=0.5 0.2 0.1 0.05 10 -1 0.02 0.01 Z th=k R thj-c δ=tp/ t Single pulse tp t -2 10 -4 10 6/13 10 -3 10 -2 10 -1 tp (s) Figure 4: Output characteristics Figure 5: Transfer characteristics Figure 6: Gate charge vs gate-source voltage Figure 7: Static drain-source on-resistance DocID026447 Rev 2 STW40N95K5 Electrical characteristics Figure 8: Capacitance variations Figure 9: Normalized gate threshold voltage vs temperature Figure 10: Normalized on-resistance Figure 11: Normalized V(BR)DSS vs temperature GIPD121120141039FSR R DS(on) (norm) 1.12 2.6 V GS= 10V ID= 1m A 2.2 1.08 1.8 1.04 1.4 1.00 1 0.96 0.6 0.92 0.2 -50 GIPD121120141041FSR V (BR)DSS (norm) 0 50 100 T j(°C) Figure 12: Output capacitance stored energy DocID026447 Rev 2 0.88 -50 0 50 100 T j(°C) Figure 13: Source-drain diode forward characteristics 7/13 Electrical characteristics STW40N95K5 Figure 14: Maximum avalanche energy vs T J GIPD141120141040FSR E AS (mJ) 600 400 200 0 -50 8/13 Single pulse ID= 13 A V DD= 50V 0 50 DocID026447 Rev 2 100 T j(°C) STW40N95K5 3 Test circuits Test circuits Figure 15: Switching times test circuit for resistive load Figure 16: Gate charge test circuit Figure 17: Test circuit for inductive load switching and diode recovery times Figure 18: Unclamped inductive load test circuit Figure 19: Unclamped inductive waveform DocID026447 Rev 2 Figure 20: Switching time waveform 9/13 Package mechanical data 4 STW40N95K5 Package mechanical data In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK ® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. 4.1 TO-247 package information Figure 21: TO-247 drawing 10/13 DocID026447 Rev 2 STW40N95K5 Package mechanical data Table 9: TO-247 mechanical data mm. Dim. Min. Typ. Max. A 4.85 5.15 A1 2.20 2.60 b 1.0 1.40 b1 2.0 2.40 b2 3.0 3.40 c 0.40 0.80 D 19.85 20.15 E 15.45 15.75 e 5.30 L 14.20 14.80 L1 3.70 4.30 L2 5.45 5.60 18.50 ØP 3.55 3.65 ØR 4.50 5.50 S 5.30 DocID026447 Rev 2 5.50 5.70 11/13 Revision history 5 STW40N95K5 Revision history Table 10: Document revision history 12/13 Date Revision Changes 03-Jun-2014 1 First release. 14-Nov-2014 2 Document status promoted from preliminary to production data. Added Section 2.1: "Electrical characteristics (curves)". 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All other product or service names are the property of their respective owners. Information in this document supersedes and replaces information previously supplied in any prior versions of this document. © 2014 STMicroelectronics – All rights reserved DocID026447 Rev 2 13/13