STW45NM50

STW45NM50 N-channel 500 V, 0.08 Ω typ., 45 A MDmesh™ Power MOSFET in a TO-247 package Datasheet - production data Features     3 2 1 Order code VDS RDS(on) max ID STW45NM50 500 V 0.1 Ω 45 A 100% avalanche tested High dv/dt and avalanche capabilities Low input capacitance and gate charge Low gate input resistance Applications TO-247  Switching applications Description Figure 1: Internal schematic diagram This N-channel Power MOSFET is developed using STMicroelectronics' revolutionary MDmesh™ technology, which associates the multiple drain process with the company's PowerMESH™ horizontal layout. This device offer extremely low on-resistance, high dv/dt and excellent avalanche characteristics. Utilizing ST's proprietary strip technique, this Power MOSFET boasts an overall dynamic performance which is superior to similar products on the market. Table 1: Device summary Order code Marking Package Packaging STW45NM50 W45NM50 TO-247 Tube July 2016 DocID8477 Rev 6 This is information on a product in full production. 1/12 www.st.com Contents STW45NM50 Contents 1 Electrical ratings ............................................................................. 3 2 Electrical characteristics ................................................................ 4 2.1 Electrical characteristics (curves) ...................................................... 6 3 Test circuits ..................................................................................... 8 4 Package information ....................................................................... 9 4.1 5 2/12 TO-247 package information ............................................................. 9 Revision history ............................................................................ 11 DocID8477 Rev 6 STW45NM50 1 Electrical ratings Electrical ratings Table 2: Absolute maximum ratings Symbol VGS Parameter Value Unit Gate-source voltage ±30 V ID Drain current (continuous) at TC = 25 °C 45 A ID Drain current (continuous) at TC = 100 °C 28.4 A Drain current (pulsed) 180 A Total dissipation at TC = 25 °C 390 W Peak diode recovery voltage slope 15 V/ns -55 to 150 °C IDM (1) PTOT (2) dv/dt Tstg Tj Storage temperature range Operating junction temperature range Notes: (1)Pulse (2)I SD width limited by safe operating area. ≤ 45 A, di/dt ≤ 400 A/µs, VDS(peak) ≤ V(BR)DSS, VDD ≤ 80% V(BR)DSS Table 3: Thermal data Symbol Parameter Rthj-case Thermal resistance junction-case Rthj-amb Thermal resistance junction-ambient Value Unit 0.32 °C/W 30 °C/W Table 4: Avalanche characteristics Symbol Parameter Value Unit IAR Avalanche current, repetitive or not-repetitive (pulse width limited by Tj max) 15 A EAS Single pulse avalanche energy (starting TJ=25 °C, ID=IAR, VDD=50 V) 700 mJ DocID8477 Rev 6 3/12 Electrical characteristics 2 STW45NM50 Electrical characteristics (TCASE = 25 °C unless otherwise specified) Table 5: On/off states Symbol V(BR)DSS Parameter Test conditions Drain-source breakdown voltage ID = 1 mA, VGS = 0 V IDSS Zero gate voltage drain current IGSS Min. Typ. Max. 500 V VGS = 0 V, VDS = 500 V 10 VGS = 0 V, VDS = 500 V, TC= 125 °C (1) 100 Gate-body leakage current VDS = 0 V, VGS = ±30 V VGS(th) Gate threshold voltage VDS = VGS, ID = 250 µA RDS(on) Static drain-source onresistance VGS = 10 V, ID = 22.5 A Unit µA ±100 nA 4 5 V 0.08 0.1 Ω Min. Typ. Max. Unit - 3290 - pF - 865 - pF - 140 - pF VGS = 0 V, VDS = 0 to 400 V - 270 - pF - 113 - nC - 17 - nC - 82 - nC - 1.7 - Ω 3 Notes: (1)Defined by design, not subject to production test. Table 6: Dynamic Symbol Ciss Parameter Test conditions Input capacitance VDS = 25 V, f = 1 MHz, VGS = 0 V Coss Output capacitance Crss Reverse transfer capacitance Coss eq. (1) Equivalent output capacitance Qg Total gate charge Qgs Gate-source charge Qgd Gate-drain charge VDD = 400 V, ID = 45 A, VGS = 10 V (see Figure 14: "Test circuit for gate charge behavior") RG Gate input resistance f = 1 MHz, ID= 0 A Notes: (1)C oss eq. is defined as a constant equivalent capacitance giving the same charging time as C oss when VDS increases from 0 to 80% VDS 4/12 DocID8477 Rev 6 STW45NM50 Electrical characteristics Table 7: Switching times Symbol Parameter Test conditions Min. Typ. Max. Unit td(on) Turn-on delay time VDD = 250 V, ID = 22.5 A, RG = 4.7 Ω, VGS = 10 V (see Figure 15: "Test circuit for inductive load switching and diode recovery times") - 29.1 - ns - 73.6 - ns VDD = 400 V, ID = 45 A, RG = 4.7 Ω, VGS = 10 V (see Figure 15: "Test circuit for inductive load switching and diode recovery times") - 20.8 - ns - 58.3 - ns - 67.6 - ns Max. Unit tr Rise time Off-voltage rise time tr(Voff) tf Fall time tc Cross-over time Table 8: Source-drain diode Symbol Parameter Test conditions Min. Typ. ISD Source-drain current - 45 A ISDM(1) Source-drain current (pulsed) - 180 A VSD(2) Forward on voltage ISD = 45 A, VGS = 0 V - 1.5 trr Reverse recovery time - 454 ns Qrr Reverse recovery charge - 9380 nC IRRM Reverse recovery current ISD = 45 A, di/dt = 100 A/µs VDD = 60 V (see Figure 15: "Test circuit for inductive load switching and diode recovery times") - 41.3 A ISD = 45 A, di/dt = 100 A/µs VDD = 100 V, Tj = 150 °C (see Figure 15: "Test circuit for inductive load switching and diode recovery times") - 567 ns - 12700 nC - 44.8 A trr Reverse recovery time Qrr Reverse recovery charge IRRM Reverse recovery current V Notes: (1)Pulse width limited by safe operating area. (2)Pulsed: pulse duration = 300 µs, duty cycle 1.5% DocID8477 Rev 6 5/12 Electrical characteristics 2.1 STW45NM50 Electrical characteristics (curves) Figure 2: Safe operating area Figure 3: Thermal impedance d Figure 4: Output characteristics Figure 5: Transfer characteristics Figure 6: Gate charge vs gate-source voltage Figure 7: Static drain-source on resistance 6/12 DocID8477 Rev 6 STW45NM50 Electrical characteristics Figure 8: Capacitance variations Figure 9: Normalized gate threshold voltage vs temperature Figure 10: Normalized on-resistance vs temperature Figure 11: Normalized V(BR)DSS vs temperature Figure 12: Source-drain diode forward characteristics DocID8477 Rev 6 7/12 Test circuits 3 STW45NM50 Test circuits Figure 13: Test circuit for resistive load switching times Figure 15: Test circuit for inductive load switching and diode recovery times Figure 17: Unclamped inductive waveform 8/12 DocID8477 Rev 6 Figure 14: Test circuit for gate charge behavior Figure 16: Unclamped inductive load test circuit Figure 18: Switching time waveform STW45NM50 4 Package information Package information In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK ® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. 4.1 TO-247 package information Figure 19: TO-247 package outline DocID8477 Rev 6 9/12 Package information STW45NM50 Table 9: TO-247 package mechanical data mm Dim. Min. Max. A 4.85 5.15 A1 2.20 2.60 b 1.0 1.40 b1 2.0 2.40 b2 3.0 3.40 c 0.40 0.80 D 19.85 20.15 E 15.45 15.75 e 5.30 L 14.20 14.80 L1 3.70 4.30 L2 10/12 Typ. 5.45 5.60 18.50 ØP 3.55 ØR 4.50 S 5.30 DocID8477 Rev 6 3.65 5.50 5.50 5.70 STW45NM50 5 Revision history Revision history Table 10: Document revision history Date Revision 30-Mar-2005 4 Modified value on Source drain diode 23-Jul-2009 5 Modified values on Switching times 6 Modified: Table 2: "Absolute maximum ratings", Table 3: "Thermal data", Table 4: "Avalanche characteristics", Table 5: "On/off states", Table 6: "Dynamic", Table 7: "Switching times" and Table 8: "Source-drain diode" Modified: Section 5.1: "Electrical characteristics (curves)" Updated: Section 7.1: "TO-247 package information" 18-Jul-2016 Changes DocID8477 Rev 6 11/12 STW45NM50 IMPORTANT NOTICE – PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement. Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers’ products. No license, express or implied, to any intellectual property right is granted by ST herein. Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners. Information in this document supersedes and replaces information previously supplied in any prior versions of this document. © 2016 STMicroelectronics – All rights reserved 12/12 DocID8477 Rev 6