STW56N60M2-4

STW56N60M2-4 Datasheet N-channel 600 V, 45 mΩ typ., 52 A MDmesh M2 Power MOSFET in a TO247-4 package Features 1 2 4 3 TO247-4 Drain(1, TAB) Order code VDS at TJ max. RDS(on) max. ID STW56N60M2-4 650 V 55 mΩ 52 A • • Extremely low gate charge Excellent output capacitance (Coss) profile • • • 100% avalanche tested Zener-protected Excellent switching performance thanks to the extra driving source pin Applications • Switching applications Gate(4) Description Driver source (3) Power source (2) AM10177v2Z This device is an N-channel Power MOSFET developed using MDmesh M2 technology. Thanks to its strip layout and an improved vertical structure, the device exhibits low on-resistance and optimized switching characteristics, rendering it suitable for the most demanding high efficiency converters. Product status link STW56N60M2-4 Product summary Order code STW56N60M2-4 Marking 56N60M2 Package TO247-4 Packing Tube DS10508 - Rev 4 - August 2022 For further information contact your local STMicroelectronics sales office. www.st.com STW56N60M2-4 Electrical ratings 1 Electrical ratings Table 1. Absolute maximum ratings Symbol Value Unit Gate-source voltage ±25 V Drain current (continuous) at TC = 25 °C 52 Drain current (continuous) at TC = 100 °C 33 IDM(1) Drain current (pulsed) 208 A PTOT Total power dissipation at TC = 25 °C 350 W dv/dt(2) Peak diode recovery voltage slope 15 V/ns dv/dt(3) MOSFET dv/dt ruggedness 50 V/ns Tstg Storage temperature range -55 to 150 °C 150 °C Value Unit 0.36 °C/W 50 °C/W VGS ID TJ Parameter Operating junction temperature A 1. Pulse width limited by safe operating area. 2. ISD ≤ 52 A, di/dt = 400 A/µs, VDS (peak) < V(BR)DSS, VDD = 400 V. 3. VDS ≤ 480 V. Table 2. Thermal data Symbol Parameter RthJC Thermal resistance, junction-to-case RthJA Thermal resistance, junction-to-ambient Table 3. Avalanche characteristics DS10508 - Rev 4 Symbol Parameter Value Unit IAR Avalanche current, repetitive or non-repetitive (pulse width limited by TJ max.) 7.5 A EAS Single pulse avalanche energy (starting TJ = 25 °C, ID = IAR, VDD = 50 V) 1100 mJ page 2/12 STW56N60M2-4 Electrical characteristics 2 Electrical characteristics TC = 25 °C unless otherwise specified. Table 4. On/off states Symbol V(BR)DSS Parameter Test conditions Drain-source breakdown voltage Min. VGS = 0 V, ID = 1 mA Typ. 600 Zero gate voltage drain current IGSS Gate-body leakage current VDS = 0 V, VGS = ± 25 V VGS(th) Gate threshold voltage VDS = VGS, ID = 250 µA RDS(on) Static drain-source on-resistance VGS = 10 V, ID = 26 A VGS = 0 V, VDS = 600 V, TC = 125 Unit V VGS = 0 V, VDS = 600 V IDSS Max. 1 °C(1) 100 µA ±10 μA 3 4 V 45 55 mΩ Min. Typ. Max. Unit - 3750 - pF - 175 - pF - 6.6 - pF 2 1. Specified by design, not tested in production. Table 5. Dynamic Symbol Parameter Test conditions Ciss Input capacitance Coss Output capacitance Crss Reverse transfer capacitance Co(er) (1) Equivalent output capacitance VGS = 0 V, VDS = 0 to 480 V - 740 - pF RG Intrinsic gate resistance f = 1 MHz, open drain - 4.7 - Ω Qg Total gate charge - 91 - nC Qgs Gate-source charge - 13.5 - nC Qgd Gate-drain charge - 41 - nC VDS = 100 V, f = 1 MHz, VGS = 0 V VDD = 480 V, ID = 52 A, VGS = 0 to 10 V (see Figure 14. Test circuit for gate charge behavior) 1. Coss eq. is defined as a constant equivalent capacitance giving the same charging time as Coss when VDS increases from 0 to 80% VDSS. Table 6. Switching times Symbol td(on) tr td(off) tf DS10508 - Rev 4 Parameter Test conditions Min. Typ. Max. Unit Turn-on delay time VDD = 300 V, ID = 26 A, - 18 - ns Rise time RG = 4.7 Ω, VGS = 10 V - 26.5 - ns Turn-off delay time (see Figure 13. Switching times test circuit for resistive load and Figure 18. Switching time waveform) - 119 - ns - 14 - ns Fall time page 3/12 STW56N60M2-4 Electrical characteristics Table 7. Source drain diode Symbol ISD ISDM (1) VSD(2) Parameter Test conditions Min. Typ. Max. Unit Source-drain current - 52 A Source-drain current (pulsed) - 208 A 1.6 V Forward on voltage ISD = 52 A, VGS = 0 - trr Reverse recovery time ISD = 52 A, di/dt = 100 A/µs - 496 ns Qrr Reverse recovery charge VDD = 60 V - 10 µC IRRM Reverse recovery current (see Figure 15. Test circuit for inductive load switching and diode recovery times) - 41 A trr Reverse recovery time ISD = 52 A, di/dt = 100 A/µs - 632 ns Qrr Reverse recovery charge VDD = 60 V, TJ = 150 °C - 14 µC Reverse recovery current (see Figure 15. Test circuit for inductive load switching and diode recovery times) - 45 A IRRM 1. Pulse width limited by safe operating area. 2. Pulsed: pulse duration = 300 µs, duty cycle 1.5%. DS10508 - Rev 4 page 4/12 STW56N60M2-4 Electrical characteristics (curves) 2.1 Electrical characteristics (curves) Figure 2. Thermal impedance Figure 1. Safe operating area ID (A) K GIPD281120141509FSR 100 ea is in th n m tio y ra d b pe ite m Li 10 ar ax R TO247EZx8 10µs is ) on ( DS 10 -1 100µs Zth=k*Rthj-c O 1ms 10ms 1 10 -2 Tj=150°C Tc=25°C Single pulse 0.1 0.1 10 1 VDS(V) 100 10 -3 10 -5 Figure 3. Output characteristics ID (A) VGS= 7, 8, 9, 10 V GIPD281120141611FSR 120 100 5V 80 80 60 60 40 VDS = 18 V 40 4V 20 20 5 10 15 20 25 30 VDS(V) Figure 5. Gate charge vs gate-source voltage GIPD011220141351FSR VDS VDD = 480 V ID = 52 A VDS (V) 0 0 400 47 300 46 4 200 45 2 100 44 6 15 30 45 60 75 90 0 Qg(nC) 4 RDS(on) (mΩ) 48 8 2 6 8 10 VGS(V) Figure 6. Static drain-source on-resistance 500 10 DS10508 - Rev 4 tp (s) 10 -1 140 6V 100 0 0 10 -2 ID (A) GIPD281120141518FSR 120 VGS (V) 10 -3 Figure 4. Transfer characteristics 140 0 0 10 -4 43 0 GIPD281120141625FSR VGS= 10V 8 16 24 32 40 48 ID(A) page 5/12 STW56N60M2-4 Electrical characteristics (curves) Figure 7. Capacitance variations C (pF) GIPD011220141357FSR 10000 Ciss 1000 Coss 100 Figure 8. Normalized gate threshold voltage vs temperature VGS(th) (norm) GIPD180920141442FSR ID = 250 µA 1.1 1.0 0.9 Crss 10 1 0.8 0.7 0.1 0.1 1 10 100 VDS(V) Figure 9. Normalized on-resistance GIPD180920141459FSR RDS(on) 0.6 -75 V(BR)DSS (norm) 2.2 1.08 1.4 1.00 1.0 0.96 0.6 0.92 -25 25 75 125 Tj(°C) GIPD180920141448FSR ID= 1mA 1.04 VGS= 10 V 0.2 -75 25 Figure 10. Normalized V(BR)DSS vs temperature (norm) 1.8 -25 75 125 TJ(°C) Figure 11. Source-drain diode forward characteristics VSD (V) GIPD011220141407FSR 1.1 Tj= -50°C 0.88 -75 -25 25 75 125 Tj(°C) Figure 12. Output capacitance stored energy E (µJ) GIPD011220141403FSR 25 1.0 20 0.9 Tj= 25°C 15 0.8 Tj= 150°C 0.7 5 0.6 0.5 DS10508 - Rev 4 10 0 8 16 24 32 40 48 ISD(A) 0 0 100 200 300 400 500 600 VDS(V) page 6/12 STW56N60M2-4 Test circuits 3 Test circuits Figure 13. Switching times test circuit for resistive load Figure 14. Test circuit for gate charge behavior VDD 12V 47kΩ 1kΩ 100nF + VD VGS 3.3 µF 2200 RL µF IG=CONST VDD 2200 µF + RG 100Ω Vi ≤ VGS D.U.T. D.U.T. VG 2.7kΩ PW 47kΩ GND1 (driver signal) GND2 (power) 1kΩ PW GND1 AM15855v1 Figure 15. Test circuit for inductive load switching and diode recovery times A A D.U.T. FAST DIODE S A L L=100µH D 25Ω VD 3.3 µF B B B AM15856v1 Figure 16. Unclamped inductive load test circuit D G GND2 + 1000 µF 2200 µF 3.3 µF + VDD VDD ID G S RG D.U.T. Vi Pw GND2 GND1 D.U.T. GND1 GND2 AM15858v1 AM15857v1 Figure 17. Unclamped inductive waveform Figure 18. Switching time waveform V(BR)DSS ton td(on) VD toff td(off) tr tf 90% 90% IDM VDD 10% 0 ID VDD VGS 0 VDS 10% 90% 10% AM01473v1 AM01472v1 DS10508 - Rev 4 page 7/12 STW56N60M2-4 Package information 4 Package information In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com. ECOPACK is an ST trademark. 4.1 TO247-4 package information Figure 19. TO247-4 package outline 8405626_Rev_3 DS10508 - Rev 4 page 8/12 STW56N60M2-4 TO247-4 package information Table 8. TO247-4 mechanical data Dim. mm Min. Typ. Max. A 4.90 5.00 5.10 A1 2.31 2.41 2.51 A2 1.90 2.00 2.10 b 1.16 b1 1.15 b2 0 0.20 c 0.59 0.66 c1 0.58 0.60 0.62 D 20.90 21.00 21.10 D1 16.25 16.55 16.85 D2 1.05 1.20 1.35 D3 24.97 25.12 25.27 E 15.70 15.80 15.90 E1 13.10 13.30 13.50 E2 4.90 5.00 5.10 E3 2.40 2.50 2.60 e 2.44 2.54 2.64 e1 4.98 5.08 5.18 L 19.80 19.92 20.10 P 3.50 3.60 3.70 1.29 1.20 P1 7.40 P2 2.40 Q 5.60 S 2.50 2.60 6.00 6.15 T 9.80 10.20 U 6.00 6.40 aaa DS10508 - Rev 4 1.25 0.04 0.10 page 9/12 STW56N60M2-4 Revision history Table 9. Document revision history Date Revision 25-Jul-2014 1 01-Dec-2014 2 29-Jan-2015 3 Changes Initial release. Document status promoted from preliminary to production data. Added Section 2.1: "Electrical characteristics (curves)". Updated Figure 1: "Internal schematic diagram". Updated Internal schematic diagram on cover page. 25-Aug-2022 4 Updated Section 4 Package information. Minor text changes. DS10508 - Rev 4 page 10/12 STW56N60M2-4 Contents Contents 1 Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2 2 Electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2.1 Electrical characteristics (curves) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3 Test circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 4 Package information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 4.1 TO247-4 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 DS10508 - Rev 4 page 11/12 STW56N60M2-4 IMPORTANT NOTICE – READ CAREFULLY STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. 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Information in this document supersedes and replaces information previously supplied in any prior versions of this document. © 2022 STMicroelectronics – All rights reserved DS10508 - Rev 4 page 12/12