STW56N65DM2

STW56N65DM2 N-channel 650 V, 0.058 Ω typ., 48 A MDmesh™ DM2 Power MOSFET in a TO-247 package Datasheet - production data Features Order code VDS RDS(on) max. ID PTOT STW56N65DM2 650 V 0.065 Ω 48 A 360 W   3 2 1     TO-247 Fast-recovery body diode Extremely low gate charge and input capacitance Low on-resistance 100% avalanche tested Extremely high dv/dt ruggedness Zener-protected Applications Figure 1: Internal schematic diagram  Switching applications Description This high voltage N-channel Power MOSFET is part of the MDmesh™ DM2 fast recovery diode series. It offers very low recovery charge (Qrr) and time (trr) combined with low RDS(on), rendering it suitable for the most demanding high efficiency converters and ideal for bridge topologies and ZVS phase-shift converters. Table 1: Device summary Order code Marking Package Packing STW56N65DM2 56N65DM2 TO-247 Tube September 2015 DocID027142 Rev 2 This is information on a product in full production. 1/12 www.st.com Contents STW56N65DM2 Contents 1 Electrical ratings ............................................................................. 3 2 Electrical characteristics ................................................................ 4 2.1 Electrical characteristics (curves) ...................................................... 6 3 Test circuits ..................................................................................... 8 4 Package information ....................................................................... 9 4.1 5 2/12 TO-247 package information ............................................................. 9 Revision history ............................................................................ 11 DocID027142 Rev 2 STW56N65DM2 1 Electrical ratings Electrical ratings Table 2: Absolute maximum ratings Symbol Value Unit Gate-source voltage ±25 V Drain current (continuous) at Tcase = 25 °C 48 Drain current (continuous) at Tcase = 100 °C 30 IDM(1) Drain current (pulsed) 192 A PTOT W VGS ID Parameter Total dissipation at Tcase = 25 °C 360 dv/dt(2) Peak diode recovery voltage slope 50 dv/dt(3) MOSFET dv/dt ruggedness 50 Tstg Tj Storage temperature Operating junction temperature A V/ns -55 to 150 °C Value Unit Notes: (1) Pulse width is limited by safe operating area. (2) ISD ≤ 48 A, di/dt= 900 A/μs; VDS peak < V(BR)DSS, VDD = 400 V (3) VDS ≤ 520 V. Table 3: Thermal data Symbol Parameter Rthj-case Thermal resistance junction-case Rthj-amb Thermal resistance junction-ambient 0.35 50 °C/W Table 4: Avalanche characteristics Symbol IAR EAS(1) Parameter Avalanche current, repetitive or not repetitive Single pulse avalanche energy Value Unit 7 A 1300 mJ Notes: (1) starting Tj = 25 °C, ID = IAR, VDD = 50 V. DocID027142 Rev 2 3/12 Electrical characteristics 2 STW56N65DM2 Electrical characteristics (Tcase = 25 °C unless otherwise specified) Table 5: Static Symbol Parameter Test conditions V(BR)DSS Drain-source breakdown voltage VGS = 0 V, ID = 1 mA Min. Typ. Max. 650 Unit V VGS = 0 V, VDS = 650 V 10 VGS = 0 V, VDS = 650 V, Tcase = 125 °C 100 Gate-body leakage current VDS = 0 V, VGS = ±25 V ±5 µA VGS(th) Gate threshold voltage VDS = VGS, ID = 250 µA 4 5 V RDS(on) Static drain-source onresistance VGS = 10 V, ID = 24 A 0.058 0.065 Ω Min. Typ. Max. Unit - 4100 - - 160 - - 2.5 - IDSS Zero gate voltage drain current IGSS 3 µA Table 6: Dynamic Symbol Parameter Test conditions Ciss Input capacitance Coss Output capacitance Crss Reverse transfer capacitance Coss eq.(1) Equivalent output capacitance VDS = 0 to 520 V, VGS = 0 V - 375 - pF RG Intrinsic gate resistance f = 1 MHz, ID = 0 A - 4.1 - Ω Qg Total gate charge - 88 - Qgs Gate-source charge - 22 - Qgd Gate-drain charge VDD = 520 V, ID = 48 A, VGS = 10 V (see Figure 15: "Test circuit for gate charge behavior") - 37 - VDS = 100 V, f = 1 MHz, VGS = 0 V pF nC Notes: (1) Coss eq. is defined as a constant equivalent capacitance giving the same charging time as Coss when VDS increases from 0 to 80% VDSS. Table 7: Switching times Symbol td(on) tr td(off) tf 4/12 Parameter Turn-on delay time Rise time Turn-off delay time Fall time Test conditions Min. Typ. Max. VDD = 325 V, ID = 24 A RG = 4.7 Ω, VGS = 10 V (see Figure 14: "Test circuit for resistive load switching times" and Figure 19: "Switching time waveform") - 28 - - 31 - - 157 - - 7.7 - DocID027142 Rev 2 Unit ns STW56N65DM2 Electrical characteristics Table 8: Source-drain diode Symbol Parameter Test conditions Min. Typ. Max. Unit ISD Source-drain current - 48 A ISDM(1) Source-drain current (pulsed) - 192 A VSD(2) Forward on voltage VGS = 0 V, ISD = 48 A - 1.6 V trr Reverse recovery time - 135 ns Qrr Reverse recovery charge - 0.68 µC IRRM Reverse recovery current ISD = 48 A, di/dt = 100 A/µs, VDD = 100 V (see Figure 16: "Test circuit for inductive load switching and diode recovery times") - 10 A ISD = 48 A, di/dt = 100 A/µs, VDD = 100 V, Tj = 150 °C (see Figure 16: "Test circuit for inductive load switching and diode recovery times") - 260 ns - 2.75 µC - 21 A trr Reverse recovery time Qrr Reverse recovery charge IRRM Reverse recovery current Notes: (1) Pulse width is limited by safe operating area. (2) Pulse test: pulse duration = 300 µs, duty cycle 1.5%. DocID027142 Rev 2 5/12 Electrical characteristics 2.1 6/12 STW56N65DM2 Electrical characteristics (curves) Figure 2: Safe operating area Figure 3: Thermal impedance Figure 4: Output characteristics Figure 5: Transfer characteristics Figure 6: Gate charge vs gate-source voltage Figure 7: Static drain-source on-resistance DocID027142 Rev 2 STW56N65DM2 Electrical characteristics Figure 8: Capacitance variations Figure 9: Normalized gate threshold voltage vs temperature Figure 10: Normalized on-resistance vs temperature Figure 11: Normalized V(BR)DSS vs temperature Figure 12: Output capacitance stored energy Figure 13: Source- drain diode forward characteristics DocID027142 Rev 2 7/12 Test circuits 3 8/12 STW56N65DM2 Test circuits Figure 14: Test circuit for resistive load switching times Figure 15: Test circuit for gate charge behavior Figure 16: Test circuit for inductive load switching and diode recovery times Figure 17: Unclamped inductive load test circuit Figure 18: Unclamped inductive waveform Figure 19: Switching time waveform DocID027142 Rev 2 STW56N65DM2 4 Package information Package information In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. 4.1 TO-247 package information Figure 20: TO-247 package outline DocID027142 Rev 2 9/12 Package information STW56N65DM2 Table 9: TO-247 package mechanical data mm. Dim. Min. Max. A 4.85 5.15 A1 2.20 2.60 b 1.0 1.40 b1 2.0 2.40 b2 3.0 3.40 c 0.40 0.80 D 19.85 20.15 E 15.45 15.75 e 5.30 L 14.20 14.80 L1 3.70 4.30 L2 10/12 Typ. 5.45 5.60 18.50 ØP 3.55 ØR 4.50 S 5.30 DocID027142 Rev 2 3.65 5.50 5.50 5.70 STW56N65DM2 5 Revision history Revision history Table 10: Document revision history Date Revision 27-Nov-2014 1 First release. 2 Text and formatting changes throughout document. In section Electrical ratings: - updated tables Absolute maximum ratings and Avalanche characteristics In section Electrical characteristics: - updated and renamed table Static (was On/off states) - updated tables Dynamic, Switching times and Source-drain diode Updated section Electrical characteristics (curves) 15-Sep-2015 Changes DocID027142 Rev 2 11/12 STW56N65DM2 IMPORTANT NOTICE – PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement. Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers’ products. No license, express or implied, to any intellectual property right is granted by ST herein. Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners. Information in this document supersedes and replaces information previously supplied in any prior versions of this document. © 2015 STMicroelectronics – All rights reserved 12/12 DocID027142 Rev 2