STW56N65M2

STW56N65M2 N-channel 650 V, 0.049 Ω typ., 49 A MDmesh™ M2 Power MOSFET in a TO-247 package Datasheet - production data Features Order code VDS RDS(on) max ID STW56N65M2 650 V 0.062 Ω 49 A • Extremely low gate charge • Excellent output capacitance (Coss) profile   • 100% avalanche tested  • Zener-protected Applications 72 • Switching applications Figure 1. Internal schematic diagram Description This device is an N-channel Power MOSFET developed using MDmesh™ M2 technology. Thanks to its strip layout and an improved vertical structure, the device exhibits low on-resistance and optimized switching characteristics, rendering it suitable for the most demanding high efficiency converters. ' * 6 $0Y Table 1. Device summary Order code Marking Package Packaging STW56N65M2 56N65M2 TO-247 Tube December 2014 This is information on a product in full production. DocID027285 Rev 1 1/12 www.st.com Contents STW56N65M2 Contents 1 Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2.1 Electrical characteristics (curves) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 3 Test circuits 4 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 4.1 5 2/12 .............................................. 8 TO-247, STW56N65M2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 DocID027285 Rev 1 STW56N65M2 1 Electrical ratings Electrical ratings Table 2. Absolute maximum ratings Symbol Value Unit Gate- source voltage ±25 V ID Drain current (continuous) at TC = 25 °C 49 A ID Drain current (continuous) at TC = 100 °C 31 A IDM (1) Drain current (pulsed) 196 A PTOT Total dissipation at TC = 25 °C 358 W Peak diode recovery voltage slope 15 V/ns MOSFET dv/dt ruggedness 50 V/ns - 55 to 150 °C 150 °C Value Unit 50 °C/W 0.35 °C/W VGS dv/dt (2) dv/dt(3) Tstg Tj Parameter Storage temperature Max. operating junction temperature 1. Pulse width limited by safe operating area 2. ISD ≤ 49 A, di/dt = 400 A/µs, peak VDS < V(BR)DSS, VDD = 400 V 3. VDS ≤ 520 V Table 3. Thermal data Symbol Parameter Rthj-amb Thermal resistance junction-ambient max Rthj-case Thermal resistance junction-case max Table 4. Avalanche characteristics Symbol Parameter IAR Max current during repetitive or single pulse avalanche (pulse width limited by TJMAX) EAS Single pulse avalanche energy (starting Tj = 25 °C, ID = IAR, VDD = 50 V) DocID027285 Rev 1 Value Unit 3.5 A 1300 mJ 3/12 12 Electrical characteristics 2 STW56N65M2 Electrical characteristics (TC = 25 °C unless otherwise specified) Table 5. On /off states Symbol V(BR)DSS Parameter Drain-source breakdown voltage Test conditions ID = 1 mA, VGS = 0 Min. Typ. Max. 650 Unit V IDSS Zero gate voltage VDS = 650 V drain current (VGS = 0) VDS = 650 V, TC = 125 °C 1 100 µA µA IGSS Gate-body leakage current (VDS = 0) ± 10 nA 3 4 V 0.049 0.062 Ω Min. Typ. Max. Unit - 3900 - pF - 160 - pF - 2.8 - pF VGS = ± 25 V VGS(th) Gate threshold voltage VDS = VGS, ID = 250 µA RDS(on) Static drain-source onVGS = 10 V, ID = 24.5 A resistance 2 Table 6. Dynamic Symbol 1. 4/12 Parameter Test conditions Ciss Input capacitance Coss Output capacitance Crss Reverse transfer capacitance Co(er)(1) Equivalent Output Capacitance VGS = 0, VDS = 0 to 520 V - 838 - pF RG Intrinsic gate resistance f = 1 MHz open drain - 4.6 - Ω Qg Total gate charge - 93 - nC - 16 - nC - 40 - nC Qgs Gate-source charge Qgd Gate-drain charge VDS = 100 V, f = 1 MHz, VGS = 0 VDD = 520 V, ID = 49 A, VGS = 10 V, (see Figure 15) Coss eq. is defined as a constant equivalent capacitance giving the same charging time as Coss when VDS increases from 0 to 80% VDSS DocID027285 Rev 1 STW56N65M2 Electrical characteristics Table 7. Switching times Symbol td(on) Parameter Test conditions Turn-on delay time VDD = 325 V, ID = 24.5 A, RG = 4.7 Ω, VGS = 10 V (see Figure 16 and Figure 19) Rise time tr td(off) tf Turn-off delay time Fall time Min. Typ. Max. Unit - 19 - ns - 27.5 - ns - 146 - ns - 13 - ns Min. Typ. Table 8. Source drain diode Symbol Parameter Test conditions Max. Unit Source-drain current - 49 A ISDM (1) Source-drain current (pulsed) - 196 A VSD (2) Forward on voltage ISD = 49 A, VGS = 0 - 1.6 V trr Reverse recovery time - 554 ns Qrr Reverse recovery charge - 13.5 µC IRRM Reverse recovery current ISD = 49 A, di/dt = 100 A/µs VDD = 60 V (see Figure 16) - 49.5 A - 688 ns - 18 µC - 52 A ISD trr Reverse recovery time Qrr Reverse recovery charge IRRM Reverse recovery current ISD = 49 A, di/dt = 100 A/µs VDD = 60 V, Tj = 150 °C (see Figure 19) 1. Pulse width limited by safe operating area 2. Pulsed: pulse duration = 300 µs, duty cycle 1.5% DocID027285 Rev 1 5/12 12 Electrical characteristics 2.1 STW56N65M2 Electrical characteristics (curves) Figure 2. Safe operating area Figure 3. Thermal impedance *,3'07 ,' $  —V LV HD Q DU 6R  ' LV WK 5 LQ D[ Q P LW R E\ UD G SH WH 2 LPL /  —V PV PV  7M ƒ& 7F ƒ& 6LQJOHSXOVH     9'69  Figure 4. Output characteristics *,3'07 ,' $ 9*6 9  Figure 5. Transfer characteristics *,3'07 ,' $    9      9'6 9  9           9'69 Figure 6. Normalized gate threshold voltage vs. temperature GIPD180920141442FSR VGS(th) (norm) ID = 250 µA 1.1  0.9  0.8  0.7  25 75 125 Tj(°C)    9*69 *,3')65 9%5'66 QRUP  -25  Figure 7. Normalized V(BR)DSS vs. temperature 1.0 0.6 -75 6/12     DocID027285 Rev 1 ,' P$     7Mƒ& STW56N65M2 Electrical characteristics Figure 8. Static drain-source on-resistance *,3'07 5'6RQ ȍ Figure 9. Normalized on-resistance vs. temperature *,3')65 5'6RQ QRUP   9*6 9 9*6 9              ,'$ Figure 10. Gate charge vs. gate-source voltage *,3'07 9'6 9 9*6 9  9'' 9 ,' $ 9'6       7Mƒ& Figure 11. Capacitance variations *,3'07 & S)       &LVV  &RVV                 4JQ& Figure 12. Output capacitance stored energy *,3'07 ( —- &UVV    Figure 13. Source-drain diode forward characteristics *,3'07 96' 9   9'69   7M ƒ&   7M ƒ&   7M ƒ&            9'69  DocID027285 Rev 1      ,6'$ 7/12 12 Test circuits 3 STW56N65M2 Test circuits Figure 14. Switching times test circuit for resistive load Figure 15. Gate charge test circuit VDD 12V 47kΩ 1kΩ 100nF 3.3 μF 2200 RL μF IG=CONST VDD VGS RG 100Ω Vi=20V=VGMAX VD 2200 μF D.U.T. D.U.T. VG 2.7kΩ PW 47kΩ 1kΩ PW AM01469v1 AM01468v1 Figure 16. Test circuit for inductive load switching and diode recovery times A A Figure 17. Unclamped inductive load test circuit L A D G FAST DIODE D.U.T. S 3.3 μF B B B VD L=100μH 25 Ω 1000 μF D VDD 2200 μF 3.3 μF VDD ID G RG S Vi D.U.T. Pw AM01471v1 AM01470v1 Figure 18. Unclamped inductive waveform Figure 19. Switching time waveform ton V(BR)DSS tdon VD toff tr tdoff tf 90% 90% IDM 10% ID VDD 10% 0 VDD VDS 90% VGS AM01472v1 8/12 0 DocID027285 Rev 1 10% AM01473v1 STW56N65M2 4 Package mechanical data Package mechanical data In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. 4.1 TO-247, STW56N65M2 Figure 20. TO-247 drawing 0075325_H DocID027285 Rev 1 9/12 12 Package mechanical data STW56N65M2 Table 9. TO-247 mechanical data mm. Dim. Min. Typ. A 4.85 5.15 A1 2.20 2.60 b 1.0 1.40 b1 2.0 2.40 b2 3.0 3.40 c 0.40 0.80 D 19.85 20.15 E 15.45 15.75 e 5.30 L 14.20 14.80 L1 3.70 4.30 5.45 L2 10/12 Max. 5.60 18.50 ∅P 3.55 3.65 ∅R 4.50 5.50 S 5.30 5.50 DocID027285 Rev 1 5.70 STW56N65M2 5 Revision history Revision history Table 10. Document revision history Date Revision 10-Dec-2014 1 Changes Initial release. DocID027285 Rev 1 11/12 12 STW56N65M2 IMPORTANT NOTICE – PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement. Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers’ products. No license, express or implied, to any intellectual property right is granted by ST herein. Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners. Information in this document supersedes and replaces information previously supplied in any prior versions of this document. © 2014 STMicroelectronics – All rights reserved 12/12 DocID027285 Rev 1