STW65N80K5

STW65N80K5 N-channel 800 V, 0.07 Ω typ., 46 A MDmesh™ K5 Power MOSFET in a TO-247 package Datasheet - production data Features Order code VDS RDS(on) max. ID PTOT STW65N80K5 800 V 0.08 Ω 46 A 446 W      3 2 1 TO-247 Industry’s lowest RDS(on) x area Industry’s best figure of merit (FoM) Ultra low gate charge 100% avalanche tested Zener-protected Applications  Figure 1: Internal schematic diagram Switching applications Description This very high voltage N-channel Power MOSFET is designed using MDmesh™ K5 technology based on an innovative proprietary vertical structure. The result is a dramatic reduction in on-resistance and ultra-low gate charge for applications requiring superior power density and high efficiency. Table 1: Device summary Order code Marking Package Packing STW65N80K5 65N80K5 TO-247 Tube October 2015 DocID027717 Rev 2 This is information on a product in full production. 1/12 www.st.com Contents STW65N80K5 Contents 1 Electrical ratings ............................................................................. 3 2 Electrical characteristics ................................................................ 4 2.1 Electrical characteristics (curves) ...................................................... 6 3 Test circuits ..................................................................................... 8 4 Package information ....................................................................... 9 4.1 5 2/12 TO-247 package information ............................................................. 9 Revision history ............................................................................ 11 DocID027717 Rev 2 STW65N80K5 1 Electrical ratings Electrical ratings Table 2: Absolute maximum ratings Symbol Value Unit Gate-source voltage ±30 V Drain current (continuous) at Tcase = 25 °C 46 Drain current (continuous) at Tcase = 100 °C 30 IDM(1) Drain current (pulsed) 184 A PTOT W VGS ID Parameter Total dissipation at Tcase = 25 °C 446 dv/dt(2) Peak diode recovery voltage slope 4.5 dv/dt(3) MOSFET dv/dt ruggedness 50 Tstg Tj Storage temperature Operating junction temperature A V/ns -55 to 150 °C Value Unit Notes: (1) Pulse width is limited by safe operating area. (2) ISD ≤ 46 A, di/dt=100 A/μs; VDS peak < V(BR)DSS, VDD = 80% V(BR)DSS. (3) VDS ≤ 640 V Table 3: Thermal data Symbol Parameter Rthj-case Thermal resistance junction-case Rthj-amb Thermal resistance junction-ambient 0.28 50 °C/W Table 4: Avalanche characteristics Symbol Parameter Value Unit IAR(1) Avalanche current, repetitive or not repetitive 16 A EAS(2) Single pulse avalanche energy 700 mJ Notes: (1) Pulse width limited by Tjmax. (2) starting Tj = 25 °C, ID = IAR, VDD = 50 V. DocID027717 Rev 2 3/12 Electrical characteristics 2 STW65N80K5 Electrical characteristics (Tcase = 25 °C unless otherwise specified) Table 5: Static Symbol V(BR)DSS Parameter Test conditions Drain-source breakdown voltage VGS = 0 V, ID = 1 mA Min. Typ. Max. 800 Unit V VGS = 0 V, VDS = 800 V 1 VGS = 0 V, VDS = 800 V, Tcase = 125 °C 50 Gate-body leakage current VDS = 0 V, VGS = ±20 V ±10 µA VGS(th) Gate threshold voltage VDS = VGS, ID = 100 µA 4 5 V RDS(on) Static drain-source onresistance VGS = 10 V, ID = 23 A 0.07 0.08 Ω Min. Typ. Max. Unit - 3230 - - 310 - - 3 - IDSS Zero gate voltage drain current IGSS 3 µA Table 6: Dynamic Symbol Parameter Test conditions Ciss Input capacitance Coss Output capacitance Crss Reverse transfer capacitance Coss(eq)(1) Equivalent output capacitance VDS = 0 to 640 V, VGS = 0 V - 734 - pF RG Intrinsic gate resistance f = 1 MHz, ID = 0 A - 1.9 - Ω Qg Total gate charge - 92 - Qgs Gate-source charge - 18 - Qgd Gate-drain charge VDD = 640 V, ID = 46 A, VGS = 10 V (see Figure 14: "Test circuit for gate charge behavior") - 65 - VDS = 100 V, f = 1 MHz, VGS = 0 V pF nC Notes: (1) Coss(eq) is defined as a constant equivalent capacitance giving the same charging time as C OSS when VDS increases from 0 to 80% VDSS. Table 7: Switching times Symbol td(on) tr td(off) tf 4/12 Parameter Turn-on delay time Rise time Turn-off delay time Fall time Test conditions Min. Typ. Max. VDD = 400 V, ID = 23 A RG = 4.7 Ω, VGS = 10 V (see Figure 13: "Test circuit for resistive load switching times" and Figure 18: "Switching time waveform") - 34 - - 30 - - 90 - - 10 - DocID027717 Rev 2 Unit ns STW65N80K5 Electrical characteristics Table 8: Source-drain diode Symbol Parameter Test conditions Min. Typ. Max. Unit ISD Source-drain current - 46 A ISDM(1) Source-drain current (pulsed) - 184 A VSD(2) Forward on voltage VGS = 0 V, ISD = 46 A - 1.5 V trr Reverse recovery time - 650 ns Qrr Reverse recovery charge - 20 µC IRRM Reverse recovery current ISD = 46 A, di/dt = 100 A/µs, VDD = 60 V (see Figure 15: "Test circuit for inductive load switching and diode recovery times") - 60 A ISD = 46 A, di/dt = 100 A/µs, VDD = 60 V, Tj = 150 °C (see Figure 15: "Test circuit for inductive load switching and diode recovery times") - 845 ns - 28 µC - 66 A Min. Typ. Max. Unit ±30 - - V trr Reverse recovery time Qrr Reverse recovery charge IRRM Reverse recovery current Notes: (1) Pulse width is limited by safe operating area. (2) Pulse test: pulse duration = 300 µs, duty cycle 1.5%. Table 9: Gate-source Zener diode Symbol V(BR)GSO Parameter Gate-source breakdown voltage Test conditions IGS = ±1 mA, ID = 0 A The built-in back-to-back Zener diodes are specifically designed to enhance the ESD performance of the device. The Zener voltage facilitates efficient and cost-effective device integrity protection, thus eliminating the need for additional external componentry. DocID027717 Rev 2 5/12 Electrical characteristics 2.1 6/12 STW65N80K5 Electrical characteristics (curves) Figure 2: Safe operating area Figure 3: Thermal impedance Figure 4: Output characteristics Figure 5: Transfer characteristics Figure 6: Gate charge vs gate-source voltage Figure 7: Static drain-source on-resistance DocID027717 Rev 2 STW65N80K5 Electrical characteristics Figure 8: Capacitance variations Figure 9: Normalized gate threshold voltage vs temperature Figure 10: Normalized on-resistance vs temperature Figure 11: Normalized V(BR)DSS vs temperature Figure 12: Maximum avalanche energy vs temperature DocID027717 Rev 2 7/12 Test circuits 3 8/12 STW65N80K5 Test circuits Figure 13: Test circuit for resistive load switching times Figure 14: Test circuit for gate charge behavior Figure 15: Test circuit for inductive load switching and diode recovery times Figure 16: Unclamped inductive load test circuit Figure 17: Unclamped inductive waveform Figure 18: Switching time waveform DocID027717 Rev 2 STW65N80K5 4 Package information Package information In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK ® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. 4.1 TO-247 package information Figure 19: TO-247 package outline DocID027717 Rev 2 9/12 Package information STW65N80K5 Table 10: TO-247 package mechanical data mm. Dim. Min. Max. A 4.85 5.15 A1 2.20 2.60 b 1.0 1.40 b1 2.0 2.40 b2 3.0 3.40 c 0.40 0.80 D 19.85 20.15 E 15.45 15.75 e 5.30 L 14.20 14.80 L1 3.70 4.30 L2 10/12 Typ. 5.45 5.60 18.50 ØP 3.55 ØR 4.50 S 5.30 DocID027717 Rev 2 3.65 5.50 5.50 5.70 STW65N80K5 5 Revision history Revision history Table 11: Document revision history Date Revision 21-May-2015 1 First release. 2 Text and formatting changes throughout document. Datasheet status promoted from preliminary to production data. On cover page: - updated title description and Features table. Updated sections - Electrical ratings and Electrical characteristics. Added section - Electrical characteristics (curves). 02-Oct-2015 Changes DocID027717 Rev 2 11/12 STW65N80K5 IMPORTANT NOTICE – PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement. Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers’ products. No license, express or implied, to any intellectual property right is granted by ST herein. Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners. Information in this document supersedes and replaces information previously supplied in any prior versions of this document. © 2015 STMicroelectronics – All rights reserved 12/12 DocID027717 Rev 2