STW70N65M2

STW70N65M2 N-channel 650 V, 0.039 Ω typ., 63 A MDmesh™ M2 Power MOSFET in a TO-247 package Datasheet - production data Features     3 2 1 VDS RDS(on) max. ID STW70N65M2 650 V 0.046 Ω 63 A Extremely low gate charge Excellent output capacitance (COSS) profile 100% avalanche tested Zener-protected Applications TO-247  Figure 1: Internal schematic diagram Switching applications Description This device is an N-channel Power MOSFET developed using MDmesh™ M2 technology. Thanks to its strip layout and an improved vertical structure, the device exhibits low on-resistance and optimized switching characteristics, rendering it suitable for the most demanding high efficiency converters. D(2) G(1) S(3) Order code AM15572v1_no_tab Table 1: Device summary Order code Marking Package Packaging STW70N65M2 70N65M2 TO-247 Tube February 2016 DocID028962 Rev 1 This is information on a product in full production. 1/12 www.st.com Contents STW70N65M2 Contents 1 Electrical ratings ............................................................................. 3 2 Electrical characteristics ................................................................ 4 2.1 Electrical characteristics (curves) ...................................................... 6 3 Test circuits ..................................................................................... 8 4 Package mechanical data ............................................................... 9 4.1 5 2/12 TO-247 package information ............................................................. 9 Revision history ............................................................................ 11 DocID028962 Rev 1 STW70N65M2 1 Electrical ratings Electrical ratings Table 2: Absolute maximum ratings Symbol VGS Parameter Gate-source voltage Value Unit ± 25 V ID Drain current (continuous) at TC = 25 °C 63 A ID Drain current (continuous) at TC= 100 °C 40 A (1) IDM Drain current (pulsed) 252 A PTOT Total dissipation at TC = 25 °C 446 W dv/dt (2) Peak diode recovery voltage slope 15 V/ns dv/dt (3) MOSFET dv/dt ruggedness 50 V/ns - 55 to 150 °C Tstg Tj Storage temperature range Operating junction temperature range Notes: (1) Pulse width limited by safe operating area. (2) ISD ≤ 63 A, di/dt ≤ 400 A/µs; VDS peak < V(BR)DSS, VDD = 400 V (3) VDS ≤ 520 V Table 3: Thermal data Symbol Parameter Rthj-case Thermal resistance junction-case max Rthj-amb Thermal resistance junction-ambient max Value Unit 0.28 °C/W 50 °C/W Table 4: Avalanche characteristics Symbol Parameter Value Unit IAR Avalanche current, repetetive or not repetetive (pulse width limited by Tjmax) 4 A EAS Single pulse avalanche energy (starting Tj = 25 °C, ID = IAR, VDD = 50 V) 3500 mJ DocID028962 Rev 1 3/12 Electrical characteristics 2 STW70N65M2 Electrical characteristics (TC= 25 °C unless otherwise specified) Table 5: On/off states Symbol V(BR)DSS Parameter Test conditions Drain-source breakdown voltage VGS = 0 V, ID = 1 mA Min. Typ. Max. 650 Unit V VGS = 0 V, VDS = 650 V 1 µA VGS = 0 V, VDS = 650 V, (1) TC = 125 °C 100 µA Gate-body leakage current VDS = 0 V, VGS = ± 25 V ±5 µA VGS(th) Gate threshold voltage VDS = VGS, ID = 250 µA 3 4 V RDS(on) Static drain-source on-resistance VGS = 10 V, ID = 31.5 A 0.039 0.046 Ω Min. Typ. Max. Unit - 5140 - pF - 208 - pF - 2.9 - pF IDSS Zero gate voltage drain current IGSS 2 Notes: (1) Defined by design, not subject to production test. Table 6: Dynamic Symbol Parameter Ciss Input capacitance Coss Output capacitance Crss Reverse transfer capacitance Test conditions VDS= 100 V, f = 1 MHz, VGS = 0 V Equivalent output capacitance VDS = 0 V to 520 V, VGS = 0 V - 520 - pF RG Intrinsic gate resistance f = 1 MHz, ID=0 A - 3 - Ω Qg Total gate charge - 117 - nC Qgs Gate-source charge - 21.5 - nC Qgd Gate-drain charge VDD = 520 V, ID = 63 A, VGS = 10 V (see Figure 15: "Test circuit for gate charge behavior") - 51 - nC Coss eq. (1) Notes: (1) Coss eq. is defined as a constant equivalent capacitance giving the same charging time as Coss when VDS increases from 0 to 80% VDSS Table 7: Switching times Symbol td(on) tr td(off) tf 4/12 Parameter Turn-on delay time Rise time Turn-off-delay time Fall time Test conditions Min. VDD = 325 V, ID = 31.5 A RG = 4.7 Ω, VGS = 10 V (see Figure 14: "Test circuit for resistive load switching times" and Figure 19: "Switching time waveform") - DocID028962 Rev 1 Typ. 24 Max. Unit - ns - 22 - ns - 134 - ns - 11 - ns STW70N65M2 Electrical characteristics Table 8: Source drain diode Symbol ISD Parameter Test conditions Min. Typ. Max. Unit Source-drain current - 63 A (1) Source-drain current (pulsed) - 252 A (2) Forward on voltage VGS = 0 V, ISD = 63 A - 1.6 V trr Reverse recovery time - 584 ns Qrr Reverse recovery charge - 14.5 µC IRRM Reverse recovery current ISD = 63 A, di/dt = 100 A/µs, VDD = 60 V (see Figure 16: "Test circuit for inductive load switching and diode recovery times") - 50.5 A ISD = 63 A, di/dt = 100 A/µs, VDD = 60 V, Tj = 150 °C (see Figure 16: "Test circuit for inductive load switching and diode recovery times") - 725 ns - 20 µC - 55.5 ISDM VSD trr Reverse recovery time Qrr Reverse recovery charge IRRM Reverse recovery current A Notes: (1) (2) Pulse width is limited by safe operating area Pulse test: pulse duration = 300 µs, duty cycle 1.5% DocID028962 Rev 1 5/12 Electrical characteristics 2.2 STW70N65M2 Electrical characteristics (curves) Figure 2: Safe operating area Figure 3: Thermal impedance d 6/12 Figure 4: Output characteristics Figure 5: Transfer characteristics Figure 6: Gate charge vs. gate-source voltage Figure 7: Static drain-source on-resistance DocID028962 Rev 1 STW70N65M2 Electrical characteristics Figure 8: Capacitance variations Figure 9: Normalized gate threshold voltage vs temperature Figure 10: Normalized on-resistance vs temperature Figure 11: Normalized V(BR)DSS vs temperature Figure 12: Output capacitance stored energy Figure 13: Source-drain diode forward characteristics DocID028962 Rev 1 7/12 Test circuits 3 8/12 STW70N65M2 Test circuits Figure 14: Test circuit for resistive load switching times Figure 15: Test circuit for gate charge behavior Figure 16: Test circuit for inductive load switching and diode recovery times Figure 17: Unclamped inductive load test circuit Figure 18: Unclamped inductive waveform Figure 19: Switching time waveform DocID028962 Rev 1 STW70N65M2 4 Package mechanical data Package mechanical data In order to meet environmental requirements, ST offers these devices in different grades of ® ® ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com. ® ECOPACK is an ST trademark. 4.1 TO-247 package information Figure 20: TO-247 package outline DocID028962 Rev 1 9/12 Package mechanical data STW70N65M2 Table 9: TO-247 package mechanical data mm. Dim. Min. Max. A 4.85 5.15 A1 2.20 2.60 b 1.0 1.40 b1 2.0 2.40 b2 3.0 3.40 c 0.40 0.80 D 19.85 20.15 E 15.45 15.75 e 5.30 L 14.20 14.80 L1 3.70 4.30 L2 10/12 Typ. 5.45 5.60 18.50 ØP 3.55 ØR 4.50 S 5.30 DocID028962 Rev 1 3.65 5.50 5.50 5.70 STW70N65M2 5 Revision history Revision history Table 10: Document revision history Date Revision 04-Feb-2016 1 DocID028962 Rev 1 Changes First release. 11/12 STW70N65M2 IMPORTANT NOTICE – PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement. Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers’ products. No license, express or implied, to any intellectual property right is granted by ST herein. Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners. Information in this document supersedes and replaces information previously supplied in any prior versions of this document. © 2016 STMicroelectronics – All rights reserved 12/12 DocID028962 Rev 1