STW75N60M6-4

STW75N60M6-4 Datasheet N-channel 600 V, 32 mΩ typ., 72 A, MDmesh™ M6 Power MOSFET in a TO247-4 package Features 1 2 4 3 TO247-4 Drain(1, TAB) Order code V DS RDS(on) max. ID STW75N60M6-4 600 V 36 mΩ 72 A • • Reduced switching losses Lower RDS(on) per area vs previous generation • • • • Low gate input resistance 100% avalanche tested Zener-protected Excellent switching performance thanks to the extra driving source pin Applications • • • Gate(4) Driver source (3) Power source (2) AM10177v2Z Switching applications LLC converters Boost PFC converters Description The new MDmesh™ M6 technology incorporates the most recent advancements to the well-known and consolidated MDmesh family of SJ MOSFETs. STMicroelectronics builds on the previous generation of MDmesh devices through its new M6 technology, which combines excellent RDS(on) per area improvement with one of the most effective switching behaviors available, as well as a user-friendly experience for maximum end-application efficiency. Product status link STW75N60M6-4 Product summary Order code STW75N60M6-4 Marking 75N60M6 Package TO247-4 Packing Tube DS12411 - Rev 2 - December 2018 For further information contact your local STMicroelectronics sales office. www.st.com STW75N60M6-4 Electrical ratings 1 Electrical ratings Table 1. Absolute maximum ratings Symbol Value Unit Gate-source voltage ±25 V Drain current (continuous) at TC = 25 °C 72 A Drain current (continuous) at TC = 100 °C 45 A IDM(1) Drain current (pulsed) 288 A PTOT Total power dissipation at TC = 25 °C 446 W dv/dt(2) Peak diode recovery voltage slope 15 dv/dt(3) MOSFET dv/dt ruggedness 100 Tstg Storage temperature range VGS ID TJ Parameter Operating junction temperature range V/ns -55 to 150 °C Value Unit 0.28 °C/W 50 °C/W Value Unit 1. Pulse width is limited by safe operating area. 2. ISD ≤ 72 A, di/dt = 400 A/µs, VDS(peak) < V(BR)DSS, VDD = 400 V 3. VDS ≤ 480 V Table 2. Thermal data Symbol Parameter Rthj-case Thermal resistance junction-case Rthj-amb Thermal resistance junction-ambient Table 3. Avalanche characteristics Symbol DS12411 - Rev 2 Parameter IAR Avalanche current, repetitive or not repetitive (pulse width limited by TJmax) 11 A EAS Single pulse avalanche energy (starting TJ = 25 °C, ID = IAR, VDD = 50 V) 1.4 J page 2/12 STW75N60M6-4 Electrical characteristics 2 Electrical characteristics (TC = 25 °C unless otherwise specified) Table 4. On/off-states Symbol V(BR)DSS IDSS IGSS Parameter Test conditions Drain-source breakdown voltage VGS = 0 V, ID = 1 mA Min. Typ. 600 1 VGS = 0 V, VDS = 600 V, drain current TC = 125 100 °C(1) Gate-body leakage current VDS = 0 V, VGS = ±25 V VGS(th) Gate threshold voltage VDS = VGS, ID = 250 µA RDS(on) Static drain-source on-resistance VGS = 10 V, ID = 36 A Unit V VGS = 0 V, VDS= 600 V Zero-gate voltage Max. µA ±5 µA 4 4.75 V 32 36 mΩ Min. Typ. Max. Unit - 4850 - pF - 380 - pF - 3.5 - pF 3.25 1. Defined by design, not subject to production test. Table 5. Dynamic Symbol Parameter Test conditions Ciss Input capacitance Coss Output capacitance Crss Reverse transfer capacitance Coss eq. (1) Equivalent output capacitance VGS = 0 V, VDS = 0 to 480 V - 851 - pF RG Intrinsic gate resistance f = 1 MHz open drain - 1.5 - Ω Qg Total gate charge VDD = 480 V, ID = 72 A, - 106 - nC Qgs Gate-source charge VGS = 0 to 10 V - 32 - nC Qgd Gate-drain charge (see Figure 2) - 45 - nC VGS = 0 V, VDS = 100 V, f = 1 MHz 1. Coss eq. is defined as the constant equivalent capacitance giving the same charging time as Coss when VDS increases from 0 to 80% VDSS. Table 6. Switching times Symbol td(on) tr td(off) tf DS12411 - Rev 2 Parameter Test conditions Turn-on delay time Rise time Turn-off delay time Fall time VDD = 300 V, ID = 36 A, RG = 4.7 Ω, VGS = 10 V (see Figure 1 and Figure 6) Min. Typ. Max. Unit - TBD - ns - TBD - ns - TBD - ns - TBD - ns page 3/12 STW75N60M6-4 Electrical characteristics Table 7. Source-drain diode Symbol ISD ISDM (1) (2) Parameter Test conditions Min. Typ. Max. Unit Source-drain current - 72 A Source-drain current (pulsed) - 288 A 1.6 V Forward on voltage VGS = 0 V, ISD = 72 A - trr Reverse recovery time ISD = 72 A, di/dt = 100 A/µs, - 367 ns Qrr Reverse recovery charge VDD = 60 V - 6.4 µC IRRM Reverse recovery current (see Figure 3) - 35 A trr Reverse recovery time ISD = 72 A, di/dt = 100 A/µs, - 552 ns Qrr Reverse recovery charge VDD = 60 V, TJ = 150 °C - 13.7 µC IRRM Reverse recovery current (see Figure 3) - 49.6 A VSD 1. Pulse width is limited by safe operating area. 2. Pulse test: pulse duration = 300 µs, duty cycle 1.5%. DS12411 - Rev 2 page 4/12 STW75N60M6-4 Electrical characteristics (curves) 2.1 Electrical characteristics (curves) Figure 2. Thermal impedance Figure 1. Safe operating area ID (A) GADG211120181126SOA d=0.5 tp=1 μs Operation in this area is limited by RDS(on) 10 2 0.2 tp =10 µs 0.1 tp =100 µs 10 1 10 AM09125v1 K tp =1 ms 0.05 10 -1 0.02 0.01 Single pulse, TC = 25 °C, TJ ≤ 150 °C, VGS = 10 V Zth =k *Rthj-c d=t p /t tp =10 ms Single pulse 0 tp t -2 10 -1 10 -1 10 0 10 1 VDS (V) 10 2 10 -4 10 10 -3 10 -2 10 -1 t p (s) Figure 3. Output characteristics Figure 4. Transfer characteristics Figure 5. Gate charge vs gate-source voltage Figure 6. Static drain-source on-resistance VDS (V) GADG211120181125QVG VGS (V) VDD = 480 V, ID = 72 A 600 12 Qg 500 400 10 VDS 8 Qgd Qgs 300 6 200 4 100 2 0 0 DS12411 - Rev 2 20 40 60 80 100 120 0 Qg (nC) page 5/12 STW75N60M6-4 Electrical characteristics (curves) Figure 7. Normalized on-resistance vs temperature RDS(on) (norm.) Figure 8. Normalized V(BR)DSS vs temperature V(BR)DSS (norm.) GADG051220171032RON 2.5 GADG051220171032BDV 1.10 2.0 1.05 VGS = 10 V 1.5 1.00 1.0 0.95 0.5 0.90 0 -75 -25 25 75 125 Tj (°C) 0.85 -75 -25 25 75 125 Tj (°C) Figure 10. Normalized gate threshold voltage vs temperature Figure 9. Capacitance variations C (pF) ID = 1 mA GADG051220171033CVR VGS(th) (norm.) 10 4 GADG051220171030VTH 1.1 CISS 1.0 10 3 COSS f = 1 MHz 10 2 0.9 ID = 250 µA 0.8 CRSS 10 1 0.7 10 0 10 -1 10 0 10 1 VDS (V) 10 2 Figure 11. Output capacitance stored energy EOSS (µJ) GADG051220171034EOS 0.6 -75 -25 25 75 Tj (°C) Figure 12. Source-drain diode forward characteristics VSD (V) GADG051220171033SDF 1.1 50 125 Tj = -50 °C 1.0 40 Tj = 25 °C 0.9 30 0.8 20 0.7 10 0 0 DS12411 - Rev 2 Tj = 150 °C 0.6 100 200 300 400 500 600 VDS (V) 0.5 0 10 20 30 40 50 60 70 ISD (A) page 6/12 STW75N60M6-4 Test circuits 3 Test circuits Figure 13. Switching times test circuit for resistive load Figure 14. Test circuit for gate charge behavior VDD RL RL + VD VGS 3.3 µF 2200 µF VDD IG= CONST VGS RG + pulse width D.U.T. 2200 μF PW D.U.T. 100 Ω 2.7 kΩ VG 47 kΩ GND1 (driver signal) GND2 (power) 1 kΩ GND1 AM15855v1 GND2 GADG180720181011SA Figure 15. Test circuit for inductive load switching and diode recovery times A A D.U.T. FAST DIODE Figure 16. Unclamped inductive load test circuit A L D G S L=100µH B B D 25Ω VD 3.3 µF B + 1000 µF 2200 µF 3.3 µF + VDD VDD ID G S RG D.U.T. Vi D.U.T. Pw GND2 GND1 GND1 GND2 AM15858v1 AM15857v1 Figure 18. Switching time waveform Figure 17. Unclamped inductive waveform ton V(BR)DSS td(on) VD toff td(off) tr tf 90% 90% IDM VDD 10% 0 ID VDD AM01472v1 VGS 0 VDS 10% 90% 10% AM01473v1 DS12411 - Rev 2 page 7/12 STW75N60M6-4 Package information 4 Package information In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. 4.1 TO247-4 package information Figure 19. TO247-4 package outline 8405626_2 DS12411 - Rev 2 page 8/12 STW75N60M6-4 TO247-4 package information Table 8. TO247-4 mechanical data Dim. mm Min. Typ. Max. A 4.90 5.00 5.10 A1 2.31 2.41 2.51 A2 1.90 2.00 2.10 b 1.16 b1 1.15 b2 0 0.20 c 0.59 0.66 c1 0.58 0.60 0.62 D 20.90 21.00 21.10 D1 16.25 16.55 16.85 D2 1.05 1.20 1.35 D3 24.97 25.12 25.27 E 15.70 15.80 15.90 E1 13.10 13.30 13.50 E2 4.90 5.00 5.10 E3 2.40 2.50 2.60 e 2.44 2.54 2.64 e1 4.98 5.08 5.18 L 19.80 19.92 20.10 P 3.50 3.60 3.70 1.29 1.20 P1 7.40 P2 2.40 Q 5.60 S DS12411 - Rev 2 1.25 2.50 2.60 6.00 6.15 T 9.80 10.20 U 6.00 6.40 page 9/12 STW75N60M6-4 Revision history Table 9. Document revision history Date Revision 11-Dec-2017 1 Changes Initial version Removed maturity status indication from cover page. The document status is production data. Updated schematic diagram on cover page. 07-Dec-2018 2 Updated Table 1. Absolute maximum ratings, Table 5. Dynamic and Table 7. Source-drain diode. Updated Section 2.1 Electrical characteristics (curves). Minor text changes DS12411 - Rev 2 page 10/12 STW75N60M6-4 Contents Contents 1 Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2 2 Electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2.1 Electrical characteristics (curves) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3 Test circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 4 Package information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 4.1 TO247-4 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 DS12411 - Rev 2 page 11/12 STW75N60M6-4 IMPORTANT NOTICE – PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement. Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers’ products. No license, express or implied, to any intellectual property right is granted by ST herein. Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners. Information in this document supersedes and replaces information previously supplied in any prior versions of this document. © 2018 STMicroelectronics – All rights reserved DS12411 - Rev 2 page 12/12