STW8019

IMPORTANT NOTICE Dear customer, As from August 2nd 2008, the wireless operations of STMicroelectronics have moved to a new company, ST-NXP Wireless. As a result, the following changes are applicable to the attached document. ● ● Company name - STMicroelectronics NV is replaced with ST-NXP Wireless. Copyright - the copyright notice at the bottom of the last page “© STMicroelectronics 200x - All rights reserved”, shall now read: “© ST-NXP Wireless 200x - All rights reserved”. Web site - http://www.st.com is replaced with http://www.stnwireless.com Contact information - the list of sales offices is found at http://www.stnwireless.com under Contacts. ● ● If you have any questions related to the document, please contact our nearest sales office. Thank you for your cooperation and understanding. ST-NXP Wireless www.stnwireless.com STw8009 STw8019 Mobile video DENC Features ■ Two analog outputs (10 bits DAC) with: – CVBS (Composite) output or Y/C (S-VHS) – NTSC-J, M & 4.43 & PAL-BDGHI, N, Nc, M support – 35 mA current driver 8-bit digital interface input supporting both embedded and external synchro – CCIR 601 / YCbCr 4:2:2 format – CCIR 656: 27 Mhz pixel input clock Latest Macrovision (7.1.L1) (STw8019 only) 2-wire serial MPU interface (I2C compatible) Master and slave modes TV / VCR plug insertion detection Supply voltages – 2.8V/3.3V analog – 1.8V/2.8Vdigital I/O – 1.2V/1.4V for core Power consumption – Sleep mode: 5 µW – Standby mode: 150 µW maximum – CVBS: 125 mW – Y/C: 245 mW Package – TFBGA 4x4x1.2 mm height, 0.5 mm pitch, – VFBGA 3x3x1 mm height, 0.4 mm pitch Full matrix: 7 x 7 STw8009 ■ TFBGA 4 mm x 4 mm x 1.2 mm VFBGA 3 mm x 3 mm x 1.0 mm ■ ■ ■ ■ ■ Description STw80x9 is aimed at mobile video Digital ENCoder (DENC). This device converts digital video signals into high quality analog signal compliant with TV standards, it is able to encode interlaced (in all standards) and non-interlaced (in PAL and NTSC). Featuring ultra low power consumption, it suits perfectly mobile appliances that interface occasionally with TV sets or VCRs. It is also the ideal companion for digital application processors such as ST’s Nomadik family. To minimize PCB space usage, STw80x9 features a high level of integration. STw80x9 drives directly the video input, CVBS of a TV set or the Y/C video input of a VCR through optional ESD protection devices. The 27 MHz clock and the device power management are controlled through the digital processor interface [PORn, Suspend and 2-wire I2C compatible serial MPU]. This digital processor interface also controls the STw80x9 operating modes (off, sleep, standby and active). ■ ■ ■ Applications ■ Mobile video Digital ENCoder (DENC) June 2007 Rev 6 1/65 www.st.com 1 Contents STw8009/STw8019 Contents 1 2 3 4 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Functional block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Ball/pin information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 4.1 4.2 4.3 4.4 4.5 4.6 4.7 4.8 4.9 4.10 4.11 4.12 4.13 General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Master & slave modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Auto test mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Input demultiplexor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Video timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Sub-carrier generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Luminance encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Chrominance encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Composite video signal generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 MacrovisionTM copy protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 TV/VCR plug insertion detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Power management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4.13.1 4.13.2 Operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Mode transition diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 4.14 JTAG interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 5 Control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 5.1 5.2 Register addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Description 5.2.1 5.2.2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 DENC registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Control & power management unit registers . . . . . . . . . . . . . . . . . . . . . 45 6 Bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 6.1 2 wire serial MPU control interface (I2C compatible) . . . . . . . . . . . . . . . . 47 7-bit address mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 2/65 STw8009/STw8019 Contents 10 bits address mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 6.2 YcbCr bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 7 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 7.1 7.2 7.3 Absolute maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Electrical and timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 8 9 10 Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Color test pattern waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 10.1 10.2 TFBGA 49 balls . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 VFBGA 49 balls . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 11 12 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 3/65 List of tables STw8009/STw8019 List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Table 24. Table 25. Table 26. Table 27. Table 28. Table 29. Table 30. Table 31. Table 32. Product name ball functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 NTSC and PAL timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Register addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 std1, std0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 sync2, sync1, sync0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 valrst1 and valrst0 selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 syncin_ad[1:0]. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 syncout_ad[1:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 jump, dec_ninc, free_jump . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 cfc[1:0]: color frequency control via CFC line . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 ph_rst_mode[1:0]:sub-carrier phase reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 dac2_mult[5:0]: multiplying factor on dac2_c digital signal . . . . . . . . . . . . . . . . . . . . . . . . . 35 c_mult[3:0]: multiplying factor of C digital output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Chroma main_coef_[8:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 main_del[3:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Luma_coef_[0:9] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 dac12_conf . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 dac1_multi[5:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 main_chr_del[3:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 STw80x9 addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 YcBCr data bus timing (Figure 22) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 2 wire serial MPU control interface timing (Figure 20) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Digital I/O interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Power consumption/R load = 37.5 ohm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 DAC & Video output characteristics / Rload = 37.5 ohm – F = 27 MHz – Rext = 2.4 kohm 53 TFBGA 4x4x1.2 mm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 VFBGA 3x3x1.0 mm - 49 balls - Pitch 0.4 ball 0.25 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 Order codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 4/65 STw8009/STw8019 List of figures List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. Figure 27. Figure 28. Figure 29. Application diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 STw8009 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 STw8019 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Ball layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Input data format (ITU-R656/D1 4:2:2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 PAL-BDGHI, PAL-N typical VBI waveform, interlaced mode (ITU-R625 line numbering) . 13 NTSC-M typical VBI waveforms, interlaced mode (SMTPE-524 line numbering . . . . . . . . 13 PAL-M typical VBI waveforms, interlaced mode (ITU-R/CCIR-525 line numbering) . . . . . 14 Horizontal blanked interval and active video timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Luma filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Luma filtering with 3.58 MHz trap . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Luma filtering with 4.43 MHz trap . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 1.1 MHz chroma filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 1.3 MHz chroma filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 1.6 MHz chroma filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 1.9 MHz chroma filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Mode transition diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 2-wire serial MPU control interface format (I2C compatible) / 7-bit addresses. . . . . . . . . . 48 2-wire serial MPU control interface format (I2C compatible) / 10-bit addresses. . . . . . . . . 49 2-wire serial MPU control interface timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 YcbCr bus format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Data bus timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Typical application schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 NTSC composite. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 NTSC S-video . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 PAL composite . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 PAL S-video . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 TFBGA 49 balls 4 x 4 x 1.2 mm body size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 VFBGA 49 balls 3 x 3 x 1.0 mm body size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 5/65 Overview STw8009/STw8019 1 Overview STw80x9 is aimed at mobile video Digital ENCoder (DENC). This device converts digital video signals into high quality analog signal compliant with TV standards, it is able to encode interlaced (in all standards) and non-interlaced (in PAL and NTSC). Featuring ultra low power consumption, it suits perfectly mobile appliances that interface occasionally with TV sets or VCRs. It is also the ideal companion for digital application processors such as ST’s Nomadik family. To minimize PCB space usage, the device features a high level of integration. The 35 mA high performance DAC allows direct drive of 37.5 Ω load. STw80x9 drives directly the video input, CVBS of a TV set or the Y/C video input of a VCR through optional ESD protection devices. It is powered by three voltage supplies, 2.8V/3.3V, 1.8V/2.8V and 1.2V/1.4V (VccA, VI/O, Vdd). The 27 MHz clock and the device power management are controlled through the digital processor interface [PORn, Suspend and 2-wire I2C compatible serial MPU]. This digital processor interface also controls the operating modes (off, sleep, standby and active). Figure 1. Application diagram STw80x9 Clk Video YCbCr PORn Y C/CVBS ESD protection 75 Ω 75 Ω Digital processor I2C Suspend Vdd Vo VccA Vdd Vo VccA TV set or VCR Supply Naming convention Unless clearly specified in the document, STw80x9 stands for both STw8009 and STw8019. 6/65 STw8009/STw8019 Functional block diagram 2 Figure 2. Functional block diagram STw8009 block diagram Figure 3. STw8019 block diagram 7/65 Ball/pin information STw8009/STw8019 3 Table 1. Ball E1 D2 C1 D1 G4 E4 A3 A5 A7 B7 B3 B5 C5 B4 B6 A4 G2 G7, G6, F7, F6, E7, E6, D7, D6 Ball/pin information Product name ball functions Name Vdd Gndd VddIO1 VssIO1 VddIO2 VssIO2 VccA1 VccA2 VccA3 VccA4 GNDA1 GNDA2 GNDA3 GNDA4 GNDA5 Rext CLK Type Power GND Power GND Power GND Power Power Power Power GND GND GND GND GND Analog Digital Input 1.8V/2.8V Voltage 1.2V/1.4V 0V 1.8V/2.8V 0V 1.8V/2.8V 0V 2.8V/3.3V 2.8V/3.3V 2.8V/3.3V 2.8V/3.3V 0V 0V 0V 0V 0V Description Digital core chip supply Digital core chip ground Digital I/O supply Digital I/O ground Digital I/O supply Digital I/O ground DAC2 matrix analog power supply DAC1 matrix analog power supply 2.8/3.3 V digital feature supply 2.8 /3.3 V digital feature supply DAC2 ground DAC1 ground 2.8 /3.3 V digital feature ground Rext ground connection Analog ground DAC current reference setting 27 MHz master pixel clock (pixclk) Time multiplexed 4:2:2 luminance and chrominance data as defined in CCIR 601 and CCIR 656 (excepted for TTL input signals) Horizontal synchronization signal: - Input in slave mode, except when sync is extracted from YcbCr data - Output in master mode and when sync is extracted from YcbCr signal. Vertical Synchronization – Odd/Even signal: - Input in slave mode, except when sync is extracted from YcbCr data - Output in master mode and when sync is extracted from YcbCr signal. 2 wire serial MPU data line 2 wire serial MPU clock Device address selection Power On Reset (Active low) Suspend input YCbCr[0:7] Digital Input 1.8V/2.8V G5 Hsync Digital I/O 1.8V/2.8V F5 Vsync Odd/Even Digital I/O 1.8V/2.8V F3 G3 E3 C7 F2 SDA SCL Add PORn Suspend Digital I/O Digital Input Digital input Digital input Digital input 1.8V/2.8V 1.8V/2.8V 1.8V/2.8V 1.8V/2.8V 1.8V/2.8V 8/65 STw8009/STw8019 Table 1. Ball A2 A6 B1 B2 C2 C3 D4 D3, F1, E2 F4 Ball/pin information Product name ball functions (continued) Name C/CVBS Y TDI TDO TCK TMS Test tst_ana[0:2] PlugDet Type Analog output Analog output Digital input Digital output Digital input Digital input Digital input Digital input Digital input 1.8V/2.8V 1.8V/2.8V 1.8V/2.8V 1.8V/2.8V 1.8V/2.8V 1.8V/2.8V 1.8V/2.8V Voltage Description The output can be selected to be composite video or chroma signal for s-video. Luminance signal for s-video JTAG test data in If not used, connected to GND JTAG test data out If not used, left open JTAG test clock If not used, connected to GND JTAG test mode select If not used, connected to GND Put the device in test mode If not used, connected to GND DENC test If not used, connected to GND TV / VCR plug connection detection / CMOS input Figure 4. Ball layout 1 A 2 C/CVBS 3 VccA1 4 Rext 5 VccA2 6 Y 7 VccA3 B TDI TDO GNDA1 GNDA4 GNDA2 GNDA5 VccA4 C Vdd_IO1 TCK TMS GNDA3 PORn D Vss_IO1 Gndd tst_ana[0] Test YCbCr[7] YCbCr[6] E Vdd tst_ana[2] Add Vss_IO2 YCbCr[5] YCbCr[4] F tst_ana[1] Suspend SDA PlugDet Vsync YCbCr[3] YCbCr[2] G CLK SCL Vdd_IO2 Hsync YCbCr[1] YCbCr[0] 9/65 Functional description STw8009/STw8019 4 4.1 Functional description General STw80x9 operates either in master mode where it supplies all sync signal or in slave mode. The digital input is an 8-bit bus carrying Y, Cb and Cr at 13.5 MHz. Input samples are latched in on the rising edge of the clock input signal. STw80x9 is able to encode interlaced (in all standards) and non interlaced (in PAL and NTSC) video. STw80x9 outputs interlaced or non-interlaced video in PAL-B,D,G,H,I,PAL-N,PAL-M or NTSC-M standards (“NTSC-4.43” is also possible). The burst sequences are internally generated, subcarrier generation being performed numerically with the 27 MHz as reference. 4-frame bursts are generated for PAL or 2-frame bursts for NTSC. Rise and fall times of synchronization tips and burst envelope are internally controlled according to the relevant ITU_R and SMPTE recommendations. 4.2 Master & slave modes In master mode, STw80x9 supplies Hsync and Odd/Even sync signals (with independently programmable polarities) to drive other blocks. STw80x9 starts encoding and counting clock cycles as soon as the master mode has been loaded into the control register (Reg 0). Configuration bits “Syncout_ad[1:0]” (Reg 4) allow to shift the relative position of the sync signals by up to 3 clock cycles to cope with any YcbCr phasing. In slave modes, several modes are available, Odd/Even+Hsync based, Vsync+Hsync based, Odd/Even-only based, Vsync-only based or Sync-in-data based. 4.3 Auto test mode An auto test mode is available, which causes STw80x9 to produce a color bar pattern, in the appropriate standard, independently from the video input. 4.4 Input demultiplexor The incoming YcbCr 4:2:2 data are demultiplexed into chroma information stream, a “bluedifference” and a “red-difference”, and a luma information stream. Incoming data bits are treated as blue, red or luma samples according to their relative position with respect to the sync signals. Brightness, Saturation and Contrast are then performed on demultiplexed data. The ITU-R601 recommendation defines the black luma level as Y=16dec and the maximum white luma level as Y=235dec. Similarly it defines 255 quantification levels for the color difference components (Cr, Cb) centered around 128. Accordingly, incoming YcbCr samples can be saturated. In this case STw80x9 provides a saturation limitation feature to avoid having heavily saturated signal before digital to analog conversion and to avoid generating a distorted signal at STw80x9 CVBS or Y/C outputs. 10/65 STw8009/STw8019 Functional description 4.5 Video timing The DENC outputs video in PAL-B,D,G,H,I, PAL-N, PAL-M or NTSC-J, M standards (‘NTSC4.43’ is also possible). The burst sequences are internally generated, subcarrier generation being performed numerically with PIX_CLK as reference. 4-frame bursts are generated for PAL or 2-frame bursts for NTSC. Rise and fall times of synchronization tips and burst envelope are internally controlled according to the relevant ITU-R and SMPTE recommendations. Figure 5, 6, 7 and 8 depict typical VBI waveforms. It is possible to allow encoding of incoming YCrCb data on those lines of the VBI that do not bear line sync pulses or pre/post-equalization pulses (Figure 5, 6, 7 and 8). This mode of operation is referred to as “partial blanking” and is the default set-up. It allows to keep in the encoded waveform any VBI data present in digitized form in the incoming YCrCb stream. Alternatively, the complete VBI may be fully blanked, so no incoming YCrCb data encoded on these lines. The ‘complete’ VBI comprises of the following lines: – – for 525/60 systems (SMPTE line numbering convention): lines 1 to 19 and second half of line 263 to line 282 for 625/50 systems (CCIR line numbering convention): second half of line 623 to line 22 and lines 311 to 335 for 525/60 systems (SMPTE line numbering convention): lines 1 to 9 and second half of line 263 to line 272 for 625/50 systems (CCIR line numbering convention): second half of line 623 to line 5 and lines 311 to 318 The ‘partial’ VBI consists of: – – Full or partial blanking is controlled by configuration bit ‘blkli in configuration register1’. Note: line 282 in 525/60/SMPTE systems is either fully blanked or fully active. line 23 in 625/60/CCIR systems is always fully active. In an ITU-R656-compliant digital TV line, the active portion of the digital line is the portion included between the SAV (Start of Active Video) and EAV (End of Active Video) words. However, this digital active line starts somewhat earlier and may end slightly later than the active line usually defined by analog standards. The DENC permits two approaches: ● ● Encodes the full digital line (720 pixels / 1440 clock cycles). In this case, the output waveform will reflect the full YCrCb stream included between SAV and EAV. Drops some YCrCb samples at the extremities of the digital line so that the encoded analog line fits within the ‘analog’ ITU-R/SMPTE specifications. Selection between these two modes of operation is performed with bit ‘aline’ in configuration register 4. In all cases, the transitions between horizontal blanking and active video are shaped to avoid too steep edges within the active video. Figure 11 on page 15 gives timings concerning the horizontal blanking interval and the active video interval. 11/65 Functional description Figure 5. Input data format (ITU-R656/D1 4:2:2) STw8009/STw8019 0H 4T E A V 128T NTSC, PAL M 137T 146T (PAL M) 128T PAL B, G, H, I, N SECAM 151T (145T in SECAM) 4T S A V 1440T 1716T Digital active line E A V 1440T 1728T Digital active line 115T Square pixel 525 / 60 system 131T 1560T 1280T Digital active line Square pixel 625 / 50 system 139T 1888T 169T 1536T Digital active line T = clock period PAL, NTSC: 37.037 ns Note: The burst envelope shown here indicates the location from which the first subcarrier positive zero crossing is sought (with respect to the 0H reference). The normal burst always starts with such a positive zero crossing. 12/65 STw8009/STw8019 Figure 6. Functional description PAL-BDGHI, PAL-N typical VBI waveform, interlaced mode (ITU-R625 line numbering) 0V IV A B 308 309 310 311 312 313 314 315 Full VBI1 316 317 318 319 A 320 Partial VBI1 I 621 622 623 624 625 1 2 Partial VBI2 II 3 Full VBI2 4 5 6 A 7 22 23 308 309 310 311 312 313 314 315 316 317 318 A 317 335 B 336 III 621 622 623 624 625 1 2 I II 3 4 5 6 7 8 C III IV 0V : Frame synchronization reference I, II, III, IV : 1st and 5th, 2nd and 6th, 3rd and 7th, 4th and 8th fields Burst phase : nominal value +135° A: Burst phase : nominal value -135° B: Burst suppression internal C: Figure 7. NTSC-M typical VBI waveforms, interlaced mode (SMTPE-524 line numbering Full VBI1 Partial VBI1 1 2 3 4 5 6 7 8 9 10 18 19 H H Full VBI2 Partial VBI2 0.5H H 262 263 264 265 266 267 268 269 270 271 272 273 282 0.5H VBI3 525 1 2 3 4 5 6 7 8 H H 9 10 18 19 VBI4 263 264 265 266 267 268 269 270 271 272 273 282 13/65 Functional description Figure 8. F' STw8009/STw8019 PAL-M typical VBI waveforms, interlaced mode (ITU-R/CCIR-525 line numbering) F F' F 0V Full VBI1 Partial VBI1 I A B 519 F 520 F' 521 F 522 523 524 525 1 2 Partial VBI2 II 3 Full VBI2 4 5 6 7 8 A 9 16 B 17 257 F F' 258 F 259 260 261 262 263 264 265 266 267 268 269 270 A 271 279 B 280 III 519 F' 520 F 521 522 523 524 525 1 2 3 4 5 6 7 A 8 B 9 IV 257 258 259 260 261 262 263 264 I II 265 266 267 268 269 270 271 272 C III IV 0V : Frame synchronization reference I, II, III, IV : 1st and 5th, 2nd and 6th, 3rd and 7th, 4th and 8th fields Burst phase : nominal value +135° A: Burst phase : nominal value -135° B: Burst suppression internal C: Figure 9. Horizontal blanked interval and active video timings Horizontal blanking interval Active video d 0H Full digital line encoding (720 pixels - 1440 T) ‘Analog’ line encoding a b1 (bit aline = 0) b2 (bit aline = 1) c1 (bit aline = 0) c2 (bit aline = 1) 14/65 STw8009/STw8019 Table 2. NTSC and PAL timings PAL-BDGHI 5.54 μs (A-type) 5.66 μs (B-type) 1.3 μs 1.52 μs 9.6 μs 10.48 μs PAL-N 5.54 μs (A-type) 5.66 μs (B-type) 1.3 μs 1.52 μs 9.6 μs 10.48 μs Functional description NTSC-M a(1) b1 b2 c1 c2 d 5.38 μs (even lines) 5.52 μs (odd lines) 1.56 μs 1.56 μs 8.8 μs 9.41 μs 9 cycles of 3.58MHz PAL-M 5.73 μs (A-type) 5.87 μs (B-type) 1.56 μs 1.56 μs 8.8 μs 9.41 μs 9 cycles of 3.58MHz 10 cycles of 4.43MHz 9 cycles of 3.58MHz 1. These are typical values. Actual values will depend on the static offset programmed for subcarrier generation 4.6 Sub-carrier generation A Direct Digital Frequency Synthesizer (DDFS) generates the required color sub-carrier frequency using a 24-bit phase accumulator. Sub-carrier frequency is programmable with a 1.6 Hz step. 4.7 Luminance encoding The luminance that is added to the chrominance to create the composite CVBS signal can be trap-filtered at 3.58 MHz (NTSC) or 4.43 MHz (PAL). This supports application oriented towards low-end TV sets which are subject to cross-color. A 7.5 IRE pedestal can be programmed if needed with all standards. This allows in particular to encode Argentinian and non-Argentinian PAL-N, or Japanese NTSC. A programmable delay can be inserted on the luminance path to offset any chroma/luma delay introduced by off-chip filtering. STw80x9 output signals are IF modulated in NTSC M standard so that a sound notch filter is required. The notch filter which is on the Luma path is defined by a set of coefficients and is implemented in the STw80x9 as default values. The set is also programmable. 15/65 Functional description Figure 10. Luma filtering STw8009/STw8019 Amplitude (dB) Frequency (MHz) Figure 11. Luma filtering with 3.58 MHz trap Frequency (MHz) 16/65 STw8009/STw8019 Figure 12. Luma filtering with 4.43 MHz trap Functional description Frequency (MHz) 4.8 Chrominance encoding Chroma components are computed from demultiplexed Cb, Cr samples. Before modulating the subcarrier, the chroma components are band-limited and interpolated at pixel clock rate. A set of 4 different filters is available for chroma filtering to suit a wide variety of applications in the different standards and filters recommended by ITU-R 624-4 and SMPTE170-M. The available –3dB bandwidths are 1.1, 1.3, 1.6 and 1.9 MHz. Narrow bandwidths are useful against cross-luminance artifacts while wide bandwidths allow to keep higher chroma contents. Figure 13. 1.1 MHz chroma filter Amplitude (dB) Frequency (MHz) 17/65 Functional description Figure 14. 1.3 MHz chroma filter STw8009/STw8019 Amplitude (dB) Frequency (MHz) Figure 15. 1.6 MHz chroma filter Amplitude (dB) Frequency (MHz) Figure 16. 1.9 MHz chroma filter Amplitude (dB) Frequency (MHz) 18/65 STw8009/STw8019 Functional description 4.9 Composite video signal generation The composite video signal is created by adding the luminance and the chrominance components. A saturation function is included in the adder to avoid overflow errors. 4.10 MacrovisionTM copy protection The chrominance luminance and composite video signals and RGB video signals can be altered according to the MacrovisionTM copy protection Revision 7.01 and Revision 6.1. This process is controlled via the I²C bus. A programming document is available to those customers who have executed a license or a non-disclosure agreement with Macrovision Corporation. For all relevant information or document please contact: Macrovision Corporation: 2830 De La Cruz Blvd. Santa Clara, CALIFORNIA 95050 USA www.macrovision.com 4.11 TV/VCR plug insertion detection Plugdet ball is used to detect the connection of a TV or a VCR. The host can read the status in a dedicated register in standby and active modes. 4.12 DAC STw80x9 outputs generate Composite video signal on one output or Y/C video signals on two outputs. Two embedded 10-bit DACs allow the STw80x9 to directly drive 37.5 Ohms loads on each output. 4.13 Power management Power management includes power supplies, reset signals, clock gating and a set of dedicated pins and registers. Power management is used to set the STw80x9 in different operating modes. 19/65 Functional description STw8009/STw8019 4.13.1 Operating modes STw80x9 can be in the following operating modes. ● OFF – – 1.2V/1.4V, 1.8V/2.8V, 2.8V/3.3V are not present. All values from STw80x9 registers are lost. 1.2V/1.4V, 1.8V/2.8V, 2.8V/3.3V are present. The suspend signal is active. The DACs are in their minimum power consumption mode. All values from the STw80x9 registers are lost. The 27 MHz pixel clock must be activated All power supplies are present: 1.2V/1.4V, 1.8V/2.8V, 2.8V/3.3V. The 27 MHz pixel clock must be activated. The suspend signal is inactive. STw80x9 is set in standby mode by programming the Control and power Management Unit registers (Reg 128 to 132) through the 2 wire serial MPU interface. STw80x9 saves the register values. The other registers (Reg 00 to 109) are not accessible in this mode. The DACs are in their minimum power consumption mode. This mode is a low power state that enables a fast switching to active mode. All power supplies are present: 1.2V/1.4V, 1.8V/2.8V, 2.8V/3.3V. STw80x9 receives the 27 MHz pixel clock. The suspend signal is inactive. STw80x9 is placed in active mode by programming the control and power management unit registers (Reg 128 to 132), through the 2 wire serial MPU interface. STw80x9 saves the register values. The 27 MHz pixel clock is distributed in all STw80x9. ● Sleep – – – – – ● Standby – – – – – – – ● Active – – – – – The DACs are supplied by the 2.8 /3.3 V and can be individually activated or deactivated. For example only one DAC in CVBS output and both DACs in Y/C output. 20/65 STw8009/STw8019 Functional description 4.13.2 Mode transition diagram The following mode transition diagram shows the main possible transitions between the modes and the actions. Figure 17. Mode transition diagram No Power supply applied Registers values lost All supplies are applied but STw8009 suspend is asserted Register values lost DAC in low power mode OFF A PORn reset occurs A PORn reset occurs after the 1.2V, 1.8V after CLK27M & 1.8 V and the 1.2 V have been applied have been applied (see AN2347). Sleep STw8009 looses all its registers and configuration when entering Sleep mode Suspend = « 0 » Suspend = « 1 » Standby No need to reset or Registers maintained Power consumption reduced DENC clock gated DACs in low power Normal operation All functions available DACs dynamically used on demand Active By Sw reconfigure DENC in either direction Transitions to OFF mode The possible transitions are indicated in Figure 17: Mode transition diagram10 in dotted lines. No internal data needs to be saved and the STw80x9 can be turned OFF from any mode. The only restriction is to comply with the power supply rules described here after. Transition from OFF mode to Sleep mode then to Active mode Power up must be done by starting from OFF to Sleep mode and then from Sleep to Active mode. Sleep to Standby is not possible. The host sends the order for the STw80x9 to switch from Sleep to Active mode by releasing Suspend ball. The device then generates a reset sequence to the DENC part. Transition from Active mode to Sleep mode In Sleep mode, DENC is not powered on. When Suspend signal changes from « 0 » to « 1 », the device goes from Active to Sleep mode and an internal Reset signal is generated by the Control Power Unit management to the DENC part. This signal has a 6 pixclk duration (pixclk = 27 MHz). 21/65 Functional description STw8009/STw8019 Transition between Standby and Active modes Transitions between these two modes are applied by software configuration through I2C interface. Supply management At power up, supplies must be applied according to the following sequence: VddIO1, VddIO2 (1.8V/2.8V) then, Vdd (1.2V/1.4V) then, VccA1, VccA2, VccA3, VccA4 (2.8V/3.3V) and removed according to the following sequence: VccA1, VccA2, VccA3, VccA4 (2.8V/3.3V) then, Vdd (1.2V/1.4V) then, VddIO1, VddIO2 (1.8V/2.8V) 4.14 JTAG interface To ease the integration of STw80x9 in its system application, a JTAG interface is available. 22/65 STw8009/STw8019 Control registers 5 5.1 Table 3. Name Control registers Register addresses Register addresses Type N° Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 DENC registers configuration0 configuration1 configuration2 configuration3 configuration4 configuration5 configuration6 configuration7 configuration8 Status increment_dfs increment_dfs increment_dfs phase_dfs phase_dfs dac2mult reserved line_reg line_reg line_reg Reserved reserved ... reserved c_mult & ttx Brightness Contrast Saturation Chroma_coef_0 Chroma_coef_1 Chroma_coef_2 R/W R/W R/W R/W R/W R/W R/W R/W R/W R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R xxx ... xxx R/W R/W R/W R/W R/W R/W R/W 00 01 02 03 04 05 06 07 08 09 10 11 12 13 14 17 20 21 22 23 24 45 ... 63 65 69 70 71 72 73 74 std1 blkli nintrl main_ entrap syncin_ad1 selrst_inc softreset [0] ph_rst_ mode1 hok d23 d15 d7 xxx o21 std0 flt1 enrst trap_4.43 syncin_ad0 bkdac2 jump [0] ph_rst_ mode0 atfr d22 d14 d6 xxx o20 d21 d13 d5 xxx o19 d20 d12 d4 xxx o18 sync2 flt0 bursten [0] sync1 sync_ok xxx [0] sync0 coki selrst main_del_ en aline [0] cfc1 [0] blk_all fldct2 d19 d11 d3 xxx o17 polh setup_main rstosc_buf val_422_ck _mux hue_en [0] cfc0 bypass_ sync_corr xxx flsct1 d18 d10 d2 xxx o16 polv [0] valrst1 xxx xxx [0] [0] [0] xxx fldct0 d17 d9 d1 o23 o15 [1] xxx ltarg2 lref3 xxx ... xxx [0] b1 c1 s1 c0(1) c1(1) c2(1) freerun [0] valrst0 [0] xxx dacinv maxdyn [0] xxx jump d16 d8 d0 o22 o14 [0] xxx ltarg1 lref2 xxx ... xxx bcs_en_main b0 c0 s0 c0(0) c1(0) c2(0) syncout_ad syncout_ad 1 0 bkdac1 dec_ninc [0] xxx [0] free_jump xxx val_422_ mux dac2_mult5 dac2_mult4 dac2_mult3 dac2_mult2 dac2_mult1 dac2_mult0 xxx ltarg8 ltarg0 lref1 xxx ... xxx c_mult3 b7 c7 s7 flt_s xxx xxx xxx ltarg7 lref8 lref0 xxx ... xxx c_mult2 b6 c6 s6 plg_div1 c8(8) c2(6) xxx ltarg6 lref7 xxx ... xxx c_mult1 b5 c5 s5 plg_div0 c1(5) c2(5) xxx ltarg5 lref6 xxx ... xxx c_mult0 b4 c4 s4 c0(4) c1(4) c2(4) xxx ltarg4 lref5 xxx ... xxx [0] b3 c3 s3 c0(3) c1(3) c2(3) xxx ltarg3 lref4 xxx ... xxx xxx b2 c2 s2 c0(2) c1(2) c2(2) 23/65 Control registers Table 3. Name Chroma_coef_3 Chroma_coef_4 Chroma_coef_5 Chroma_coef_6 Chroma_coef_7 Chroma_coef_8 configuration9 luma_coef_0 luma_coef_1 luma_coef_2 luma_coef_3 luma_coef_4 luma_coef_5 luma_coef_6 luma_coef_7 luma_coef_8 luma_coef_9 configuration11 configuration12 configuration13 hue_control dac1_mult Chroma_delay Chroma_delay_ en STw8009/STw8019 Register addresses Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W N° 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 93 94 95 105 106 108 109 Bit7 xxx c4(7) c5(7) c6(7) c7(7) c8(7) main_del3 xxx l9(9) l6(8) l7(8) l4(7) l5(7) l6(7) l7(7) l8(7) l9(7) [0] [0] [0] hue_cont (7) [0] - Bit6 c3(6) c4(6) c5(6) c6(6) c7(6) c8(6) main_del2 xxx l9(8) l2(6) l3(6) l4(6) l5(6) l6(6) l7(6) l8(6) l9(6) [0] [0] [0] hue_cont (6) [0] - Bit5 c3(5) c4(5) c5(5) c6(5) c7(5) c8(5) main_del1 l8(8) l1(5) l2(5) l3(5) l4(5) l5(5) l6(5) l7(5) l8(5) l9(5) [1] [0] dac12_conf hue_cont (5) Bit4 c3(4) c4(4) c5(4) c6(4) c7(4) c8(4) main_del0 l0(4) l1(4) l2(4) l3(4) l4(4) l5(4) l6(4) l7(4) l8(4) l9(4) [0] [0] [0] hue_cont (4) Bit3 c3(3) c4(3) c5(3) c6(3) c7(3) c8(3) xxx l0(3) l1(3) l2(3) l3(3) l4(3) l5(3) l6(3) l7(3) l8(3) l9(3) xxx [0] [0] hue_cont (3) Bit2 c3(2) c4(2) c5(2) c6(2) c7(2) c8(2) plg_div_y1 l0(2) l1(2) l2(2) l3(2) l4(2) l5(2) l6(2) l7(2) l8(2) l9(2) main_if_del ennotch [0] hue_cont (2) Bit1 c3(1) c4(1) c5(1) c6(1) c7(1) c8(1) plg_div_y0 l0(1) l1(1) l2(1) l3(1) l4(1) l5(1) l6(1) l7(1) l8(1) l9(1) xxx [0] [0] hue_cont (1) Bit0 c3(0) c4(0) c5(0) c6(0) c7(0) c8(0) flt_ys l0(0) l1(0) l2(0) l3(0) l4(0) l5(0) l6(0) l7(0) l8(0) l9(0) xxx xxx [1] hue_cont(0) dac1_mult0 main_chr_del 0 main_chr_ del_en dac1_mult5 dac1_mult4 dac1_mult3 dac1_mult2 dac1_mult1 [0] [0] main_chr_ del3 main_chr_ del2 [0] main_chr_ del1 [0] Control & power management unit registers Cpmu_conf0 Cpmu_conf1 dac2ctrl dac1ctrl Plugdet I_test0 R/W R/W R/W R/W R R/W 128 129 130 131 132 133 poff1 poff2 notzero-d1 notzerod2 standby cpmuswrst pedestalOnd 1 pedestalOnd 2 loadD - 24/65 STw8009/STw8019 Control registers 5.2 Caution: Description (*) = DEFAULT mode when not_reset pin is active (LOW level) All binary values quoted should be understood as MSB........LSB 5.2.1 DENC registers REGISTER 0 content default std1 1 configuration0 std0 0 sync2 0 Address: 0x0000 sync1 1 sync0 0 Type: R/W polh 0 polv 1 freerun 0 Table 4. std1 0 0 (*) 1 1 std1, std0 std0 0 1 0 1 PAL BDGHI PAL N (see bit set-up) NTSC M(1) PAL M Standard selected 1. Standard on hardware reset is NTSC; any standard modification selects automatically the right parameters for correct subcarrier generation. Table 5. sync2 0 0 (*) 0 1 1 1 1 sync2, sync1, sync0 sync1 0 0 1 0 0 1 1 sync0 0 1 0 0 1 0 1 Configuration ODDEV-only based SLAVE mode (frame locked) ‘F’ based SLAVE mode (frame locked) ODDEV+HSYNC based SLAVE mode (line locked) VSYNC-only based SLAVE mode (frame locked)(1) VSYNC+HSYNC based SLAVE mode (line locked) MASTER mode AUTOTEST mode (colour bar pattern) 1. In VSYNC-only based slave mode (sync[2:0]=”100”), HSYNC is nevertheless needed as an input. polh: synchro: active edge of HSYNC selection (when input) or polarity of HSYNC (when output) (*) 0 = HSYNC is a negative pulse (128 Tpix_clk wide) or falling edge is active 1 = HSYNC is a positive pulse (128 Tpix_clk wide) or rising edge is active polv: synchro: active edge of ODDEV/VSYNC selection (when input) 0 = falling edge of ODDEV flags start of field1 (odd field) or VSYNC is active low (*) 1 = rising edge of ODDEV flags start of field1 (odd field) or VSYNC is active high 25/65 Control registers freerun: (*) 0 = disabled 1 = enabled STw8009/STw8019 Note: This bit is taken into account in ODDEV-only or VSYNC-only based slave modes and is irrelevant for other synchronization modes. REGISTER 1 content default blkli 0 configuration1 flt1 1 flt0 0 Address: 0x0001 sync_ok 0 coki 0 Type: R/W setup_ main 1 [0] [0] blkli: Vertical Blanking Interval selection for active video lines area (*) 0 = (‘partial blanking’) Only the following lines inside Vertical Interval are blanked NTSC-M: PAL-M: Other PAL: NTSC-M: PAL-M: Other PAL: lines [1; 9], [263(half); 272] (525-SMPTE) lines [523; 6], [260(half); 269] (525-CCIR) lines [623(half); 5], [311; 318] (625-CCIR) lines [1; 19], [263(half); 282] (525-SMPTE) lines [523; 16], [260(half); 279] (525-CCIR) lines [623(half); 22], [311; 335] (625-CCIR) 1 = “full blanking” All lines inside VBI are blanked flt[1:0]: U/V Chroma filter bandwidth selection Table 6. flt1 0 0 (*) 1 1 Register 1 flt0 0 1 0 1 3dB bandwidth f-3dB=1.1MHz f-3dB=1.3MHz f-3dB=1.6MHz f-3dB=1.9MHz Typical application low def NTSC filter low def PAL filter high def. NTSC filter (ATSC compliant) & PAL M/N (ITU-R 624.4 compliant) high def. PAL filter: Rec 624 - 4 for PAL BDG/I compliant. sync_ok: availability of sync signals (analog and digital) in case of input synchronization loss with no free-run active (i.e. freerun=0) (*) 0 = no synchro output signals 1 = output synchro signals available on YS, CVBS and, when applicable, HSYNC (if output port), ODDEV (if output port): i.e same behavior as free-run except that video outputs are blanked in the active portion of the line. coki: color killer (*) 0 = color ON 1 = color suppressed on CVBS output signal (CVBS=YS) but color still present on C output. For color suppression on chroma DAC ‘C’, see register 5 bit bkdac1. 26/65 STw8009/STw8019 Control registers setup_main: pedestal 0 = Blanking level and black level are identical on all lines. (e.g.: Argentinian PAL-N, Japan NTSC-M, PAL-BDGHI) (*) 1 = Black level is 7.5 IRE above blanking level on all lines outside VBI (e.g. Paraguayan and Uruguayan PAL-N). In all cases, gain factor is adjusted to obtain the required levels for chrominance. Note: Depending on the different output configurations chosen by programming bit from dac12_conf, pedestal is automatically selected on it. REGISTER 2 content default nintrl 0 configuration2 enrst 0 bursten 1 Address: 0x0002 xxx 0 selrst 0 Type: R/W rstosc_ buf 0 valrst1 0 valrst0 0 nintrl: non-interlaced mode select (*) 0 = interlaced mode (625/50 or 525/60 system) 1 = non-interlaced mode(2x312/50 or 2x262/60 system) enrst: cyclic update of DDFS phase (*) 0 = no cyclic subcarrier phase reset 1 = cyclic subcarrier phase reset depending of valrst1 and valrst0 (see below) bursten: chrominance burst control 0 = burst is turned off on CVBS, chrominance output is not affected (*) 1 = burst is enabled selrst: selects set of reset values for Direct Digital Frequency Synthesizer accumulator (*) 0 = hardware reset values for phase of subcarrier oscillator (see description of registers 13 and14 for values) 1 = loaded reset values selected (see contents of registers 13 and 14) rstosc_buf: software phase reset of DDFS (Direct Digital Frequency Synthesizer) buffer (*) 0 1 = when a 0-to-1 transition occurs either the hard-wired default phase value or the value loaded in Reg. 13-14 (according to bit ‘selrst’) is put to the phase buffer. This value is then loaded into accumulator (phase of sub-carrier) when the bits ‘ph_rst_mode’ from register 8 are programmed or when standard changes or when a soft reset occur. Note: Bit ‘rstosc_buf’ is automatically set back to ‘0’ after the buffer is loaded. valrst [1:0] Note: valrst[1:0] is taken into account only if bit ‘enrst’ is set. 27/65 Control registers Table 7. valrst1 and valrst0 selection valrst0 0 1 0 1 selection Automatic reset of the oscillator every line Automatic reset of the oscillator every 2nd field Automatic reset of the oscillator every 4th field Automatic reset of the oscillator every 8th field STw8009/STw8019 valrst1 (*) 0 0 1 1 Resetting the oscillator means forcing the value of the phase accumulator to its nominal value to avoid accumulating errors due to the finite number of bits used internally. The value at which the accumulator is reset is either the hard-wired default phase value or the value loaded in Reg. 13-14 (according to bit ‘selrst’) at which a 00, 900, 1800, or 2700 correction is applied according to the field and line at which the reset is performed. REGISTER 3 content default main_ entrap 0 configuration3 trap_4.43 0 [0] [0] Address: 0x0003 Type: R/W xxx 0 [0] main_del_ val_422_ en ck_ mux 0 0 main_entrap: enable trap filter (*) 0 = trap filter disabled 1 = trap filter enabled trap_4.43: trap filter centered frequency value selection (*) 0 = trap filter centered around 3.58 MHz 1 = trap filter centered around 4.43 MHz Note: ‘trap_4.43’ is taken into account only if bit ‘main_entrap’ is set. main_del_en: Enable chroma to luma delay programming on cvbs output: (*) 0 = disabled (DENC automatically set this delay) 1 = enabled (chroma to luma delay is programmed by del(3:0) bits from register 81. Note: This delay affects only the cvbs output. The component outputs Y/C remain unaffected. Refer to register 109 to program chroma to luma delay on Y/C output. val_422_ck_mux: should be programmed to “0” only. 28/65 STw8009/STw8019 Control registers REGISTER 4 content default configuration4 syncin_ ad1 0 syncin_ ad0 0 Address: 0x0004 aline 0 Type: R/W hue_en 0 xxx 0 xxx 0 syncout_ syncout_ ad1 ad0 0 0 syncin_ad[1:0]: Adjustment of incoming sync signals. Used to insure correct interpretation of incoming video samples as Y, Cr or Cb when the encoder is slaved to incoming sync signals (inc. ‘F/H’ flags stripped off ITU-R656/D1 data). Table 8. syncin_ad[1:0] syncin_ad0 0 1 0 1 Internal delay undergone by incoming sync nominal* +1 pix_clk +2 pix_clk +3 pix_clk syncin_ad1 (*) 0 0 1 1 syncout_ad[1:0]: Adjustment of outgoing sync signals. Used to ensure correct interpretation of incoming video samples as Y, Cr or Cb when the encoder is master and supplies sync signals. Table 9. syncout_ad[1:0] syncout_ad0 0 1 0 1 Delay added to sync signals before they are output nominal* +1 pix_clk +2 pix_clk +3 pix_clk syncout_ad1 (*) 0 0 1 1 aline: video active line duration control (*) 0 = Full digital video line encoding (720 pixels - 1440 clock cycles) 1 = Active line duration follows ITU-R/SMPTE ‘analog’ standard requirements hue_en: Enables variance in phase of the subcarrier, as programmed in register_105, during active video with respect to the phase of the subcarrier during the color burst. Once set, this bit is automatically reset to ‘0’. (*) 0 = Disabled 1 = Enabled 29/65 Control registers STw8009/STw8019 REGISTER 5 content default selrst_ inc 0 configuration5 bkdac2 0 bkdac1 0 Address: 0x0005 Type: R/W dacinv [0] [0] [0] [0] 0 selrst_inc: Choice of Digital Frequency Synthesizer increment after soft reset or when ph_rst_mode = ‘01’ . See Register 8. (*) 0 = hard wired value (depending on TV standard) 1 = soft (value from registers 10 to 12) bkdacN: blanking of DACs (N = 1 or 2) (*) 0 = DAC N in normal operation 1 = DAC N input code forced to black level for C output or blanking level for Y or CVBS output depending of dac12_conf bit of configuration13 register. dacinv: ‘Inverts’ DAC codes to compensate for an inverting output stage in the application (*) 0 = non inverted DAC inputs (outputs) 1 = inverted DAC inputs (outputs) REGISTER 6 content default configuration6 softreset 0 jump 0 dec_ninc 0 Address: 0x0006 free_ jump 1 cfc1 0 Type: R/W cfc0 0 [0] maxdyn 0 softreset: software reset (*) 0 = no reset 1 = software reset Note: Bit ‘softreset’ is automatically reset after internal reset generation. Software reset is active during 4 PIX_CLK periods. When softreset is activated, all the device is reset as with hardware reset except for the first nine user registers (registers 0 to 8: configurations).Registers 10 up to 14 (increment and phase of oscillator), 25-30, 31-33 and 39-42 are never reset (hard/soft). Table 10. jump jump, dec_ninc, free_jump dec_ ninc free_ jump update mode Normal mode (no line skip/insert capability) ITU-R (CCIR): 313/312 or 263/262 non-interlaced: 312/312 or 262/262 Manual mode for line insert (“dec_ninc”=0) or skip (“dec_ninc”=1) capability. Both fields of all the frames following the writing of this value are modified according to “lref” and “ltar” bits of registers 2122-23 (by default, “lref”=0 and “ltar”=1 which leads to normal mode above). 0 0 0 (*) 0 x 1 30/65 STw8009/STw8019 Table 10. jump Control registers jump, dec_ninc, free_jump dec_ ninc free_ jump update mode Automatic line insert mode. The 2nd field of the frame following the writing of this value is increased. Line insertion is done after line 245 in 525/60 and after line 290 in 625/50. “lref” and “ltar” are ignored.(1) Automatic line skip mode. The 2nd field of the frame following the writing of this value is decreased. Line suppression is done after line 245 in 525/60 and after line 290 in 625/50. “lref” and “ltar” are ignored.(1) Not to be used. 1 0 0 1 1 0 1 1. x 1 Two lines are skipped (inserted) in 525/60 and four lines in 625/50 standards Note: bit “jump” is automatically reset after use. Table 11. cfc1 (*) 0 0 1 1 cfc[1:0]: color frequency control via CFC line cfc0 0 1 0 1 update mode disabled (update is done by loading of registers 10,11 and12) update of increment for DDFS just after serial loading via CFC update of increment for DDFS on next active edge of HSYNC update of increment for DDFS just before next color burst maxdyn: max dynamic magnitude allowed on YCrCb inputs for encoding. (*) 0 = 10hex to EBhex for Y, 10hex to F0hex for chrominance (Cr,Cb) 1= 01hex to FEhex for Y, Cr and Cb Note: In any case, EAV and SAV words are replaced by blanking values before being fed to the luminance and Chrominance processing. REGISTER 7 content default [0] [0] [0] configuration7 Address: 0x0007 xxx 0 [0] Type: R/W bypass_ sync_ corr 0 [0] [0] bypass_sync_corr: tst_dac bypass mode with sync correction. This is a test mode in which data coming from port tst_dac can be output with or without sync correction and given to the dacs. (*) 0 = There is no sync correction applicable to the data coming from tst_dac. 1 = Sync correction takes place before setting the dacs provided tst_ana(0) is set to ‘1’. Please note that in this case only 8 MSBs are used to generate a 10-bit sync corrected output from the filter. 31/65 Control registers STw8009/STw8019 REGISTER 8 content default ph_rst_ mode1 0 configuration8 ph_rst_ mode0 0 xxx 1 Address: 0x0008 val_422_ mux 0 blk_all 0 Type: R/W xxx 0 xxx 0 xxx 0 Table 12. ph_rst_mode[1:0]:sub-carrier phase reset update mode disabled enabled - phase is updated with value from phase buffer register (see Reg2 bit rstosc_buf) at the beginning of the next video line. In the mean time, the increment is updated with hard or soft values depending on selreg_inc value (see Register 5) enabled - phase is updated with values from Registers 10 and 11, based on the next increment update from cfc (depending on cfc loading moment and Register6 cfc(1:0) bits. enabled - phase is reset following the detection of rst bit on cfc line, up to 9 pix_clk after loading of cfc’s LSB. ph_rst_mode ph_rst_mode 1 0 (*) 0 0 0 1 1 0 1 1 Note: Bits ‘ph_rst_mode(1:0)’ are automatically set back to ‘00’ following the oscillator reset in modes ‘01’ and ‘10’. val_422_mux: should be programmed to “1” only after each reset. blk_all: blanking of all video lines (*) 0 = disabled 1 = enabled (all inputs are ignored - 80hex instead of Cr and Cb and 10hex instead of Y and Y4) REGISTER 9 content hok atfr Address: 0x0009 fieldct2 Type: Read only fieldct1 fieldct0 jump (*) = DEFAULT mode when not_reset pin is active (LOW level) hok: Hamming decoding of frame sync flag embedded within ITU-R656 / D1 compliant YCrCb streams 0 = Consecutive errors (*) 1 = A single or no error Note: Signal quality detector is issued from Hamming decoding of EAV, SAV from YcrCb atfr : Frame synchronization flag (*) 0 = encoder not synchronized 1 = in slave mode: encoder synchronized 32/65 STw8009/STw8019 Control registers fieldct[2:0]: Digital field identification number 000 = indicates field 1 ... 111 = indicates field 8 fieldct[0] also represents the odd/even information (odd=’0’, even=’1’) jump: indicates whether a frame length modification has been programmed at ‘1’ from programming of bit’ jump’ to end of frame(s) concerned. (*)default = 0 Refer to register 6 and registers 21-22-23 Address: 0x000A to 0x000C d21 d13 d5 d20 d12 d4 d19 d11 d3 REGISTERS 10, 11, 12 Increment_dfs register_10 register_11 register_12 d23 d15 d7 d22 d14 d6 Type: R/W d18 d10 d2 d17 d9 d1 d16 d8 d0 These registers contain the 24-bit increment used by the DDFS if bit ‘selrst_inc’ equals ‘1’ to generate the subcarrier phase i.e. the address that is supplied to the sine ROM. It therefore allows to customize the subcarrier synthesized frequency. 1 LSB ~ 1.609325 Hz The procedure to validate the usage of these registers rather than the hard-wired values is the following: - Load the registers with the required value - Set bit ‘selrst_inc’ to 1 (Reg 5) - Perform a software reset (Reg 6) Note: 1 2 3 The values loaded in Reg10-12 are taken into account after a software reset, and ONLY IF bit ‘selrst_inc’=’1’ (Reg. 5). These registers are never reset and must be explicitly written into to contain sensible information. On hardware or on software reset with selrst_inc=’0’, the DDFS is initialized with a hardwired increment, independent of Registers 10-12. These hardwired values being out of any user register cannot be read. These values are: Value d(23:0): 21F07C hexa for NTSC M d(23:0): 2A098B hexa for PAL B,G,H,I,N d(23:0): 21F694 hexa for PAL N d(23:0): 21E6F0 hexa for PAL M Frequency synthesized f=3.5795452 MHz f=4.43361875MHz f=3.5820558 MHz f=3.57561149 MHz 33/65 Control registers STw8009/STw8019 REGISTERS 13, 14 register_13 register_14 xxx o21 Phase_dfs xxx o20 xxx o19 Address: 0x000D to 0x000E xxx o18 xxx o17 Type: R/W xxx o16 o23 o15 o22 o14 Static phase offset for digital frequency synthesizer (10 bits only) Under certain circumstances (detailed below), these registers contain the 10 MSBs of the value with which the phase accumulator of the DDFS is initialized after a 0-to-1 transition of bit ‘rstosc_buf’ of Reg 2, or after a standard change, or when cyclic phase readjustment has been programmed (see bits valrst[1:0] of Reg 2). The 14 remaining LSBs loaded into the accumulator in these cases are all ‘0’s (this allows to define the phase reset value with a 0.35o accuracy). The procedure to validate the usage of these registers rather than the hard-wired values is the following: - Load the registers with the required value - Set bit ‘selrst’ to 1 (Reg 2) - Perform a software reset or set ‘rstosc_buf’ to 1 (Reg 2) (to put soft phase value into a tampon register) and ph_rst_mode[1:0] Note: 1 2 Registers 13-14 are never reset and must be explicitly written into to contain sensible information. If bit ‘selrst’=0 (e.g. after a hardware reset) the phase offset used every time the DDFS is re initialized is a hard-wired value. The hard-wired values being out of any register, they cannot be read out. Reset values: D9C000hex for PAL BDGHI, N, M, 1FC000hex for NTSC-M, 000000hex (blue lines) 34/65 STw8009/STw8019 Control registers REGISTER 17 content default dac2_ mult5 1 dac2 multiplying factors dac2_ mult4 0 dac2_ mult3 0 Address: 0x0011 dac2_ mult2 0 dac2_ mult1 0 Type: R/W dac2_ mult0 0 [1] [0] dac2_mult[5:0]: multiplying factor on dac2_c digital signal before the D/A converters with 0.78% step. Table 13. dac2_mult[5:0]: multiplying factor on dac2_c digital signal dac2_mult[5:0] 0 0 0 0 ... (*) 1 ... 1 0 0 0 0 ... 0 ... 1 0 0 0 0 ... 0 ... 1 0 0 0 0 ... 0 ... 1 1 Address: 1 0 0 0 0 1 1 0 1 0 1 75.00% 75.78% 76.56% 77.34% ... 100% ... 124.22% REGISTERS 21, 22, 23 clig_i_reg = ltarg[8:0] and lref[8:0] register 21 register 22 register 23 ltarg8 ltarg0 lref1 ltarg7 lref8 lref0 ltarg6 lref7 - 0x0015 to 0x0017 ltarg5 lref6 ltarg4 lref5 - Type: R/W ltarg3 lref4 ltarg2 lref3 ltarg1 lref2 - These registers may be used to jump from a reference line (end of that line) to a target line of the SAME FIELD. However, not all lines can be skipped or repeated with no problems and, if needed, this functionality should BE USED WITH CAUTION. lref[8:0] contains, in binary format, the reference line from which a jump is required. ltarg[8:0] contains the target line as a binary number. Default values: lref[8:0]:= 000000000 and ltarg[8:0]:= 000000001. 35/65 Control registers STw8009/STw8019 REGISTER 65 content default c_mult3 0 C_mult&ttxs c_mult2 0 c_mult1 0 Address: 0x0041 c_mult0 0 [0] Type: R/W xxx 0 [0] bcs_en_ main 1 c_mult[3:0]: multiplying factor of C digital output (before D/A convertors) and of color part of CVBS signal. Table 14. c_mult[3:0]: multiplying factor of C digital output c_mult2 0 0 0 0 ... 1 c_mult1 0 0 1 1 ... 1 c_mult0 0 1 0 1 ... 1 factor value (c_mult) 1.000000 (1.000000 Dec.) 1.000001 (1.015625 Dec.) 1.000010 (1.031250 Dec.) 1.000011 (1.046875 Dec.) ... 1.001111 (1.234375 Dec.) c_mult3 (*) 0 0 0 0 ... 1 bcs_en_main: Brightness, Contrast and Saturation control by Registers 69 to 71 on 4:4:4 video input 0 = disable (*) 1 = enable REGISTER 69 content default b7 1 Brightness b6 0 b5 0 Address: 0x0045 b4 0 b3 0 b2 0 Type: R/W b1 0 b0 0 To adjust the luminance intensity of the display video image, the following formula is used: Yout = Yin + b –128 Yin is the 8-bit input luminance Yout is the result of ‘Brightness’ operation (still on 8 bits) This value is saturated at 235 (16) or 254 (1) according to register6 bit ‘maxdyn’, b: brightness (unsigned value with center at 128, default 128) 36/65 STw8009/STw8019 Control registers REGISTER 70 content default c7 0 Contrast c6 0 c5 0 Address: 0x0046 c4 0 c3 0 c2 0 Type: R/W c1 0 c0 0 Adjustment of the relative difference between high and low intensity luminance values of the displayed image is made according to the following formula: ( Yi n – 128 ) ( c + 128 ) Yo ut = -------------------------------------- - + 128 ---------128 Yin is the 8-bit input luminance, Yout is the result of ‘Contrast’ operation (still on 8 bits) This value is saturated at 235 (16) or 254 (1) according to register6 bit ‘maxdyn’, c: contrast (2’s complement value from -128 to 127, default 0) REGISTER 71 content default s7 1 Saturation s6 0 s5 0 Address: 0x0047 s4 0 s3 0 s2 0 Type: R/W s1 0 s0 0 To adjust the color intensity of the displayed video image, the following formula is used: s ( Cbin – 128 ) Cbout = ---------------------------------- + 128 128 s ( Crin – 128 ) Cro ut = --------------------------------- + 128 128 Crin, Cbin 8-bit input chroma, Crout, Cbout the result of ‘Saturation’ operation (still on 8 bits) This value is saturated at 240 (16) or 254 (1) according to bit ‘maxdyn’ (Reg 6), s: saturation value (unsigned value with centre at 128, default 128) 37/65 Control registers STw8009/STw8019 REGISTERS 72 to 80 Address: Chroma filter coefficients Table 15. Chroma main_coef_[8:0] reg_ main_plg main_flt_s 72 _div1 reg_ xxx 73 reg_ xxx 74 reg_ xxx 75 reg_ coef4(7) 76 reg_ coef5(7) 77 reg_ coef6(7) 78 reg_ coef7(7) 79 reg_ coef8(7) 80 coef8(8) coef2(6) coef3(6) coef4(6) coef5(6) coef6(6) coef7(6) coef8(6) main_plg _div0 coef1(5) coef2(5) coef3(5) coef4(5) coef5(5) coef6(5) coef7(5) coef8(5) : 0x0048 to 0x0050 Type: R/W chroma_main_coef_0 chroma_main_coef_1 chroma_main_coef_2 chroma_main_coef_3 chroma_main_coef_4 chroma_main_coef_5 chroma_main_coef_6 chroma_main_coef_7 chroma_main_coef_8 coef0(4) coef0(3) coef0(2) coef0(1) coef0(0) coef1(4) coef1(3) coef1(2) coef1(1) coef1(0) coef2(4) coef2(3) coef2(2) coef2(1) coef2(0) coef3(4) coef3(3) coef3(2) coef3(1) coef3(0) coef4(4) coef4(3) coef4(2) coef4(1) coef4(0) coef5(4) coef5(3) coef5(2) coef5(1) coef5(0) coef6(4) coef6(3) coef6(2) coef6(1) coef6(0) coef7(4) coef7(3) coef7(2) coef7(1) coef7(0) coef8(4) coef8(3) coef8(2) coef8(1) coef8(0) Values from these registers are used only when bit main_flt_s (Reg 72) is set to 1. Bit main_flt_s has the highest priority over the rest. With main_flt_s bit set to 1, all bits from main_plg_div[1:0] need to be programmed to the chroma coefficients. Alternatively, the coefficients default values are loaded depending on the selected mode or the selected filter type in a particular mode with flt(1:0) bits from register 1. The values are soft loaded when main_flt_s = 1. The value to be loaded in the register should be the actual coefficient value + an offset. The hardware will internally subtract this offset to get the actual coefficient value. main_flt-s default value: 0 The main_plg_div value is chosen according to the sum of all the coefficients. main_plg_div = 11 when sum of coeffs = 4096 main_plg_div = 10 when sum of coeffs = 2048 main_plg_div = 01 when sum of coeffs = 1024, (default) main_plg_div = 00 when sum of coeffs = 512 Offset change before loading to user register: chroma_main_coef0 = Actual value + 16; chroma_main_coef1 = Actual value + 32; chroma_main_coef2 = Actual value + 64; chroma_main_coef3 = Actual value + 32; 38/65 STw8009/STw8019 Control registers chroma_main_coef4 = Actual value + 32; chroma_main_coef5 = Actual value + 32; chroma_main_coef6 = Actual value chroma_main_coef7 = Actual value chroma_main_coef8 = Actual value Default values: chroma_main_coef0[4:0] = 10001 chroma_main_coef1[5:0] = 100111 chroma_main_coef2[6:0] = 1010100 chroma_main_coef3[6:0] = 1000111 chroma_main_coef4[7:0] = 01011111 chroma_main_coef5[7:0] = 01110111 chroma_main_coef6[7:0] = 01101100 chroma_main_coef7[7:0] = 01111011 chroma_main_coef8[8:0] = 010000000 means c0 = 1. means c1 = 7; means c2= 20; means c3 = 39; means c4 = 63; means c5 = 87; means c6 = 108; means c7 = 123; means c8 = 128. The FIR symmetrical filter has the following response: H ( z ) = c 0 + c1z –1 + c 2z –2 + + c 7z –7 + c8z –8 + c7 z –9 + + c 2z – 14 + c 1z –15 + c0 z – 16 The filter working frequency is comprised in the range [pix_clk, 27 MHz] and the filtering is done on upsampled signal (half pix_clk to pix_clk frequency by padding by zeros). 39/65 Control registers STw8009/STw8019 REGISTER 81 content default Configuration 9 Address: 0x0051 xxx 0 Type: R/W plg_div_ plg_div_ y1 y0 0 1 flt_ys 0 main_de main_de main_de main_de l3 l2 l1 l0 0 0 1 0 main_del[3:0]: delay on chroma path with reference to luma path, on the encoded signal coming from the main outputs. The delay value varies with modes, delays are hardwired to have different delays in different modes. If the delays are to be made programmable, set bit main_del_en to 1 (Reg 03) to enable soft delay from main_del[3:0]. Table 16. main_ del3 (*) 0 0 0 0 1 1 1 1 main_del[3:0] main_ del2 0 0 1 1 1 1 1 1 Others Others main_ del1 1 1 0 0 0 0 1 1 main_ del0 0 1 0 1 0 1 0 1 1 0 Delay on chroma path with reference to luma path encoding [One pixel corresponds to 2/fpix_clk] - 0.5 pixel delay on chroma - 1 pixel delay on chroma - 1.5 pixel delay on chroma - 2 pixel delay on chroma + 2.5 pixel delay on chroma + 2 pixel delay on chroma + 1.5 pixel delay on chroma + 1 pixel delay on chroma 0 pixel delay on chroma (reference delay) + 0.5 pixel delay on chroma If main_del_en = 0 then the delays used are: main_del[3:0] = 0010 when mode = PAL/NTSC in 4:2:2 format on CVBS main_del[3:0] = 0001 when mode = PAL/NTSC in 4:4:4. plg_div_y = 00 when sum of coefficients = 256 plg_div_y = 01 when sum of coefficients = 512 (default) plg_div_y = 10 when sum of coefficients = 1024 plg_div_y = 11 when sum of coefficients = 2048 Bit flt_ys enables the software loading capability of luma coefficients. Values from registers 82 to 91 are used only when bit “flt_ys” of this register is set to 1. Bit “flt_ys” has the highest priority. With this bit set to 1, all bits from plg_div_y[1:0] must be programmed as luma coefficients. Alternatively, the default values of the coefficients are loaded. The luma coefficients are mode and standard independent. flt_ys default value is “0”. 40/65 STw8009/STw8019 Control registers REGISTERS 82 to 91: luma filter coefficients Address: 0x0052 to 0x005B Type: R/W Table 17. Luma_coef_[0:9] reg_82 xxx reg_83 l9(9) reg_84 l6(8) reg_85 l7(8) reg_86 l4(7) reg_87 l5(7) reg_88 l6(7) reg_89 l7(7) reg_90 l8(7) reg_91 l9(7) xxx l9(8) l2(6) l3(6) l4(6) l5(6) l6(6) l7(6) l8(6) l9(6) l8(8) l1(5) l2(5) l3(5) l4(5) l5(5) l6(5) l7(5) l8(5) l9(5) l0(4) l1(4) l2(4) l3(4) l4(4) l5(4) l6(4) l7(4) l8(4) l9(4) l0(3) l1(3) l2(3) l3(3) l4(3) l5(3) l6(3) l7(3) l8(3) l9(3) l0(2) l1(2) l2(2) l3(2) l4(2) l5(2) l6(2) l7(2) l8(2) l9(2) l0(1) l1(1) l2(1) l3(1) l4(1) l5(1) l6(1) l7(1) l8(1) l9(1) l0(0) l1(0) l2(0) l3(0) l4(0) l5(0) l6(0) l7(0) l8(0) l9(0) luma_coef_0 luma_coef_1 luma_coef_2 luma_coef_3 luma_coef_4 luma_coef_5 luma_coef_6 luma_coef_7 luma_coef_8 luma_coef_9 Values from these registers are used only when bit flt_ys of register 81 is set to 1. The coefficient values of luma_coef_0 to luma_coef_7 should be entered as 2’s complement, and the rest as normal positive values. The hardware will internally generate normal positive values. Default values: a0 = luma_coef_0[4:0] = 00001 a1 = luma_coef_1[5:0] = 111111 a2 = luma_coef_2[6:0] = 1110111 a3 = luma_coef_3[6:0] = 0000011 a4 = luma_coef_4[7:0] = 00011111 a5 = luma_coef_5[7:0] = 11111011 a6 = luma_coef_6[8:0] = 110101100 a7 = luma_coef_7[8:0] = 000000111 a8 = luma_coef_8[8:0] = 100111101 a9 = luma_coef_9[9:0] = 0111111000 means +1; means -1; means -9; means +3; means +31; means -5; means -84; means +7; means +317; means +504; The FIR filter is symmetrical with the following response: H ( z ) = a0 + a1 z –1 + a2z –2 + + a8z –8 + a9z –9 + a8 z – 10 + + a2 z –16 + a1z – 17 +a Working frequency of this filter is the one of pix_clk (27, 24.545454 or 29.5 MHz), and the filtering is done on upsampled signal (half pix_clk to pix_clk frequency by padding by zeros). 41/65 Control registers STw8009/STw8019 REGISTER 93 content default [0] Configuration 11 Address: 0x005D xxx Type: R/W main_if_ del 0 xxx 0 xxx 0 [0] [1] [0] 1 main_if_del: The delay on the luma comparing to chroma in CVBS and S-VHS outputs. This delay is 5 clock cycles (27 MHz clock). (*) 0 = enabled 1 = disabled REGISTER 94 content default [0] Configuration 12 xxx 0 xxx 0 Address: 0x005E xxx 0 [0] Type: R/W ennotch 0 [0] xxx 0 ennotch: Notch filtering on the cvbs output (*) 0 = disabled 1 = enabled REGISTER 95 content default [0] [0] Configuration 13 dac12_ conf 0 Address: 0x005F Type: R/W [0] [0] [0] [0] [1] dac12_conf: Please refer to the table below for all combinations to be observed at DACs. Table 18. dac12_conf dac12_conf (*)0 1 REGISTER 105 content default Hue control hue_ cont (7) 0 hue_ cont (6) 0 hue_con t (5) 0 Address: 0x0069 hue_ cont (4) 0 hue_ cont (3) 0 dac1 Y dac2 C CVBS Type: R/W hue_ cont (2) 0 hue_ cont (1) 0 hue_ cont (0) 0 Defines the phase shift in the subcarrier during active video with respect to the subcarrier phase during the color burst. Once enabled by Register_4(2) “hue_en”, phase variation would be in a range of +/- 22.324 degrees with increments of 0.17578127. Note: Pulse the Register_4(2) “hue_en” to make sure that a value programmed in this register is effective immediately after programming Hue_control. Once enabled, to disable any phase shift in active subcarrier wrt burst, write the default value into the Hue_control register followed by a pulse on Register_4(2) “hue_en”. 42/65 STw8009/STw8019 hue_control [6:0]: absolute value of phase adjustment, range 1 to 127. LSB (0x01) implies 0.17578127 degrees, 0x7F imply 22.324 degrees hue_control [7]: Sign of phase 1 = +ve; (*) 0 = -ve (*) “00000000” “10000000” “11111111” “01111111” REGISTER 106 content default xxx 0 Control registers : No phase shift : No phase shift : +22.324 degrees phase : -22.324 degrees phase dac1 multiplying factor Address: 0x006A xxx 0 dac1_ mult5 1 dac1_ mult4 0 dac1_ mult3 0 Type: R/W dac1_ mult2 0 dac1_ mult1 0 dac1_ mult0 0 dac1_mult(5:0): multiplying factor on dac1_y digital signal before the D/A converters with 0.78% step. Table 19. dac1_multi[5:0] dac1_mult[5:0] 0 0 0 0 ... (*) 1 ... 1 REGISTER 108 content default [0] [0] [0] [0] 0 0 0 0 ... 0 ... 1 0 0 0 0 ... 0 ... 1 Chroma Delay 0 0 0 0 ... 0 ... 1 1 1 0 0 0 0 1 1 0 1 0 1 75.00% 75.78% 76.56% 77.34% ... 100% ... 124.22% Type: R/W main_chr_ del1 1 main_chr_ del0 0 Address: 0x006C main_chr_ del3 0 main_chr_ del2 0 main_chr_del[3:0]: delay on chroma path with reference to luma path on encoded component outputs. The delay value varies with modes and the delays are hardwired to have different delays in different modes. If the delays are to be made programmable make bitmain_chr_del_en = 1 (Reg 109). That way, soft delay from main_chr_del[3:0] is enabled. 43/65 Control registers Table 20. main_chr_del[3:0] STw8009/STw8019 main_ main_ main_ main_ chr_ del3 chr_ del2 chr_ del1 chr_ del0 (*) 0 0 0 0 1 1 1 1 0 0 1 1 1 1 1 1 Others Others 1 1 0 0 0 0 1 1 0 1 0 1 0 1 0 1 1 0 Delay on chroma path with reference to luma path encoding [One pixel corresponds to /fpix_clk] - 0.5 pixel delay on chroma - 1 pixel delay on chroma - 1.5 pixel delay on chroma - 2 pixel delay on chroma + 2.5 pixel delay on chroma + 2 pixel delay on chroma + 1.5 pixel delay on chroma + 1 pixel delay on chroma 0 pixel delay on chroma (reference delay) + 0.5 pixel delay on chroma If main_chr_del_en = 0 then the delays used are: main_chr_del[3:0] = 0010 when mode = PAL/NTSC in 4:2:2 format on CVBS. main_chr_del[3:0] = 0001 when mode = PAL/NTSC in 4:4:4 REGISTER 109 content default [0] [0] Chroma Delay Enable Address: 0x006D Type: R/W main_chr _del_en 0 main_chr_del_en: Enable of luma to chroma delay on the 4:4:4 component outputs. (*) 0 = disabled (DENC automatically sets this delay) 1 = enabled (chroma to luma delay is programmed by main_chr_del[3:0] bits (Reg 108). Note: This delay affects only the component Y/C. The cvbs output remains unaffected. Refer to register 3 to program chroma to luma delay on cvbs output signal. 44/65 STw8009/STw8019 Control registers 5.2.2 Control & power management unit registers Control and power management unit REGISTER 128 content default 0 0 0 0 0 0 0 Configuration0 Address: 0x0080 Type: R/W standby 0 standby: In this mode the analog subsystem is supplied by the 1.2V/1.4V and the 2.8V/3.3V, but the DACs are set in power down mode, via poff[1:2] bits (Reg 130 & 131). Digital to analog data conversion is disabled. (*) 0 = disabled (active mode) 1 = standby Control and power management unit reset REGISTER 129 content default 0 0 0 0 0 0 0 Configuration 1 Address: 0x0081 Type: R/W cpmuswrst 0 cpmuswrst: Control and power management unit reset (*) 0 = disabled 1 = control and power management unit software reset Note: Bit cpmuswrst is automatically reset to its default value after internal reset generation and the I2C data transfer is stopped. This reset is kept available for a CLK cycle. REGISTER 130 content default 0 0 0 0 0 DAC1 control Address: 0x0082 poff1 1 Type: R/W notzerod1 1 pedestal Ond1 0 poff1: DAC2 power off, then turn off DAC2 is in a low power consumption mode 0 = disabled (DAC2 active) (*) 1 = turned off Note: As Default value is “1”, Digital processor must write “0” when going from sleep or standby to active mode. notzerod1 : null digital data inputed on DAC2 0 = independently of what is coming from the digital part, “0000000000” is forced on DAC2 input. (*) 1 = disabled, values issued from DENC are transmitted to DAC2. pedestalOnd1 : Black level video pedestal active on DAC2 (*) 0 = disabled 1 = video pedestal active 45/65 Control registers STw8009/STw8019 REGISTER 131 content default 0 DAC2 control Address: 0x0083 poff2 Type: R/W notzerod2 1 pedestal Ond2 0 0 0 0 0 1 poff2: DAC1 power off, then turn off DAC1 is in a low power consumption mode. 0 = disabled (DAC1 active) (*)1 = turned off Note: As Default value is “1”, Digital processor must write “0” when going from sleep or standby to active mode. notzerod2 : null digital data input on DAC1 0 = independently of that is coming from the digital part, “0000000000” is forced on DAC1 input. (*)1 = disabled, values issued from DENC are transmitted to DAC1. pedestalOnd2: Black level video pedestal active on DAC1 (*) 0 = disabled 1 = video pedestal active REGISTER 132 content default - Plugdet Address: 0x0084 Type: R LoadD - LoadD: Reports Plugdet Ball status. Unless otherwise specified all voltages are referenced to GND. 0 = Plugdet ball voltage less than VIL 1 = Plugdet ball voltage higher than VIH 46/65 STw8009/STw8019 Bus interface 6 6.1 Bus interface 2 wire serial MPU control interface (I2C compatible) STw80x9 serial MPU control interface is compliant with I2C standard and acts only as a slave device. It supports 100 kHz and 400 kHz speeds. In addition to the basic definition of the I2C standard (SDA & SCL signals), STw80x9 serial MPU interface has an additional “Add” input used to select one out of two slave addresses. The device supports 7-bit and 10-bit addresses. Table 21. STw80x9 addresses 7-bit addresses Read Write 01000000 01000010 10-bit addresses Read 00001000001 00001000011 Write 00001000000 00001000010 Add pin = 0 Add pin = 1 01000001 01000011 7-bit address mode In Write mode, several data can be sent without re-initializing a transfer and data is written in successive registers. (Figure 18: 2-wire serial MPU control interface format (I2C compatible) / 7-bit addresses). In Read mode: (Figure 18). ● Double transaction read: The operation is split into to transactions: The first one is a write that transmits the desired address. The I2C interface memorizes the address of the register. The second transfer is a read that can be repeated to read successive registers. After each read byte and except for the last one, the master issues an “acknowledge”. The master indicates that it is reading the last byte by issuing a “no acknowledge” instead of an “acknowledge”. Single transaction read: As opposed to the double transaction, instead of stopping the first transaction and starting the second one, the transactions are combined with a repeated start condition. ● 47/65 Bus interface STw8009/STw8019 Figure 18. 2-wire serial MPU control interface format (I2C compatible) / 7-bit addresses * Write operation (7 bits addresses) S STw8009 slave address r/w A STw8009 register address A STw8009 register data A P Write (0) Can be repeated n times to write in successive registers * Double transaction read S STw8009 slave address r/w A STw8009 register address A P Write (0) r/w S STw8009 slave address A STw8009 register data A/NA P Read (1) * Single transaction read Can be repeated n times to read in successive registers S STw8009 slave address r/w A STw8009 register address A Sr STw8009 slave address r/w STw8009 register data A/NA P Write (0) Read (1) Can be repeated n times to read in successive registers S Start condition Sr Repeated start condition P Stop condition A/NA Acknowledge / No Acknoledge From master to slave From slave to master 10 bits address mode In Write mode, several data can be sent without re-initializing a transfer, in this case, data is written in successive registers. (Figure 19: 2-wire serial MPU control interface format (I2C compatible) / 10-bit addresses) In Read mode: (Figure 19) ● Double transaction read: The operation is split into two transactions: The first one is a write that transmits the desired address. The I2C interface memorizes the address of the register. The second transfer is a read that can be repeated to read successive registers. After each read byte and except for the last one, the master issues an “acknowledge”. The master indicates that it is reading the last byte by issuing a “no acknowledge” instead of an “acknowledge”. Note: Only the higher part of the address is sent again before sending the read indication. ● Single transaction read: As opposed to the double transaction, instead of stopping the first transaction and starting the second one, the transactions are combined with a repeated start condition. 48/65 STw8009/STw8019 Bus interface Figure 19. 2-wire serial MPU control interface format (I2C compatible) / 10-bit addresses * Write operation (10 bits addresses) S 11110 2MSBs r/w A1 8 LSBs A2 STw8009 register address A STw8009 register data A P Write (0) Can be repeated n times to write in successive registers STw8009 slave address * Double transaction read S 11110 2MSBs r/w A1 8 LSBs A2 STw8009 register address A P Write (0) STw8009 slave address S 11110 2MSBs r/w A1 8 LSBs A2 Sr 11110 2MSBs r/w A3 STw8009 register data A/NA P Write (0) STw8009 slave address * Single transaction read S 11110 2MSBs r/w A1 8 LSBs A2 Read (1) Can be repeated n times to read in successive registers STw8009 register address A3 Sr 11110 2MSBs r/w A STw8009 register data A/NA P Write (0) STw8009 slave address Read (1) Can be repeated n times to read in successive registers S Start condition Sr Repeated start condition P Stop condition A/NA Acknowledge / No Acknoledge From master to slave From slave to master Figure 20. 2-wire serial MPU control interface timing tHD_DAT tSU_DAT SA D tBUF tF tR tSU_STA tHD_STA tSU_STO S LK C tHD_STA tLOW tHIGH P=Stop S=Start Sr=Start repeated P= Stop 49/65 Bus interface STw8009/STw8019 6.2 YcbCr bus Figure 21. YcbCr bus format Clk YCbCr[7:0] Cb0 Y0 Cr0 Y1 Cb2 Y2 Cr2 Y3 Cb4 Table 22. Symbol CLK27M CLKdc th ts YcBCr data bus timing (Figure 22) Parameter Clock frequency Clock duty cycle Data input hold time Data input setup time 45 3 1.5 Test conditions Min. Typ. 27 55 Max. Unit MHz % ns ns Figure 22. Data bus timing 1V8 CCIR data GND ts CLK27M th ts: CCIR data to CLK27M setup time th: CCIR data to CLK27M hold time 50/65 STw8009/STw8019 Electrical characteristics 7 7.1 Electrical characteristics Absolute maximum rating Unless otherwise specified: TA=+25°C, all voltages are referenced to GND. Table 23. Symbol Vdd VddIO VccA VDCdig VDCana Pmax Tstg Vesd Absolute maximum ratings Parameter Digital core supply voltage I/O digital supply voltage Analog supply voltage DC input voltage on any digital pin DC input voltage on any analog pin Maximum power dissipation Storage temperature range Human body Electrostatic discharge voltage model(1) Value -0.3 to +1.65 -0.3 to +3.6 -0.3 to +3.8 -0.3 to +2.0 -0.3 to +3.8 700 -40 to 125 -2 to +2 -500 to +500 Unit V V V V V mW °C KV V Charge device model(2) 1. HBM tests have been performed in compliance with JESD22-A114-B and ESD STM 5.1-2001.HBM 2. CDM tests have been performed in compliance with CDM ANSI-ESDSTM5.3.1-1999 7.2 Operating conditions Unless otherwise specified: TA=+25°C, all voltages are referenced to GND. Table 24. Symbol Vdd VddIO VccA TA Operating conditions Parameter Digital core supply voltage I/O digital supply voltage Analog supply voltage Operating temperature Min. 1.08 1.65 2.7 -30 Typ. 1.2 1.8 Max. 1.47 3.0 3.6 +85 Unit V V V °C 51/65 Electrical characteristics STw8009/STw8019 7.3 Table 25. Symbol fSCL tBUF tHD_STA tf tLOW tr tHIGH tHD_DAT tSU_DAT tSU_STA tSU_STO Electrical and timing characteristics Unless otherwise specified: TA=+25°C, all voltages are referenced to GND. 2 wire serial MPU control interface timing (Figure 20) Parameter Clock Frequency Bus free time Start condition hold time SDA & SCLK fall time SCLK pulse width low SDA & SCLK rise time SCLK pulse width high Data input hold time Data input set up time Start condition set up time Stop condition set up time 600 0 100 600 600 1300 300 1300 600 300 Test conditions Min. Typ. Max. 400 Unit kHz ns ns ns ns ns ns ns ns ns ns ) Table 26. Symbol VIL VIH VOL VOH IIL IIH Digital I/O interface Parameter Input Low voltage Input High voltage Output Low level Output High level Input Low current Input High current Test conditions All digital inputs All digital inputs All digital outputs All digital outputs All digital inputs / 0V < Vin < VIL All digital inputs / VCCIO < Vin < VIH 0.8*VddIO -10 -10 10 10 0.7*VddIO 0.1*VddIO Min. Typ. Max. 0.2*VddIO Unit V V V V µA µA 52/65 STw8009/STw8019 Table 27. Symbol PSLVdd PSTVdd PSTVcca PACVdd PACVddIO PAC0Vcca PAC1Vcca PAC2Vcca Electrical characteristics Power consumption/R load = 37.5 ohm Parameter Sleep mode on Vdd Stand by mode on Vdd Stand by mode on Vcca Active mode on Vdd Active mode on VddIO Active mode on Vcca Active mode on Vcca Active mode on Vcca Test conditions Vdd = 1.2V no 27 MHz clock Vdd = 1.2V Vcca = 2.8V Vdd = 1.2 V 0, 1 or 2 DAC enabled VddIO = 1.8V Vcca = 2.8V no DAC enabled Vcca = 2.8V 1 DAC enabled Vcca = 2.8V 2 DAC enabled Min. Typ. 3 150 1 5 180 2 120 240 Max. Unit µW µW µW mW µW µW mW mW Table 28. Symbol RDAC INLDAC DNLDAC VFR1 VFR2 SFDR SNR PSRR DAC & Video output characteristics / Rload = 37.5 ohm – F = 27 MHz – Rext = 2.4 kohm Parameter Resolution Integral non linearity Differential non linearity Full range output voltage Pedestal on low Full range output voltage Pedestal on high Spurious free dynamic range Signal to noise ratio Power supply rejection ratio F = 1 MHz / 1 Vpp With white level 2.8 V supply / F = 200 Hz Average measurements on VSA R&S on NTC7comp and CCIR17 line test patterns Average measurements on VSA R&S on NTC7comp and CCIR17 line test patterns -1.5 -0.8 1.14 1.24 TBD 55 1.21 1.31 49 62 65 Test conditions Min. Typ. 10 +1.5 +0.8 1.27 1.38 Max. Unit Bits LSB LSB V V dB dB dB DiffG Differential gain 1 % DiffPh Differential phase 1 deg 53/65 Application information STw8009/STw8019 8 Application information Figure 23. Typical application schematic Clk Video Interface YCbCr[0:7] C/CVBS Optional L.P. filter ESD 2 wire MPU bus TV set 75 Ω W 75 W 75 Ω PORn or VCR STw8009 75 Ω W Protection Optional L.P. filter Digital Processor Suspend Rext 2.4 K Vdd VIO VccA Y Only for S-VHS 75 Ω W Cvd Cio Cca Vdd VIO VccA 100 nF / One capacitor connected on each ball supply Supply Gnd 54/65 STw8009/STw8019 Color test pattern waveforms 9 Color test pattern waveforms Figure 24. NTSC composite 55/65 Color test pattern waveforms Figure 25. NTSC S-video STw8009/STw8019 56/65 STw8009/STw8019 Figure 26. PAL composite Color test pattern waveforms 57/65 Color test pattern waveforms Figure 27. PAL S-video STw8009/STw8019 58/65 STw8009/STw8019 Package mechanical data 10 10.1 Package mechanical data TFBGA 49 balls Table 29. TFBGA 4x4x1.2 mm Dimensions (mm) Reference A A1 A2 A3 A4 b D D1 E E1 e F ddd eee fff 3.85 0.25 3.85 0.3 4.00 3.00 4.00 3.00 0.50 0.5 0.08 0.15 0.05 4.15 0.15 0.8 0.2 0.6 0.35 4.15 Min Typ Max 1.2 59/65 Package mechanical data Figure 28. TFBGA 49 balls 4 x 4 x 1.2 mm body size STw8009/STw8019 60/65 STw8009/STw8019 Package mechanical data 10.2 VFBGA 49 balls Table 30. VFBGA 3x3x1.0 mm - 49 balls - Pitch 0.4 ball 0.25 Dimensions (mm) Reference A(1) A1 A2 A3 A4 b(2) D D1 E E1 e F ddd eee(3) fff(4) 1. VFBGA stands for Very thin profile Fine pitch Ball Grid Array. Very thin profile: 0.80mm