STW81101AT

STW81101 Multi-band RF frequency synthesizer with integrated VCOs Features ■ ■ Integer-N frequency synthesizer Dual differential integrated VCOs with automatic center frequency calibration: – 3300 - 3900 MHz (Direct output) – 3800 - 4400 MHz (Direct output) – 1650 - 1950 MHz (Internal divider by 2) – 1900 - 2200 MHz (Internal divider by 2) – 825 - 975 MHz (Internal divider by 4) – 950 - 1100 MHz (Internal divider by 4) Excellent integrated phase noise Fast lock time: 150µs Dual modulus programmable prescaler (16/17 or 19/20) 2 programmable counters to achieve a feedback division ratio from 256 to 65551 (prescaler 16/17) and from 361 to 77836 (prescaler 19/20). Programmable reference frequency divider (10 bits) Phase frequency comparator and charge pump Programmable charge pump current Digital lock detector Dual digital bus Interface: SPI and I2C bus with a 3-bit programmable address (1100A2A1A0) 3.3V power supply Power down mode (HW and SW) Small size exposed pad VFQFPN28 package 5x5x1.0mm Process: BICMOS 0.35µm SiGe VFQFPN28 ■ ■ ■ ■ Applications ■ ■ ■ ■ 2.5G and 3G cellular infrastructure equipment CATV equipment Instrumentation and test equipment Other wireless communication systems Description The STMicroelectronics STW81101 is an integrated RF synthesizer with voltage controlled oscillators (VCOs). Showing high performance, high integration, low power, and multi-band performances, STW81101 is a low-cost one-chip alternative to discrete PLL and VCO solutions. The STW81101 includes an Integer-N frequency synthesizer and two fully integrated VCOs featuring low phase-noise performance and a noise floor of -155dBc/Hz. The combination of wide frequency range VCOs (using centerfrequency calibration over 32 sub-bands) and multiple output options (direct output, divided by 2, or divided by 4) allows coverage of the 825MHz-1100MHz, 1650MHz-2200MHz and 3300MHz-4400MHz bands. The STW81101 is designed with STMicroelectronics advanced 0.35µm SiGe process. ■ ■ ■ ■ ■ ■ ■ ■ ■ August 2007 Rev 3 1/48 www.st.com 1 Contents STW81101 Contents 1 Block diagram and pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 1.1 1.2 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2 Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.1 2.2 2.3 2.4 2.5 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Digital logic levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Phase noise specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3 4 5 Typical performance characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 General description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Circuit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 5.1 5.2 5.3 5.4 5.5 5.6 5.7 5.8 Reference input stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Reference divider . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 A and B counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Phase frequency detector (PFD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Lock detect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Charge pump . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Voltage controlled oscillators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 5.8.1 5.8.2 5.8.3 VCO selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 VCO frequency calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 VCO voltage amplitude control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 6 I2C bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 6.1 General features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 6.1.1 6.1.2 6.1.3 Data validity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 START and STOP conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Byte format and acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 2/48 STW81101 6.1.4 6.1.5 6.1.6 6.1.7 Contents Device addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Single-byte write mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Multi-byte write mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Current byte address read mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 6.2 6.3 Timing specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 I2C registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 6.3.1 6.3.2 6.3.3 Write-only registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Read-only register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Default configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 6.4 VCO calibration procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 7 SPI digital interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 7.1 7.2 7.3 7.4 General features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Timing specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Bit tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 7.3.1 Default configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 VCO calibration procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 8 Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 8.1 8.2 8.3 8.4 Direct output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Divided by 2 output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Divided by 4 output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Evaluation kit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 9 10 11 12 Application diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 3/48 List of tables STW81101 List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Table 24. Table 25. Table 26. Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Operating conditions (refer to Figure 36: Application diagram) . . . . . . . . . . . . . . . . . . . . . . 9 Digital logic levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Electrical specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Phase noise specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Current value vs. selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 VCO A performances versus amplitude setting (Freq=3.6GHz). . . . . . . . . . . . . . . . . . . . . 23 VCO B performances vs. amplitude setting (Freq=4.1GHz). . . . . . . . . . . . . . . . . . . . . . . . 23 Single-byte write mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Multi-byte write mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Current byte address read mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Data and clock timing specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Start and stop timing specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Ack timing specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Write-only registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Functional modes of the FUNCTIONAL_MODE register . . . . . . . . . . . . . . . . . . . . . . . . . . 29 SPI data structure (MSB is sent first) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Address decoder and outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 SPI timing specification. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Bits at 00h and ST1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Bits at 01h and ST2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Order code of the evaluation kit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Package dimensions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Order codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 4/48 STW81101 List of figures List of figures Figure 1. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Figure 2. Pin connection (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Figure 3. VCO A (direct output) open loop phase noise . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Figure 4. VCO B (direct output) open loop phase noise . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Figure 5. VCO A (direct output) closed loop phase noise at 3.6GHz (FSTEP=200kHz; FPFD=200kHz; ICP=3.5mA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Figure 6. VCO B (direct output) closed loop phase noise at 4.0GHz (FSTEP=200kHz; FPFD=200kHz; ICP=4mA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Figure 7. VCO A (div. by 2 output) closed loop phase noise at 1.8GHz (FSTEP=200kHz; FPFD=400kHz; ICP=2mA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Figure 8. VCO B (div. by 2 output) closed loop phase noise at 2.0GHz (FSTEP=200kHz; FPFD=400kHz; ICP=3mA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Figure 9. VCO A (div. by 4 output) closed loop phase noise at 900MHz (FSTEP=200kHz; FPFD=800kHz; ICP=1.5mA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Figure 10. VCO B (div. by 4 output) closed loop phase noise at 1.0GHz (FSTEP=200kHz; FPFD=800kHz; ICP=1.5mA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Figure 11. PFD frequency spurs (direct output; FPFD=200kHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Figure 12. PFD frequency spurs (div. by 2 output; FPFD=400kHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Figure 13. PFD frequency spurs (div. by 4 output; FPFD=800kHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Figure 14. Settling time (final frequency=1.8 GHz; FPFD=400kHz; ICP=2mA . . . . . . . . . . . . . . . . . . . 16 Figure 15. Reference frequency input buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Figure 16. VCO divider diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Figure 17. PFD diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Figure 18. Loop filter connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Figure 19. VCO sub-bands frequency characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Figure 20. Data validity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Figure 21. START and STOP conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Figure 22. Byte format and acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Figure 23. Data and clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Figure 24. Start and stop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Figure 25. Ack . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Figure 26. SPI input and output bit order . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Figure 27. SPI timing specification. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Figure 28. Differential/single-ended output network (MATCH_LC_LUMP_4G_DIFF.dsn) . . . . . . . . . 38 Figure 29. LC lumped balun and matching network (MATCH_LC_LUMP_4G.dsn) . . . . . . . . . . . . . . 39 Figure 30. Evaluation board (EVB4G) matching network (MATCH_EVB4G.dsn) . . . . . . . . . . . . . . . . 40 Figure 31. Differential/single-ended output network (MATCH_LC_LUMP_2G_DIFF.dsn) . . . . . . . . . 40 Figure 32. LC lumped balun for divided by 2 output (MATCH_LC_LUMP_2G.dsn) . . . . . . . . . . . . . . 41 Figure 33. Evaluation board (EVB2G) matching network (MATCH_EVB2G.dsn) . . . . . . . . . . . . . . . . 41 Figure 34. LC lumped balun for divided by 4 output (MATCH_LC_LUMP_1G.dsn) . . . . . . . . . . . . . . 42 Figure 35. Evaluation board (EVB1G) matching network (MATCH_EVB1G.dsn) . . . . . . . . . . . . . . . . 43 Figure 36. Application diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Figure 37. VFQFPN28 mechanical drawing (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 5/48 Block diagram and pin configuration STW81101 1 1.1 Block diagram and pin configuration Block diagram Figure 1. Block diagram OUTBUFN OUTBUFP REF_CLK VSS_PLL VDD_PLL REXT VDD_OUTBUF V SS _OUTBUF BUF VDD_DIV4 V SS _DIV4 VDD_DIV2 V SS _DIV2 VCO BUF DIV4 BUF DIV4 DIV2 BUF REF Divider P F D UP DN V SS _CP VDD_CP C P DIV2 VDD_BUFVCO V SS _BUFVCO BUF VCO Divider ICP LOCK_DET DBUS _ S EL S CL / CLK DBUS EXTVCO_INP EXTVCO_INN EXT VCO BUF S DA / DATA VDD_VCOA VSS_VCOA VDD_VCOB VSS_VCOB VDD_ESD VSS_ESD VCO BUFF VCO Calib r ator ADD0 / LOAD ADD1 ADD2 VDD_DBUS V SS _DBUS VCTRL TEST1 TEST2 EXT_PD 6/48 STW81101 Block diagram and pin configuration 1.2 Pin configuration Figure 2. Pin connection (top view) ADD0/LOAD VDD_DBUS DBUS_SEL VDD_BUFVCO EXTVCO_INP EXTVCO_INN VDD_PLL REF_CLK TEST2 LOCK_DET VDD_ESD VDD_CP SDA/DATA SCL/CLK VDD_VCOA VDD_DIV2 VDD_OUTBUF OUTBUFP OUTBUFN VDD_DIV4 VDD_VCOB VFQFPN28 QFN 28 VCTRL Table 1. Pin No 1 2 3 4 5 6 7 8 9 Pin description Name VDD_VCOA VDD_DIV2 VDD_OUTBUF OUTBUFP OUTBUFN VDD_DIV4 VDD_VCOB VDD_ESD VCTRL Description VCOA power supply Divider by 2 power supply Output buffer power supply LO buffer positive output LO buffer negative output Divider by 4 power supply VCOB power supply ESD positive rail power supply VCO control voltage Open collector Open collector Observation TEST1 REXT ICP EXT_PD ADD2 ADD1 7/48 Block diagram and pin configuration Table 1. Pin No 10 11 12 13 14 15 16 17 18 ICP REXT VDD_CP TEST1 LOCK_DET TEST2 REF_CLK VDD_PLL EXTVCO_INN STW81101 Pin description (continued) Name Description PLL charge pump output External resistance connection for PLL charge pump Power supply for charge pump Test input 1 Lock detector Test input 2 Reference clock input PLL digital power supply External VCO negative input For test purposes only; must be connected to GND For test purposes only; must be connected to GND For test purposes only; must be connected to GND CMOS output For test purposes only; must be connected to GND Observation 19 20 21 22 23 24 25 26 27 28 EXTVCO_INP VDD_BUFVCO DBUS_SEL VDD_DBUS EXT_PD SDA/DATA SCL/CLK ADD0/LOAD ADD1 ADD2 External VCO positive input VCO buffer power supply Digital Bus Interface select SPI and I 2C CMOS input bus power supply CMOS input CMOS Bidir Schmitt triggered CMOS input CMOS input CMOS input CMOS input Power down hardware ‘0’ device ON; ‘1’ device OFF I2CBUS/SPI data line I2CBUS/SPI clock line I2CBUS address select pin/ SPI load line I2CBUS address select pin I2CBUS address select pin 8/48 STW81101 Electrical specifications 2 2.1 Table 2. Symbol AVCC DVCC Tstg Electrical specifications Absolute maximum ratings Absolute maximum ratings Parameter Analog supply voltage Digital supply voltage Storage temperature Electrical static discharge - HBM(1) - CDM-JEDEC standard - MM Values 0 to 4.6 0 to 4.6 -65 to 150 4 1.5 0.2 Unit V V °C ESD KV 1. The maximum rating of the ESD protection circuitry on pin 4 and pin 5 is 800V. 2.2 Table 3. Symbol AVDD DVDD IVDD1 IVDD2 Tamb Tj Rth j-amb Operating conditions Operating conditions (refer to Figure 36: Application diagram) Parameter Analog supply voltage Digital supply voltage VDD1 current consumption VDD2 current consumption Operating ambient temperature Maximum junction temperature Junction to ambient package thermal resistance Multilayer JEDEC board 35 -40 Test conditions Min 3.0 3.0 Typ 3.3 3.3 Max 3.6 3.6 100 15 85 125 Unit V V mA mA °C °C °C/W 2.3 Table 4. Symbol Vil Vih Vhyst Vol Voh Digital logic levels Digital logic levels Parameter Low level input voltage High level input voltage Schmitt trigger hysteresis Low level output voltage High level output voltage 0.85*Vdd 0.8*Vdd 0.8 0.4 Test conditions Min Typ Max 0.2*Vdd Unit V V V V V 9/48 Electrical specifications STW81101 2.4 Table 5. Symbol Electrical specifications All the electrical specifications are intended at 3.3V supply voltage. Electrical specifications Parameter Test conditions Min Typ Max Unit Output frequency range Direct output FOUTA Output frequency range with VCOA Divider by 2 Divider by 4 Direct output FOUTB Output frequency range with VCOB Divider by 2 Divider by 4 VCO dividers N VCO divider ratio Prescaler 16/17 Prescaler 19/20 256 361 65551 77836 3300 1650 825 3800 1900 950 3900 1950 975 4400 2200 1100 MHz MHz MHz MHz MHz MHz Reference clock and phase frequency detector Fref R FPFD Reference input frequency Reference input sensitivity Reference divider ratio PFD input frequency Prescaler 16/17 FSTEP Frequency step(2) Prescaler 19/20 Charge pump ICP VOCP ICP sink/source(3) Output voltage compliance range Direct output (FPFD = 200kHz) Spurious(4) Divider by 2 (FPFD = 400kHz) Divider by 4 (FPFD = 800kHz) VCOs Lower frequency range KVCOA VCOA sensitivity(5) Intermediate frequency range Higher frequency range Lower frequency range KVCOB VCOB sensitivity(5) pushing(5) pushing(5) Intermediate frequency range Higher frequency range VCO A VCO B 40 60 70 35 55 60 65 80 95 60 70 80 6 11 80 100 125 80 100 120 10 16 MHz/V MHz/V MHz/V MHz/V MHz/V MHz/V MHz/V MHz/V 3bit programmable 0.4 -75 -84 -92 5 Vdd-0.3 mA V dBc dBc dBc FOUT/ 65551 FOUT/ 77836 (1) 10 0.35 2 1 200 1.5 1023 16 FOUT/ 256 FOUT/ 361 MHz Vpeak MHz Hz Hz 10/48 STW81101 Table 5. Symbol VCTRL Electrical specifications Electrical specifications (continued) Parameter VCO control voltage(5) LO harmonic spurious (5) Test conditions Min 0.4 Typ Max 3 -20 Unit V dBc mA mA mA mA mA mA mA IVCOA IVCOB IVCOBUF IDIV2 IDIV4 VCOA current consumption FVCO=3.6GHz; amplitude [11] FVCO=3.6GHz; amplitude [00] FVCO=4.1GHz; amplitude [11] FVCO=4.1GHz; amplitude [00] 27 15 24 13 15 17 13 VCOB current consumption VCO buffer consumption Divider by 2 consumption Divider by 4 consumption LO output buffer PLO RL IOUTBUF Output level Return loss(5) Matched to 50 ohms DIV4 buff Current consumption DIV2 buff Direct output External VCO (for test purposes only) Frequency range Input level Current consumption PLL miscellaneous IPLL tlock Current consumption Lock up time (5),(6) Input buffer, prescaler, digital dividers, misc. 25 kHz PLL bandwidth; within 1 ppm of frequency error 12 150 mA µs VCO internal buffer 3.3 0 15 4.4 +6 GHz dBm mA 0 15 27 23 39 dBm dB mA mA mA 1. In order to achieve best phase noise performance 1V peak level is suggested. 2. The frequency step is related to the PFD input frequency as follows: - Fstep = FPFD for direct output - Fstep = FPFD/2 for divided by 2 output - Fstep = FPFD/4 for divided by 4 output 3. See the relationship between ICP and REXT in Section 5.7: Charge pump. 4. The level of the spurs may change depending on PFD frequency, charge pump current, selected channel and PLL loop BW. 5. Guaranteed by design and characterization. 6. Frequency jump from 1950 to 1800 MHz; it includes the time required by the VCO calibration procedure (7 FPFD cycles with FPFD=400kHz). 11/48 Electrical specifications STW81101 2.5 Table 6. Phase noise specification Phase noise specification Parameter Test conditions Min Typ Max Unit Phase noise performance(1) Inband phase noise floor – closed loop(2) Normalized inband phase noise floor Inband phase noise floor direct output Inband phase noise floor divider by 2 Inband phase noise floor divider by 4 PLL integrated phase noise – direct output Integrated phase noise 100Hz to 40MHz FOUT = 4 GHz, FPFD = 200kHz, FSTEP =200 kHz, PLL BW = 15kHz, ICP=4mA -36 1.3 dBc ° rms ICP=4mA, PLL BW = 50kHz; including reference clock contribution ICP=4mA, PLL BW = 50kHz; including reference clock contribution -222 dBc/Hz -222+20log(N)+10log(FPFD) dBc/Hz dBc/Hz dBc/Hz -228+20log(N)+10log(FPFD) -234+20log(N)+10log(FPFD) PLL integrated phase noise – divider by 2 Integrated phase noise 100Hz to 40MHz FOUT = 2 GHz, FPFD = 400kHz, FSTEP =200 kHz, PLL BW = 25kHz, ICP=3mA -43 0.55 dBc ° rms PLL integrated phase noise – divider by 4 Integrated phase noise 100Hz to 40MHz FOUT = 1 GHz, FPFD = 800kHz, FSTEP =200 kHz, PLL BW = 25kHz, ICP=1.5mA -51 0.23 dBc ° rms VCO A direct (3300MHz-3900MHz) – open loop(3) Phase noise @ 1 kHz Phase noise @ 10 kHz Phase noise @ 100 kHz Phase noise @ 1 MHz Phase Noise @ 10 MHz Phase Noise @ 40 MHz VCO B direct (3800MHz-4400MHz) – open loop Phase noise @ 1 kHz Phase noise @ 10 kHz Phase noise @ 100 kHz Phase noise @ 1 MHz Phase noise @ 10 MHz Phase noise @ 40 MHz (3) -56 -83 -106 -129 -149 -159 dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz -55 -83 -106 -128 -148 -158 dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz 12/48 STW81101 Table 6. Phase noise specification (continued) Parameter Test conditions Min Electrical specifications Typ Max Unit VCO A with divider by 2 (1650MHz-1950MHz) – open loop(3) Phase noise @ 1 kHz Phase noise @ 10 kHz Phase noise @ 100 kHz Phase noise @ 1 MHz Phase noise @ 10 MHz Phase noise floor @ 40 MHz VCO B with divider by 2 (1900MHz-2200MHz) – open loop Phase noise @ 1 kHz Phase noise @ 10 kHz Phase noise @ 100 kHz Phase noise @ 1 MHz Phase noise @ 10 MHz Phase noise floor @ 40 MHz VCO A with divider by 4 (825MHz-975MHz) – open loop(3) Phase noise @ 1 kHz Phase noise @ 10 kHz Phase noise @ 100 kHz Phase noise @ 1 MHz Phase noise @ 10 MHz Phase noise floor @ 40 MHz VCO B with divider by 4 (950MHz-1100MHz) – open loop Phase noise @ 1 kHz Phase noise @ 10 kHz Phase noise @ 100 kHz Phase noise @ 1 MHz Phase noise @ 10 MHz Phase noise floor @ 40 MHz (3) (3) -62 -89 -112 -135 -151.5 -155 dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz -61 -89 -112 -134 -151.5 -155 dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz -68 -95 -118 -141 -154 -155 dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz -67 -95 -118 -140 -154 -155 dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz 1. Phase noise SSB. VCO amplitude setting to value [11]. All the closed-loop performances are specified using a reference clock signal at 76.8 MHz with phase noise of -135dBc/Hz @1kHz offset, -145dBc/Hz @10kHz offset and -149.5dBc/Hz of noise floor. 2. Normalized PN = Measured PN – 20log(N) – 10log(FPFD) where N is the VCO divider ratio (N=B*P+A) and FPFD is the comparison frequency at the PFD input 3. Typical Phase Noise at centre band frequency An evaluation kit is available upon request, including a powerful simulation tool (STWPLLSim) that allows a very accurate estimation of the device’s phase noise according to the desired project parameters (VCO frequency, selected output stage, reference clock, frequency step, and so on); refer to Chapter 8: Application information for more details. 13/48 Typical performance characteristics STW81101 3 Typical performance characteristics Phase noise is measured with the Agilent E5052A Signal Source Analyzer. All closed-loop measurements are done with FSTEP=200 kHz, with the FPFD and charge pump current properly set. The loop filter configuration is depicted in Figure 36: Application diagram, and the reference clock signal is at 76.8 MHz with phase noise of -135dBc/Hz @1kHz offset, 145dBc/Hz @10kHz offset and -149.5dBc/Hz of noise floor. Figure 3. VCO A (direct output) open loop phase noise Figure 4. VCO B (direct output) open loop phase noise Figure 5. VCO A (direct output) closed loop phase noise at 3.6GHz (FSTEP=200kHz; FPFD=200kHz; ICP=3.5mA) Figure 6. VCO B (direct output) closed loop phase noise at 4.0GHz (FSTEP=200kHz; FPFD=200kHz; ICP=4mA) 1.3° rms 1.3° rms 14/48 STW81101 Typical performance characteristics Figure 7. VCO A (div. by 2 output) closed loop phase noise at 1.8GHz (FSTEP=200kHz; FPFD=400kHz; ICP=2mA) Figure 8. VCO B (div. by 2 output) closed loop phase noise at 2.0GHz (FSTEP=200kHz; FPFD=400kHz; ICP=3mA) 0.53° rms 0.55° rms Figure 9. VCO A (div. by 4 output) closed loop phase noise at 900MHz (FSTEP=200kHz; FPFD=800kHz; ICP=1.5mA) Figure 10. VCO B (div. by 4 output) closed loop phase noise at 1.0GHz (FSTEP=200kHz; FPFD=800kHz; ICP=1.5mA 0.24° rms 0 .2 3 ° rm s 15/48 Typical performance characteristics STW81101 Figure 11. PFD frequency spurs (direct output; FPFD=200kHz) Figure 12. PFD frequency spurs (div. by 2 output; FPFD=400kHz -75 dBc @200KHz -84 dBc @400KHz Figure 13. PFD frequency spurs (div. by 4 output; FPFD=800kHz) Figure 14. Settling time (final frequency=1.8 GHz; FPFD=400kHz; ICP=2mA < -92 dBc @800KHz 16/48 STW81101 General description 4 General description Figure 1: Block diagram shows the separate blocks that, when integrated, form an Integer-N PLL frequency synthesizer. The STW81101 consists of two internal low-noise VCOs with buffer blocks, a divider by 2, a divider by 4, a low-noise PFD (phase frequency detector), a precise charge pump, a 10-bit programmable reference divider, two programmable counters and a programmable dualmodulus prescaler. The 5-bit A-counter and 12-bit B-counter, in conjunction with the dual modulus prescaler P/P+1 (16/17 or 19/20), implement an N integer divider, where N = B*P +A. The division ratio of both reference and VCO dividers is controlled through the selected digital interface (I2C bus or SPI). The selection of the digital interface type is done by the proper hardware connection of the pin DBUS_SEL (0 V for I2C bus, 3.3 V for SPI). All devices operate with a power supply of 3.3 V and can be powered down when not in use. 17/48 Circuit description STW81101 5 5.1 Circuit description Reference input stage The reference input stage is shown in Figure 15. The resistor network feeds a DC bias at the Fref input while the inverter used as the frequency reference buffer is AC coupled. Figure 15. Reference frequency input buffer VDD F ref INV BUF Power Down 5.2 Reference divider The 10-bit programmable reference counter allows division of the input reference frequency to produce the input clock to the PFD. The division ratio is programmed through the digital interface. 5.3 Prescaler The dual-modulus prescaler P/P+1 takes the CML clock from the VCO buffer and divides it down to a manageable frequency for the CMOS A and B counters. The modulus P is programmable and can be set to 16 or 19. The prescaler is based on a synchronous 4/5 core whose division ratio depends on the state of the modulus input. 18/48 STW81101 Circuit description 5.4 A and B counters The 5-bit A-counter and 12-bit B-counter, in conjunction with the selected dual modulus (16/17 or 19/20) prescaler, make it possible to generate output frequencies which are spaced only by the reference frequency divided by the reference division ratio. Thus, the division ratio and the VCO output frequency are given by these formulas: N = B× P+A ( B × P + A ) × F ref F VCO = -----------------------------------------------R where: FVCO: output frequency of VCO P: modulus of dual modulus prescaler (16 or 19 selected through the digital interface) B: division ratio of the main counter A: division ratio of the swallow counter Fref: input reference frequency R: division ratio of reference counter N: division ratio of PLL For a correct working of the VCO divider, B must be strictly higher than A. A can take any value ranging from 0 to 31. The range of N can vary from 256 to 65551 (P=16) or from 361 to 77836 (P=19). Figure 16. VCO divider diagram VCOBUFPrescaler 16/17 or 19/20 VCOBUF+ To PFD modulus 5-bit A-counter 12-bit B-counter PC00403 19/48 Circuit description STW81101 5.5 Phase frequency detector (PFD) The PFD takes inputs from the reference and the VCO dividers and produces an output proportional to the phase error. The PFD includes a delay gate that controls the width of the anti-backlash pulse. This pulse ensures that there is no dead zone in the PFD transfer function. Figure 17 is a simplified schematic of the PFD. Figure 17. PFD diagram VDD D FF F ref R Up Delay R F ref VDD D FF Down ABL 5.6 Lock detect This signal indicates that the difference between rising edges of both UP and DOWN PFD signals is found to be shorter than the fixed delay (roughly 5 ns). The Lock Detect signal is high when the PLL is locked and low when the PLL is unlocked. Lock Detect consumes current only during PLL transients. 5.7 Charge pump This block drives two matched current sources, IUP and IDOWN, which are controlled respectively by UP and DOWN PFD outputs. The nominal value of the output current is controlled by an external resistor (to be connected to the REXT input pin) and a 3-bit word that allows selection among 8 different values. The minimum value of the output current is: IMIN = 2*VBG/REXT (VBG~1.17 V) 20/48 STW81101 Table 7. CPSEL2 0 0 0 0 1 1 1 1 Circuit description Current value vs. selection CPSEL1 0 0 1 1 0 0 1 1 CPSEL0 0 1 0 1 0 1 0 1 Current IMIN 2*IMIN 3*IMIN 4*IMIN 5*IMIN 6*IMIN 7*IMIN 8*IMIN Value for REXT=4.7 KΩ 0.5 mA 1.0 mA 1.5 mA 2.0 mA 2.5 mA 3.0 mA 3.5 mA 4.0 mA Note: The current is output on pin ICP. During VCO auto calibration, the ICP and VCTRL pins are forced to VDD/2 Figure 18. Loop filter connection VDD VCTRL BUF C3 R3 Charge Pump ICP R1 C2 C1 BUF Cal bit 21/48 Circuit description STW81101 5.8 5.8.1 Voltage controlled oscillators VCO selection The STW81101 integrates two low-noise VCOs to cover a wide band from: ● ● ● 3300MHz to 4400MHz (direct output) 1650MHz to 2200MHz (selecting divider by 2) 825MHz to 1100MHz (selecting divider by 4) VCO A frequency range is 3300 MHz to 3900MHz. VCO B frequency range 3800 MHz to 4400MHz. 5.8.2 VCO frequency calibration Both VCOs can operate on 32 frequency ranges that are selected by adding or subtracting capacitors from the resonator. These frequency ranges are intended to cover the wide band of operation and compensate for process variation on the VCO center frequency. The range is automatically selected when the SERCAL bit rises from 0 to 1. The charge pump is inhibited, and the ICP and VCTRL pins are at VDD/2 volts. The ranges are then tested with this VCO input voltage to select the one nearest to the desired output frequency (FOUT = N*Fref/R). After this selection, the signal ENDCALB (which means End of Calibration) falls to 0, and the charge pump is once again enabled. Additionally, the SERCAL bit should be reset to 0 before the next channel step. To enable a fast settle, the PLL needs only to perform fine adjustment around VDD/2 on the loop filter to reach FOUT. Figure 19. VCO sub-bands frequency characteristics 22/48 STW81101 Circuit description The SERCAL bit should be set to 1 at each division ratio change. Note that to reset the auto calibrator state machine after a power-up, and before the first calibration in any case, the INITCAL bit should be set to 1 and back to 0 (the Power On Reset circuitry does this automatically). The calibration requires approximately 7 periods of the PFD frequency. The maximum allowed FPFD to perform the calibration process is 1 MHz. When using a higher FPFD , follow the steps below: 1. 2. Calibrate the VCO at the desired frequency with an FPFD less than 1 MHz. Set the A, B and R dividers ratio for the desired FPFD . 5.8.3 VCO voltage amplitude control The voltage swing of the VCOs can be adjusted over four levels by means of two dedicated programming bits (PLL_A1 and PLL_A0). This setting trades current consumption with phase noise performances of the VCO. Higher amplitudes provide best phase noise, whereas lower amplitudes save power. Table 8 gives the voltage swing level expected on the resonator nodes, the current consumption, and the phase noise @1MHz. Table 8. VCO A performances versus amplitude setting (Freq=3.6GHz) Differential voltage swing (Vp) 1.1 1.3 1.9 2.1 Current consumption (mA) 15 16 24 27 PN @1MHz (dBc/Hz) -124 -125 -128.5 -129 PLL_A[1:0] 00 01 10 11 Table 9. VCO B performances vs. amplitude setting (Freq=4.1GHz) Differential voltage swing (Vp) 1.1 1.3 1.9 2.1 Current consumption (mA) 13 15 22 24 PN @1MHz (dBc/Hz) -123 -125 -127.5 -128 PLL_A[1:0] 00 01 10 11 23/48 I2C bus interface STW81101 6 I2C bus interface The I2C bus interface is selected by hardware connection of the pin #21 (DBUS_SEL) to 0 V. Data is transmitted from microprocessor to the STW81101 through the 2-wire (SDA and SCL) I2C bus interface. The STW81101 is always a slave device. The I2C bus protocol defines any device that sends data on the bus as a transmitter, and any device that reads the data as a receiver. The device controlling the data transfer is the master, and the others are slaves. The master always initiates the transfer and provides the serial clock for synchronization. 6.1 6.1.1 General features Data validity Data changes on the SDA line must only occur when the SCL is low. SDA transitions while the clock is high are used to identify a START or STOP condition. Figure 20. Data validity SDA SCL Data line Stable data Valid Change data allowed PC00406 6.1.2 START and STOP conditions START condition A START condition is identified by a transition of the data bus SDA from high to low while the clock signal SCL is stable in the high state. A START condition must precede any data transfer command. STOP condition A STOP condition is identified by a transition of the data bus SDA from low to high while the clock signal SCL is stable in the high state. A STOP condition terminates communications between the STW81101 and the bus master. 24/48 STW81101 Figure 21. START and STOP conditions I2C bus interface SCL SDA START STOP 6.1.3 Byte format and acknowledge Every byte put on the SDA line must be 8 bits long, and be followed by an acknowledge bit to indicate a successful data transfer. Data is transferred with the most significant bit (MSB) first. The transmitter releases the SDA line after sending 8 bits of data. During the 9th clock pulse, the receiver pulls the SDA line low to acknowledge the receipt of 8 bits of data. Figure 22. Byte format and acknowledge S CL 1 2 3 7 8 9 // SDA START MSB // Acknowledgement from receiver 6.1.4 Device addressing The master must first initiate with a START condition to communicate with the STW81101, and then send 8 bits (MSB first) on the SDA line which correspond to the device select address and the read or write mode. The first 7 MSBs are the device address identifier, which corresponds to the I2C bus definition. For the STW81101, the address is set at “1100A2A1A0”, 3 bits programmable. The 8th bit (LSB) is the read or write (RW) operation bit, which is set to 1 in read mode and to 0 in write mode. Following a START condition, the STW81103 identifies the device address on the bus and, if matched, acknowledges the identification on the SDA bus during the 9th clock pulse. 25/48 I2C bus interface STW81101 6.1.5 Single-byte write mode Following a START condition, the master sends a device select code with the RW bit set to 0. The STW81101 sends an acknowledge and waits for the 1-byte internal sub-address that provides access to the internal registers. After receiving the sub-address internal byte, the STW81101 again responds with an acknowledge. A single-byte write to sub-address 00H changes the FUNCTIONAL_MODE register, a single-byte write with sub-address 04H changes the CONTROL register, and so on. Table 10. S Single-byte write mode 0 ack sub-address byte ack DATA IN ack P 1100A2A1A0 6.1.6 Multi-byte write mode The multi-byte write mode can start from any internal address. The master sends the data bytes, and each one is acknowledged. The master then terminates the transfer by generating a STOP condition. The sub-address decides the starting byte. For example, a multi-byte with sub-address 01H and 2 DATA_IN bytes will change the B_COUNTER and A_COUNTER registers (01H,02H), and a multi-byte with sub-address 00H and 6 DATA_IN bytes changes all the STW81101 registers. Table 11. S Multi-byte write mode 0 ack sub-address byte ack DATA IN ack .... DATA IN ack P 1100A2A1A0 6.1.7 Current byte address read mode In the current byte address read mode, following a START condition, the master sends the device address with the RW bit set to 1. Note that no sub-address is needed since there is only one read register. The STW81101 acknowledges this and outputs the data byte. The master does not acknowledge the received byte, and terminates the transfer with a STOP condition. Table 12. S Current byte address read mode 1100 A2 A1 A0 1 ack DATA OUT No ack P 26/48 STW81101 I2C bus interface 6.2 Timing specification Figure 23. Data and clock SDA SCL t cwl t cs t ch t cwh Table 13. tcs tch tcwh tcwl Data and clock timing specifications Parameter Data to clock setup time Data to clock hold time Clock pulse width high Clock pulse width low Minimum time 2 2 10 5 Units ns ns ns ns Symbol Figure 24. Start and stop SDA SCL t start t stop 27/48 I2C bus interface Table 14. tstart tstop STW81101 Start and stop timing specifications Parameter Clock to data start time Data to clock down stop time Minimum time 2 2 Units ns ns Symbol Figure 25. Ack SDA 8 SCL 9 t d1 t d2 Table 15. td1 td2 Ack timing specifications Parameter Ack begin delay Ack end delay Minimum time 2 2 Units ns ns Symbol 28/48 STW81101 I2C bus interface 6.3 I2C registers STW81101 has 6 write-only registers and 1 read-only register. 6.3.1 Write-only registers Table 16 gives a short description of the write-only registers. Table 16. Write-only registers DEC code 0 1 2 3 4 5 Description FUNCTIONAL_MODE B_COUNTER A_COUNTER REF_DIVIDER CONTROL CALIBRATION HEX code 0x00 0x01 0x02 0x03 0x04 0x05 FUNCTIONAL_MODE MSB b7 PD6 b6 PD5 b5 PD4 b4 PD3 b3 PD2 b2 PD1 b1 PD0 LSB b0 B11 The FUNCTIONAL_MODE register selects different functional modes for the STW81101 synthesizer according to Table 17: Table 17. Functional modes of the FUNCTIONAL_MODE register Description Power down mode Enable VCO A, output frequency divided by 2 Enable VCO B, output frequency divided by 2 Enable external VCO, output frequency divided by 2 Enable VCO A, output frequency divided by 4 Enable VCO B, output frequency divided by 4 Enable external VCO, output frequency divided by 4 Enable VCO A, direct output Enable VCO B, direct output Enable external VCO, direct output Decimal value 0 1 2 3 4 5 6 7 8 9 29/48 I2C bus interface STW81101 B_COUNTER MSB b7 B10 b6 B9 b5 B8 b4 B7 b3 B6 b2 B5 b1 B4 LSB b0 B3 B[10:3]. Counter value (bit B11 in the previous register, bits B[2:0] in the next register) A_COUNTER MSB b7 B2 b6 B1 b5 B0 b4 A4 b3 A3 b2 A2 b1 A1 LSB b0 A0 Bits B[2:0] for B_COUNTER, A_COUNTER value. REF_DIVIDER MSB b7 R9 b6 R8 b5 R7 b4 R6 b3 R5 b2 R4 b1 R3 LSB b0 R2 Reference clock divider ratio R[9:1] (bits R1, R0 in the next register). CONTROL MSB b7 R1 b6 R0 b5 PLL_A1 b4 PLL_A0 b3 CPSEL2 b2 CPSEL1 b1 CPSEL0 LSB b0 PSC_SEL The CONTROL register is used to set the charge pump current, the VCO output voltage amplitude and the prescaler modulus: PLL_A[1:0]: CPSEL[2:0]: PSC_SEL: VCO amplitude charge pump output current prescaler modulus select ('0' for P=16, '1' for P=19) The LO output frequency is programmed by setting the proper values for A, B and R according to the following formula: F OUT =D R F REF – CLK × ( B × P + A ) × ---------------------------------R where DR equals { 1 0.5 for direct output for output divided by 2 0.25 for output divided by 4 30/48 STW81101 and P is the selected prescaler modulus. I2C bus interface CALIBRATION MSB b7 INITCAL b6 SERCAL b5 SELEXTCAL b4 CAL4 b3 CAL3 b2 CAL2 b1 CAL1 LSB b0 CAL0 This register controls the VCO calibrator using the following values: INITCAL: SERCAL: SELEXTCAL: CAL[4:0]: resets the auto-calibrator state machine (writing to 1 and back to 0) at 1, starts the VCO auto-calibration (should be reset to 0 at the end of calibration) for test purposes only; must be set to 0 for test purposes only; must be set to 0 6.3.2 Read-only register MSB b7 DEV_ID1 b6 DEV_ID0 b5 b4 b3 b2 b1 LSB b0 LOCK_DET INTCAL4 INTCAL3 INTCAL2 INTCAL1 INTCAL0 This register is automatically addressed in the 'current byte address read mode', using the following values: DEV_ID[1:0]: LOCK_DET: INTCAL[4:0]: device identifier bits; returns 00 1 when PLL is locked internal value of the VCO control word 6.3.3 Default configuration At power on reset, the following configuration is automatically loaded: – – – – – – – FUNCTIONAL MODE = 1 (VCOA with divided by 2 output) A COUNTER = 8 B COUNTER = 562 R DIVIDER = 192 PLL_A[1:0] = [10] CP_SEL[2:0] = [111] PSC_MOD_SEL set to "0" (modulus = 16) This corresponds to an output frequency of 1800MHz and a PFD frequency of 400kHz using a 76.8MHz reference clock (calibration algorithm of the VCO is automatically started). 31/48 I2C bus interface STW81101 6.4 VCO calibration procedure Calibration of the VCO center frequency is activated when the SERCAL bit (CALIBRATION register bit[6]) transitions from 0 to 1. To program the device properly while ensuring VCO calibration, perform the following steps before every channel change: 1. Program all the registers using a multi-byte write sequence with the desired settings (functional mode, B and A counters, R counter, VCO amplitude, charge pump, prescaler modulus), and all the bits of the CALIBRATION register (05H) set to 0. Program the CALIBRATION register using a single-byte write sequence (subaddress 05H) with the SERCAL bit set to 1. The maximum allowed PFD frequency (FPFD) during calibration is 1 MHz; if you want a FPFD higher than 1 MHz, perform the following additional steps: a) Perform all the steps of the calibration procedure, making sure to program the desired VCO frequency with proper settings for the R, B and A counters so that FPFD is ≤1 MHz. Program the device with the desired VCO and PFD frequency settings according to step 1) above. 2. 3. b) 32/48 STW81101 SPI digital interface 7 7.1 SPI digital interface General features The SPI digital interface is selected by hardware connection of the pin #21 (DBUS_SEL) to 3.3V. The STW81101 IC is programmed by means of a high-speed serial-to-parallel interface with write option only. The 3-wire bus can be clocked at a frequency as high as 100MHz to allow fast programming of the registers containing the data for RF IC configuration. The chip is programmed through serial words with a full length of 26 bits. The first 2 MSBs represent the address of the registers, and the 24 LSBs represent the value of the registers. Each data bit is stored in the internal shift register on the rising edge of the CLOCK signal. The outputs of the selected register are sent to the device on the rising edge of the LOAD signal. Figure 26. SPI input and output bit order Last bit sent (LSB)0 DATA 2 1 23 25(MSB) 24 A1 LOAD Address decoder D23 (MSB) LOAD #4 D0 (LSB) Reg.#0 Reg.#1 Reg.#4 33/48 SPI digital interface Table 18. MSB Address Data for register (24 bits) STW81101 SPI data structure (MSB is sent first) LSB A1 A0 D23 D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Table 19. Address A1 0 0 1 1 A0 0 1 0 1 Address decoder and outputs Outputs Data bits D23-D0 24 24 24 24 No 0 1 2 3 Name ST1 ST2 ST3 ST4 Function Reference divider, VCO amplitude, VCO calibration, charge pump current, prescaler modulus Functional modes, VCO dividers Reserved Reserved 7.2 Timing specification Figure 27. SPI timing specification tsetup thold Data Clock MSB MSB-1 LSB tclk_loadf tdk Load t clk_loadr tload Table 20. Parameter tsetup thold tclk tload tclk_loadr tclk_loadf SPI timing specification Description Data to clock setup time Data to clock hold time Clock cycle period Load pulse width Clock to load rising edge Clock to load falling edge Min. 0.8 0.2 10 3 2 0.5 Typ. Max. Unit ns ns ns ns ns ns 34/48 STW81101 SPI digital interface 7.3 Bit tables Table 21. Bits at 00h and ST1 Register name = ST1 Description Serial interface address = 00h Bit [23] [22] [21] [20] [19] [18] [17] [16] [15] [14] [13] [12] [11] [10] [9] [8] [7] [6] [5] [4] [3] [2] [1] [0] Name R9 R8 R7 R6 R5 Reference clock divider ratio R4 R3 R2 R1 R0 PLL_A1 VCO amplitude control PLL_A0 CPSEL2 CPSEL1 CPSEL0 PSC_SEL INITCAL SERCAL SELEXTCAL CAL4 CAL3 CAL2 CAL1 CAL0 For test purposes only; must be set to 0 Prescaler modulus select (0 for P=16, 1 for P=19) For test purposes only; must be set to 0 Enable VCO calibration (see Section 7.4) For test purposes only; must be set to 0 Charge pump output current control 35/48 SPI digital interface Table 22. Bits at 01h and ST2 Register name = ST2 Description STW81101 Serial interface address = 01h Bit [23] [22] [21] [20] [19] [18] [17] [16] [15] [14] [13] [12] [11] [10] [9] [8] [7] [6] [5] [4] [3] [2] [1] [0] Name PD6 PD5 PD4 PD3 PD2 PD1 PD0 B11 B10 B9 B8 B7 B6 B Counter Bits B5 B4 B3 B2 B1 B0 A4 A3 A2 A1 A0 A Counter Bits DEVICE FUNCTIONAL MODES 0. Power down 1. Enable VCO A, output frequency divided by 2 2. Enable VCO B, output frequency divided by 2 3. Enable external VCO, output frequency divided by 2 4. Enable VCO A, output frequency divided by 4 5. Enable VCO B, output frequency divided by 4 6. Enable external VCO, output frequency divided by 4 7. Enable VCO A, direct output 8. Enable VCO B, direct output 9. Enable external VCO, direct output The LO output frequency is programmed by setting the proper values for A, B and R according to the following formula: F REF – CLK F OUT = D R × ( B × P + A ) × --------------------------R where DR equals { 1 0.5 for direct output for output divided by 2 0.25 for output divided by 4 and P is the selected prescaler modulus. 36/48 STW81101 SPI digital interface 7.3.1 Default configuration At power on reset, the following configuration is automatically loaded: – – – – – – – FUNCTIONAL MODE = 1 (VCOA with divided by 2 output) A COUNTER = 8 B COUNTER = 562 R DIVIDER = 192 PLL_A[1:0] = [10] CP_SEL[2:0] = [111] PSC_MOD_SEL set to 0 (Modulus = 16) This corresponds to an output frequency of 1800MHz and a PFD frequency of 400kHz using a 76.8MHz reference clock (calibration algorithm of the VCO is automatically started). 7.4 VCO calibration procedure Calibration of the VCO center frequency is activated by a transition of the SERCAL bit (ST1 register bit[6]) from 0 to 1. To program the device properly while ensuring VCO calibration, perform the following steps before every channel change: 1. 2. 3. 4. Program the ST1 register with the desired settings (R counter, VCO amplitude, charge pump, prescaler modulus) and with the SERCAL bit set to 0. Program the ST2 register with the desired settings (functional mode, B and A counters). Program the ST1 register with the desired settings (R counter, VCO amplitude, charge pump, prescaler modulus) and with the SERCAL bit set to 1. The maximum allowed PFD frequency (FPFD) during calibration is 1 MHz; if you want a FPFD higher than 1MHz, perform the following additional steps: a) Perform all the steps of the calibration procedure, making sure to program the desired VCO frequency with proper settings of the R, B and A counters so that FPFD is ≤1MHz. Program the device with the desired VCO and PFD frequency settings using only steps 1) and 2) above. b) 37/48 Application information STW81101 8 Application information The STW81101 features three different alternately selectable bands: direct output (3.3 to 4.4GHz), divided by 2 (1.65 to 2.2GHz) and divided by 4 (850 to 1100MHz). To achieve a suitable power level, a good matching network is necessary to adapt the output stage to a 50Ω load. Moreover, since most commercial RF components have single-ended input and output terminations, a differential to single-ended conversion may be required. The different matching configurations shown below for each of the three bands are suggested as a guideline when designing your own application board. Inside the evaluation kit is the ADS design for each matching configuration suggested in this chapter. The name of the corresponding ADS design is given in each figure. The ADS designs provide only a first indication of the output stage matching, and should be reworked according to the choices of layout, board substrate, components and so on. The ADS designs of the evaluation boards are provided with a complete electromagnetic modelling (board, components, and so on). 8.1 Direct output If you do not need a differential to single conversion, you can match the output buffer of the STW81101 in the simple way shown in Figure 28. This illustrates a differential to singleended output network in the 3.3 - 4.4GHz range (MATCH_LC_LUMP_4G_DIFF.dsn). Figure 28. Differential/single-ended output network (MATCH_LC_LUMP_4G_DIFF.dsn) Vcc 100 ohm 5.5nH 10pF 50 ohm RF OUTP 10pF RF OUTN 100 ohm 5.5nH 50 ohm Vcc Since most discrete components for microwave applications are single-ended, you can easily use one of the two outputs and terminate the other one to 50Ω with a 3dB power loss. 38/48 STW81101 Application information Alternatively, you can combine the two outputs in other ways. A first topology for the direct output (3.3GHz to 4.4GHz) is suggested in Figure 29. It basically consists of a simple LC balun and a matching network to adapt the output to a 50Ω load. The two LC networks shift output signal phase of -90° and +90°, thus combining the two outputs. This topology, designed for a center frequency of 4GHz, is intrinsically narrow-band since the LC balun is tuned at a single frequency. If the application requires a different sub-band, the LC combiner can be easily tuned to the frequency of interest. Figure 29. LC lumped balun and matching network (MATCH_LC_LUMP_4G.dsn) Vcc 50 ohm 1.9nH 0.8pF 1.9nH RF OUTP 0.8pF 2.5pF 1.9nH RF 50 ohm OUTN 0.8pF 50 ohm 1.9nH 0.8pF Vcc The 1.9nH shunt inductor works as a DC feed for one of the open collector terminals as well as a matching element along with the other components. The 1.9nH series inductors are used to resonate the parasitic capacitance of the chip. For optimum output matching, it is recommended to use 0402 Murata or AVX capacitors and 0403 or 0604 HQ Coilcraft inductors. It is also advisable to use short interconnection paths to minimize losses and undesired impedance shift. An alternative topology that permits a more broadband matching as well as balanced to unbalanced conversion, is shown in Figure 30. 39/48 Application information STW81101 Figure 30. Evaluation board (EVB4G) matching network (MATCH_EVB4G.dsn) Vcc 50 ohm 5.5nH 12pF 12pF 2:1 12pF 4.7pF RF OUTP RF 1pF 1pF 1.2pF 1.2pF 50 ohm OUTN 50 ohm 5.5nH Vcc For differential to single conversion, the 50 to 100Ω Johanson balun is recommended (3700BL15B100). 8.2 Divided by 2 output If your application does not require a balanced to unbalanced conversion, the output matching reduces to the simple circuit shown below (Figure 31), which illustrates a differential to single-ended output network in the 1.65 - 2.2GHz range (MATCH_LC_LUMP_2G_DIFF.dsn). You can easily use this solution to provide one singleended output that terminates the other output at 50Ω with a 3dB power loss. Figure 31. Differential/single-ended output network (MATCH_LC_LUMP_2G_DIFF.dsn) Vcc 50 ohm 22nH 10pF 50 ohm RF OUTP 10pF RF OUTN 50 ohm 22nH 50 ohm Vcc 40/48 STW81101 Application information A first solution to combine the differential outputs is the lumped LC type balun tuned in the 2GHz band (Figure 32). Figure 32. LC lumped balun for divided by 2 output (MATCH_LC_LUMP_2G.dsn) Vcc 50 ohm 2.7nH 2pF 2.7nH RF OUTP 2pF 3pF 2.7nH 3nH RF OUTN 50 ohm 2pF 50 ohm 2.7nH 2pF Vcc The same recommendation for the SMD components also applies to the divided by 2 output. Another topology suited to combining the two outputs for the divided by 2 frequencies is represented in Figure 33. Figure 33. Evaluation board (EVB2G) matching network (MATCH_EVB2G.dsn) Vcc 50 ohm 5.5nH 22pF 22pF 2:1 22pF RF 1.9nH OUTP RF 1.2pF 50 ohm OUTN 50 ohm 5.5nH Vcc 41/48 Application information STW81101 For differential to single conversion, the 50 to 100Ω Johanson balun (1600BL15B100) is recommended. 8.3 Divided by 4 output The topology, components, values and considerations of Figure 31, also apply to the divided by 4 output (MATCH_LC_LUMP_1G_DIFF.dsn). As for the previous sections, a solution to combine the differential outputs is the lumped LC type balun tuned in the 1GHz band (Figure 34). Figure 34. LC lumped balun for divided by 4 output (MATCH_LC_LUMP_1G.dsn) Vcc 25 ohm 5.5nH 4pF 5.5nH RF OUTP 4pF 6pF 5.5nH RF 14nH 50 ohm OUTN 4pF 25 ohm 5.5nH 4pF Vcc If you prefer to use an RF balun, you can adapt the topology depicted in Figure 33, and change the balun and the matching components (Figure 35). The suggested balun for the 0.8 - 1.1GHz frequency range is the 1:1 Johanson 900BL15C050. 42/48 STW81101 Application information Figure 35. Evaluation board (EVB1G) matching network (MATCH_EVB1G.dsn) Vcc 25 ohm 18nH 8.2pF 22pF 1:1 8.2pF RF 2.1nH OUTP RF 0.5pF 50 ohm OUTN 25 ohm 18nH Vcc 8.4 Evaluation kit An evaluation kit can be delivered upon request, including the following: ● ● ● ● ● Evaluation board GUI (graphical user interface) to program the device Measured S parameters of the RF output ADS2005 schematics providing guidelines for application board design STWPLLSim software for PLL loop filter design and noise simulation Three different evaluation kits are available, each optimized for one of the following frequency ranges: ● ● ● 1GHz 2GHz 4GHz When ordering, please specify one of the following order codes: Table 23. Order code of the evaluation kit Part number STW81101-EVB1G STW81101-EVB2G STW81101-EVB4G Description 1GHz frequency range - divider by 4 output optimized 2GHz frequency range - divider by 2 output optimized 4GHz frequency range - direct output optimized The three evaluation kits differ only for the output stage network and can be adapted from one frequency band variant to a different one replacing properly the matching components and the balun. 43/48 Application diagram STW81101 9 Application diagram Figure 36. Application diagram From/to microcontroller 100 100 100 15p 15p 15p ADD0/LOAD SCL/CLK 1n 22p 10 SDA/DATA E XT_P D ADD2 ADD1 VDD1 V DD_DBUS I2C SPI VDD2 VDD_VCOA VDD_DIV2 DBUS _S EL VDD_BUFVCO VDD1 RF Out VDD_OUTBUF EXTVCO_INP OUTBUFP STW81101 STW81103 1n EXTVCO_INN 22p 10 OUTBUFN VDD_PLL VDD_DIV4 REF_CLK ref clk 1.8n 51 VDD _CP VDD_E S D VCTR L VDD1 1n 22p 10 RE X T ICP 4.7K VDD1 2.2K 8.2K 68p 2.7n 1n 22p 10µ 270p loop filter T E ST1 VDD_VCOB LO CK_DET VDD1 TE S T2 to microcontroller Note: 1 2 3 See Chapter 8: Application information for further information on output matching topology. EXT_PD, ADD2, ADD1 (and ADD0 when the I2C bus is selected) can be hard wired directly on the board. Loop filter values are for FSTEP = 200kHz. 44/48 STW81101 Package mechanical data 10 Package mechanical data In order to meet environmental requirements, ST offers these devices in ECOPACK® packages, which have a lead-free second level interconnect. The category of second level interconnect is marked on the package and on the inner box label, in compliance with JEDEC standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: http://www.st.com. Figure 37. VFQFPN28 mechanical drawing (Note 1) 7655832 A Note: 1 2 VFQFPN stands for Thermally Enhanced Very thin Fine pitch Quad Flat Package No lead. (Very thin: A=1.00 Max) Details of the terminal 1 identifier are optional, but if given, must be located on the top surface of the package by using either a mold or marked features. 45/48 Package mechanical data Table 24. Ref. A A1 A2 A3 b D D1 D2 E E1 E2 e L P K ddd 0.350 2.950 2.950 4.850 0.180 4.850 STW81101 Package dimensions Min. 0.800 Typ. 0.900 0.020 0.650 0.200 0.250 5.000 4.750 3.100 5.000 4.750 3.100 0.500 0.550 0.750 0.600 14 0.080 3.250 3.250 5.150 0.300 5.150 Max. 1.000 0.050 1.000 Unit mm mm mm mm mm mm mm mm mm mm mm mm mm mm degrees mm 46/48 STW81101 Ordering information 11 Ordering information Table 25. Order codes Temp range, ° C -40 to 85 -40 to 85 Package VFQFPN28 VFQFPN28 Tray Tape and reel Packing Part number STW81101AT STW81101ATR 12 Revision history Table 26. Date 06-Mar-2006 16-Jun-2006 Document revision history Revision 1 2 Initial release. Changed from preliminary data to maturity. Updated Chapter 2: Electrical specifications; Chapter 8: Application information and Chapter 9: Application diagram. Updated Section 6.4: VCO calibration procedure, and pin #23 description in Table 1. Moved order codes to Chapter 11. Changes 13-Aug-2007 3 47/48 STW81101 Please Read Carefully: Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale. Purchasers are solely responsible for the choice, selection and use of the ST products and services described herein, and ST assumes no liability whatsoever relating to the choice, selection or use of the ST products and services described herein. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. 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