STW81102-EVB1G

STW81102 Multi-band RF frequency synthesizer with integrated VCOs Feature summary ■ ■ Integer-N Frequency Synthesizer Dual differential integrated VCOs with automatic center frequency calibration: – 3000 - 3620 MHz (Direct output) – 4000 - 4650 MHz (Direct output) – 1500 - 1810 MHz (Internal divider by 2) – 2000 - 2325 MHz (Internal divider by 2) – 750 - 905 MHz (Internal divider by 4) – 1000 - 1162.5 MHz (Internal divider by 4) Excellent integrated phase noise Fast lock time: 150µs Dual modulus programmable prescaler (16/17 or 19/20) 2 programmable counters to achieve a feedback division ratio from 256 to 65551 (prescaler 16/17) and from 361 to 77836 (prescaler 19/20). Programmable reference frequency divider (10 bits) Phase frequency comparator and charge pump Programmable charge pump current Digital Lock Detector Dual Digital Bus Interface: SPI and I2C bus with 3 bit programmable address (1100A2A1A0) 3.3V Power Supply Power down mode (HW and SW) Small size exposed pad VFQFPN28 package 5x5x1.0mm Process: BICMOS 0.35µm SiGe VFQFPN28 Applications ■ ■ ■ ■ ■ ■ 2.5G and 3G Cellular Infrastructure Equipment CATV Equipment ■ Instrumentation and Test Equipment ■ Other Wireless Communication Systems Description The STMicroelectronics STW81102 is an integrated RF synthesizer with voltage controlled oscillators (VCOs). Showing high performance, high integration, low power, and multi-band performances, STW81102 is a low cost one chip alternative to discrete PLL and VCOs solutions. STW81102 includes an Integer-N frequency synthesizer and two fully integrated VCOs featuring low phase noise performance and a noise floor of -155dBc/Hz. The combination of wide frequency range VCOs (thanks to centerfrequency calibration over 32 sub-bands) and multiple output options (direct output, divided by 2 or divided by 4) allows to cover from 750MHz to 905MHz and 1000MHz to 1162.5MHz, from 1500MHz to 1810MHz and 2000MHz to 2325MHz, from 3000MHz to 3620MHz and 4000MHz to 4650MHz bands. The STW81102 is designed with STMicroelectronics advanced 0.35µm SiGe process. ■ ■ ■ ■ ■ ■ ■ ■ ■ Order codes Part number STW81102AT STW81102ATR Temp range, °C -40 to 85 -40 to 85 Package VFQFPN28 VFQFPN28 Packing Tray Tape & Reel June 2006 Rev 2 1/43 www.st.com 1 Contents STW81102 Contents 1 Block diagram and pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 1.1 1.2 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2 Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.1 2.2 2.3 2.4 2.5 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Digital logic levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Phase noise specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3 4 Typical performance characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 General description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4.1 Circuit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4.1.1 4.1.2 4.1.3 4.1.4 4.1.5 4.1.6 4.1.7 4.1.8 Reference input stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Reference divider . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 A and B counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Phase frequency detector (PFD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Lock detect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Charge pump . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Voltage controlled oscillators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 VCO Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 VCO Frequency Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 VCO Voltage Amplitude Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 5 I2C bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 5.1 General features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 5.1.1 5.1.2 5.1.3 5.1.4 5.1.5 Data validity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 START condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 STOP condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Byte format and acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Device addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 2/43 STW81102 5.1.6 5.1.7 5.1.8 Contents Single-byte write mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Multi-byte write mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Current byte address read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 5.2 5.3 Timing specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 I2C registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 5.3.1 5.3.2 5.3.3 5.3.4 5.3.5 5.3.6 5.3.7 5.3.8 FUNCTIONAL_MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 B_COUNTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 A_COUNTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 REF_DIVIDER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 CONTROL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 CALIBRATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 READ-ONLY register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Default configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 5.4 VCO calibration procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 6 SPI digital interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 6.1 6.2 6.3 6.4 General features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Timing specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Bits table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 6.3.1 Default configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 VCO calibration procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 7 Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 7.1 7.2 7.3 7.4 Direct Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Divided by 2 Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Divided by 4 Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Evaluation Kit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 8 9 10 Application diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 3/43 List of tables STW81102 List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Table 24. Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Operating conditions (Refer to application diagram) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Digital logic levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Phase noise specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Current value vs selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 VCO A performances vs. amplitude setting (Freq=3.3GHz). . . . . . . . . . . . . . . . . . . . . . . . 21 VCO B performances vs. amplitude setting (Freq=4.3GHz). . . . . . . . . . . . . . . . . . . . . . . . 21 Single-byte write mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Multi-byte write mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Current Byte Address Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Data and clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Start and stop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Write-only registers list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Different functional mode of the FUNCTIONAL_MODE register . . . . . . . . . . . . . . . . . . . . 26 SPI data structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Address decoder and outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 SPI Timing specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Bits (Serial Interface Address = 00h; Register name = ST1) . . . . . . . . . . . . . . . . . . . . . . . 32 Bits (Serial Interface Address = 01h; Register name = ST2) . . . . . . . . . . . . . . . . . . . . . . . 33 Order code of the evaluation kit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 4/43 STW81102 List of figures List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. Figure 27. Figure 28. Figure 29. Figure 30. Figure 31. Figure 32. Figure 33. Figure 34. Figure 35. Figure 36. Figure 37. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Pin connection (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 VCO A (Direct output) open loop phase noise . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 VCO B (Direct output) open loop phase noise . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 VCO A (Direct output) closed loop phase noise at 3.6GHz . . . . . . . . . . . . . . . . . . . . . . . . 14 VCO B (Direct output) closed loop phase noise at 4.3GHz . . . . . . . . . . . . . . . . . . . . . . . . 14 VCO A (Div. by 2 output) closed loop phase noise at 1.65GHz . . . . . . . . . . . . . . . . . . . . . 15 VCO B (Div. by 2 output) closed loop phase noise at 2.15GHz . . . . . . . . . . . . . . . . . . . . . 15 VCO A (Div. by 4 output) closed loop phase noise at 825MHz . . . . . . . . . . . . . . . . . . . . . 15 VCO B (Div. by 4 output) closed loop phase noise at 1.075GHz . . . . . . . . . . . . . . . . . . . . 15 PFD Frequency Spurs (Direct Output; FPFD=200KHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 PFD Frequency Spurs (Div. by 2 Output; FPFD=400KHz) . . . . . . . . . . . . . . . . . . . . . . . . . 16 PFD Frequency Spurs (Div. by 4 Output; FPFD=800KHz) . . . . . . . . . . . . . . . . . . . . . . . . . 16 Settling Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Reference Frequency Input Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 VCO Divider Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 PFD diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Loop filter connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 VCO Sub-Bands Frequency Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Data validity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Start and Stop condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Byte format and acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Data and clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Start and stop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 SPI input and output bit order . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 SPI Timing specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Differential/single ended output network in the 3.0 - 4.65GHz range . . . . . . . . . . . . . . . . . 35 LC lumped balun and matching network (MATCH_LC_LUMP_4G.dsn) . . . . . . . . . . . . . . 36 Evaluation Board (EVB4G) matching network (MATCH_EVB4G.dsn) . . . . . . . . . . . . . . . . 36 Differential/single ended output network in the 1.5 - 2.325GHz range . . . . . . . . . . . . . . . . 37 LC lumped balun for divided by 2 output (MATCH_LC_LUMP_2G.dsn) . . . . . . . . . . . . . . 37 Evaluation Board (EVB2G) matching network (MATCH_EVB2G.dsn) . . . . . . . . . . . . . . . 38 LC lumped balun for the divided by 4 output (MATCH_LC_LUMP_1G.dsn) . . . . . . . . . . . 38 Evaluation Board (EVB1G) matching network (MATCH_EVB1G.dsn) . . . . . . . . . . . . . . . 39 Application diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 VFQFPN28 Mechanical Data & Package Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 5/43 Block diagram and pin configuration STW81102 1 1.1 Figure 1. Block diagram and pin configuration Block diagram Block diagram OUTBUFP OUTBUFN REF_CLK VDD_PLL VSS_PLL REXT VDD_OUTBUF VSS_OUTBUF BUF VDD_DIV4 VSS_DIV4 VCO BUF DIV4 BUF DIV2 BUF VSS_CP VDD_DIV2 VSS_DIV2 REF Divider P F D VCO Divider UP DN DIV4 DIV2 VDD_CP VDD_BUFVCO VSS_BUFVCO C P ICP BUF EXTVCO_INP EXTVCO_INN EXT VCO BUF LOCK_DET DBUS_SEL SCL / CLK SDA / DATA ADD0 / LOAD ADD1 ADD2 DBUS VCO BUFF VDD_VCOA VSS_VCOA VDD_VCOB VSS_VCOB VDD_ESD VSS_ESD VCO Calibrator VDD_DBUS VSS_DBUS EXT_PD TEST1 TEST2 VCTRL 6/43 STW81102 Block diagram and pin configuration 1.2 Pin configuration Figure 2. Pin connection (top view) ADD0/LOAD SDA/DATA VDD_DBUS DBUS_SEL VDD_BUFVCO EXTVCO_INP EXTVCO_INN SCL/CLK VDD_VCOA VDD_DIV2 VDD_OUTBUF OUTBUFP OUTBUFN VDD_DIV4 VDD_VCOB VDD_ESD VFQFPN28 EXT_PD ADD2 ADD1 VDD_PLL REF_CLK TEST2 LOCK_DET VDD_CP VCTRL Table 1. Pin No 1 2 3 4 5 6 7 8 9 10 11 12 13 14 Pin description Name VDD_VCOA VDD_DIV2 VDD_OUTBUF OUTBUFP OUTBUFN VDD_DIV4 VDD_VCOB VDD_ESD VCTRL ICP REXT VDD_CP TEST1 LOCK_DET Description VCOA power supply Divider by 2 power supply Output buffer power supply LO buffer positive output LO buffer negative output Divider by 4 power supply VCOB power supply ESD positive rail power supply VCO control voltage PLL charge pump output External resistance connection for PLL charge pump Power supply for charge pump Test input 1 Lock detector Test purpose only; must be connected to GND CMOS Output Open collector Open collector Observation TEST1 REXT ICP 7/43 Block diagram and pin configuration Table 1. Pin No 15 16 17 18 19 20 21 22 23 24 25 26 27 28 TEST2 REF_CLK VDD_PLL EXTVCO_INN EXTVCO_INP VDD_BUFVCO DBUS_SEL VDD_DBUS EXT_PD SDA/DATA SCL/CLK ADD0/LOAD ADD1 ADD2 STW81102 Pin description (continued) Name Test input 2 Reference clock input PLL digital power supply External VCO negative input External VCO positive input VCO buffer power supply Digital Bus Interface select SPI and I 2C Description Observation Test purpose only; must be connected to GND Test purpose only; must be connected to GND Test purpose only; must be connected to GND CMOS Input bus power supply CMOS Input CMOS Bidir Schmitt triggered CMOS Input CMOS Input CMOS Input CMOS Input Power down hardware I2CBUS/SPI data line I2CBUS/SPI clock line I2CBUS address select pin/ SPI load line I2CBUS address select pin I2CBUS address select pin 8/43 STW81102 Electrical specifications 2 2.1 Table 2. Symbol AVCC DVCC Tstg Electrical specifications Absolute maximum ratings Absolute maximum ratings Parameter Analog Supply voltage Digital Supply voltage Storage temperature Electrical Static Discharge - HBM(1) - CDM-JEDEC Standard - MM Values 0 to 4.6 0 to 4.6 -65 to 150 4 1.5 0.2 Unit V V °C ESD KV 1. The maximum rating of the ESD protection circuitry on pin 4 and pin 5 is 800V. 2.2 Table 3. Symbol AVDD DVDD IVDD1 IVDD2 Tamb Tj Rth j-amb Operating conditions Operating conditions (Refer to application diagram) Parameter Analog Supply voltage Digital Supply voltage VDD1 Current Consumption VDD2 Current Consumption Operating ambient temperature Maximum junction temperature Junction to ambient package thermal resistance Multilayer JEDEC board 35 -40 Test conditions Min 3.0 3.0 Typ 3.3 3.3 Max 3.6 3.6 100 15 85 125 Unit V V mA mA °C °C °C/W 2.3 Table 4. Symbol Vil Vih Vhyst Vol Voh Digital logic levels Digital logic levels Parameter Low level input voltage High level input voltage Schmitt trigger hysteresis Low level output voltage High level output voltage 0.85*Vdd 0.8*Vdd 0.8 0.4 Test conditions Min Typ Max 0.2*Vdd Unit V V V V V 9/43 Electrical specifications STW81102 2.4 Table 5. Symbol Electrical characteristics Electrical characteristics All the Electrical Specifications are intended at 3.3V supply Voltage. Parameter Test conditions Min Typ Max Unit OUTPUT FREQUENCY RANGE Direct Output Output Frequency Range with Divider by 2 VCOA Divider by 4 Direct Output Output Frequency Range with Divider by 2 VCOB Divider by 4 3000 1500 750 4000 2000 1000 3620 1810 905 4650 2325 1162.5 MHz MHz MHz MHz MHz MHz FOUTA FOUTB VCO DIVIDERS N VCO Divider Ratio Prescaler 16/17 Prescaler 19/20 256 361 65551 77836 REFERENCE CLOCK and PHASE FREQUENCY DETECTOR fref R fPFD Reference input frequency Reference input sensitivity Reference Divider Ratio PFD input frequency Prescaler 16/17 fstep Frequency step(2) Prescaler 19/20 CHARGE PUMP ICP VOCP ICP sink/source(3) Output voltage compliance range Direct Output (fPFD = 200KHz) Spurious(4) Divider by 2 (fPFD = 400KHz) Divider by 4 (fPFD = 800KHz) VCOs Lower frequency range KVCOA VCOA sensitivity(5) Intermediate frequency range Higher frequency range Lower frequency range KVCOB VCOB sensitivity(5) Intermediate frequency range Higher frequency range 40 60 80 30 40 50 55 75 105 45 55 70 70 95 140 60 70 90 MHz/V MHz/V MHz/V MHz/V MHz/V MHz/V 3bit programmable 0.4 -73 -83 -91 5 Vdd-0.3 mA V dBc dBc dBc FOUT/ 65551 FOUT/ 77836 (1) 10 0.35 2 1 200 1.5 1023 16 FOUT/ 256 FOUT/ 361 MHz Vpeak MHz Hz Hz 10/43 STW81102 Table 5. Symbol Electrical specifications Electrical characteristics (continued) All the Electrical Specifications are intended at 3.3V supply Voltage. Parameter VCO A Pushing(5) VCO B Pushing (5) Test conditions Min Typ 4 14 Max 7 20 3 -20 Unit MHz/V MHz/V V dBc mA mA mA mA mA mA mA VCTRL VCO control voltage(5) LO Harmonic Spurious (5) 0.4 IVCOA IVCOB IVCOBUF IDIV2 IDIV4 VCOA current consumption fVCO=3.3GHz ; amplitude [11] fVCO=3.3GHz ; amplitude [00] fVCO=4.3GHz ; amplitude [11] fVCO=4.3GHz ; amplitude [00] 30 16 22 11 15 17 13 VCOB current consumption VCO buffer consumption DIVIDER by 2 consumption DIVIDER by 4 consumption LO OUTPUT BUFFER PLO RL IOUTBUF Output level Return Loss(5) Matched to 50ohm DIV4 Buff Current Consumption DIV2 Buff Direct Output EXTERNAL VCO (Test purpose only) Frequency range Input level Current Consumption PLL MISCELLANEOUS IPLL Tlock Current Consumption Lock up time (5), (6) Input Buffer, Prescaler, Digital Dividers, misc. 25KHz PLL bandwidth; within 1 ppm of frequency error 12 150 mA µs VCO Internal Buffer 3.0 0 15 4.65 +6 GHz dBm mA 0 15 27 23 39 dBm dB mA mA mA 1. In order to achieve best phase noise performance 1V peak level is suggested. 2. The frequency step is related to the PFD input frequency as follows: - fstep = fPFD for Direct Output - fstep = fPFD/2 for Divided by 2 Output - fstep = fPFD/4 for Divided by 4 Output 3. see relationship between ICP and REXT in the Circuit Description section (Charge Pump) 4. The level of the spurs may change depending on PFD frequency, Charge Pump current, selected channel and PLL loop BW. 5. Guaranteed by design and characterization. 6. Frequency jump from 2300 to 2150 MHz; it includes the time required by the VCO calibration procedure (7 fPFD cycles with fPFD=400KHz). 11/43 Electrical specifications STW81102 2.5 Table 6. Phase noise specification Phase noise specification Parameter Test conditions Min Typ Max Unit PHASE NOISE PERFORMANCE(1) In Band Phase Noise Floor – Closed Loop(2) Normalized In Band Phase Noise Floor In Band Phase Noise Floor Direct Output In Band Phase Noise Floor Divider by 2 In Band Phase Noise Floor Divider by 4 PLL Integrated Phase Noise – Direct Output Integrated Phase Noise 100Hz to 40MHz FOUT = 4.3 GHz, fPFD = 200KHz, fSTEP =200 KHz, PLL BW = 15KHz, ICP=4mA -35 1.4 dBc ° rms ICP=4mA, PLL BW = 50KHz; including reference clock contribution ICP=4mA, PLL BW = 50KHz; including reference clock contribution -222 dBc/Hz -222+20log(N)+10log(fPFD) dBc/Hz dBc/Hz dBc/Hz -228+20log(N)+10log(fPFD) -234+20log(N)+10log(fPFD) PLL Integrated Phase Noise – Divider by 2 Integrated Phase Noise 100Hz to 40MHz FOUT = 2.15 GHz, fPFD = 400KHz, fSTEP =200 KHz, PLL BW = 20KHz, ICP=3mA -44 0.52 dBc ° rms PLL Integrated Phase Noise – Divider by 4 Integrated Phase Noise 100Hz to 40MHz FOUT = 1.075 GHz, fPFD = 800KHz, fSTEP =200 KHz, PLL BW = 30KHz, ICP=2.5mA -51 0.22 dBc ° rms VCO A Direct (3000MHz-3620MHz) – Open Loop(3) Phase Noise @ 1 KHz Phase Noise @ 10 KHz Phase Noise @ 100 KHz Phase Noise @ 1 MHz Phase Noise @ 10 MHz Phase Noise @ 40 MHz VCO B Direct (4000MHz-4650MHz) – Open Loop Phase Noise @ 1 KHz Phase Noise @ 10 KHz Phase Noise @ 100 KHz Phase Noise @ 1 MHz Phase Noise @ 10 MHz Phase Noise @ 40 MHz (3) -56 -83 -107 -129 -149 -159 dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz -54 -82 -106 -128 -148 -158 dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz 12/43 STW81102 Table 6. Phase noise specification (continued) Parameter Test conditions Min Electrical specifications Typ Max Unit VCO A with divider by 2 (1500MHz-1810MHz) – Open Loop(3) Phase Noise @ 1 KHz Phase Noise @ 10 KHz Phase Noise @ 100 KHz Phase Noise @ 1 MHz Phase Noise @ 10 MHz Phase Noise Floor @ 40 MHz VCO B with divider by 2 (2000MHz-2325MHz) – Open Loop Phase Noise @ 1 KHz Phase Noise @ 10 KHz Phase Noise @ 100 KHz Phase Noise @ 1 MHz Phase Noise @ 10 MHz Phase Noise Floor @ 40 MHz VCO A with divider by 4 (750MHz-905MHz) – Open Loop(3) Phase Noise @ 1 KHz Phase Noise @ 10 KHz Phase Noise @ 100 KHz Phase Noise @ 1 MHz Phase Noise @ 10 MHz Phase Noise Floor @ 40 MHz VCO B with divider by 4 (1000MHz-1162.5MHz) – Open Loop Phase Noise @ 1 KHz Phase Noise @ 10 KHz Phase Noise @ 100 KHz Phase Noise @ 1 MHz Phase Noise @ 10 MHz (3) (3) -62 -89 -113 -135 -151.5 -155 dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz -60 -88 -112 -134 -151.5 -155 dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz -68 -95 -119 -141 -154 -155 dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz -66 -94 -118 -140 -154 -155 dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz Phase Noise Floor @ 40 MHz 1. Phase Noise SSB. VCO amplitude setting to value [11]. All the closed-loop performances are specified using a Reference Clock signal at 76.8 MHz with phase noise of -135dBc/Hz @1KHz offset, -145dBc/Hz @10KHz offset and -149.5dBc/Hz of noise floor. 2. Normalized PN = Measured PN – 20log(N) – 10log(fPFD) where N is the VCO divider ratio (N=B*P+A) and fPFD is the comparison frequency at the PFD input 3. Typical Phase Noise at centre band frequency Upon request an Evaluation Kit is available including a powerful simulation tool (STWPLLSim) which allows to estimate very accurately the Phase Noise of the device according to the desired project parameters (VCO Frequency, Selected Output Stage, Reference Clock, Frequency Step, …); refer to the Application Information (Section 7) for more details. 13/43 Typical performance characteristics STW81102 3 Typical performance characteristics The phase noise is measured with the Agilent E5052A Signal Source Analyzer. All the closed-loop measurements are done with fSTEP=200 KHz setting properly the fPFD and the Charge Pump current. The loop filter configuration used is depicted in the paragraph 8 (Application Diagram) and the Reference Clock signal is at 76.8 MHz with phase noise of 135dBc/Hz @1KHz offset, -145dBc/Hz @10KHz offset and -149.5dBc/Hz of noise floor. Figure 3. VCO A (Direct output) open loop phase noise Figure 4. VCO B (Direct output) open loop phase noise Figure 5. VCO A (Direct output) closed loop phase noise at 3.6GHz (FSTEP=200KHz; FPFD=200KHz; ICP=3mA) Figure 6. VCO B (Direct output) closed loop phase noise at 4.3GHz (FSTEP=200KHz; FPFD=200KHz; ICP=4mA) 1. 2 ° r m s 1.4° rms 14/43 STW81102 Figure 7. VCO A (Div. by 2 output) closed loop phase noise at 1.65GHz (FSTEP=200KHz; FPFD=400KHz; ICP=2mA) Figure 8. Typical performance characteristics VCO B (Div. by 2 output) closed loop phase noise at 2.15GHz (FSTEP=200KHz; FPFD=400KHz; ICP=3mA) 0 . 5 ° rm s 0.57° rms Figure 9. VCO A (Div. by 4 output) closed loop phase noise at 825MHz (FSTEP=200KHz; FPFD=800KHz; ICP=1.5mA) Figure 10. VCO B (Div. by 4 output) closed loop phase noise at 1.075GHz (FSTEP=200KHz; FPFD=800KHz; ICP=2.5mA) 0 .2° rm s 0 .24° rm s 15/43 Typical performance characteristics Figure 11. PFD Frequency Spurs (Direct Output; FPFD=200KHz) Figure 12. STW81102 PFD Frequency Spurs (Div. by 2 Output; FPFD=400KHz) -73 dBc @200KHz -83 dBc @400KHz Figure 13. PFD Frequency Spurs (Div. by 4 Output; FPFD=800KHz) Figure 14. Settling Time (Final Frequency=2.15 GHz; FPFD=400KHz; ICP=3mA) -91 dBc @800KHz 16/43 STW81102 General description 4 General description The block diagram of Figure 1 shows the different blocks, which have been integrated to achieve an integer-N PLL frequency synthesizer. The STW81102 consists of 2 internal low-noise VCOs with buffer blocks, a divider by 2, a divider by 4, a low-noise PFD (Phase Frequency Detector), a precise charge pump, a 10-bit programmable reference divider, two programmable counters and a programmable dualmodulus prescaler. The A-counter (5 bits) and B counter (12 bits) counters, in conjunction with the dual modulus prescaler P/P+1 (16/17 or 19/20), implement an N integer divider, where N = B*P +A. The division ratio of both reference and VCO dividers is controlled through the selected digital interface (I2C bus or SPI). The selection of the digital interface type is done by the proper hardware connection of the pin DBUS_SEL (0 V for I2C bus, 3.3 V for SPI). All devices operate with a power supply of 3.3 V and can be powered down when not in use. 4.1 4.1.1 Circuit description Reference input stage The reference input stage is shown in Figure 15. The resistor network feeds a DC bias at the Fref input while the inverter used as the frequency reference buffer is AC coupled. Figure 15. Reference Frequency Input Buffer VDD Fref INV BUF Power Down 4.1.2 Reference divider The 10-bit programmable reference counter allows the input reference frequency to be divided to produce the input clock to the PFD. The division ratio is programmed through the digital interface. 4.1.3 Prescaler The dual-modulus prescaler P/P+1 takes the CML clock from the VCO buffer and divides it down to a manageable frequency for the CMOS A and B counters. The modulus (P) is programmable and can be set to 16 or 19. It is based on a synchronous 4/5 core which division ratio depends on the state of the modulus input. 17/43 General description STW81102 4.1.4 A and B counters The A (5 bits) and B (12 bits) counters, in conjunction with the selected dual modulus (16/17 or 19/20) prescaler make it possible to generate output frequencies which are spaced only by the reference frequency divided by the reference division ratio. Thus, the division ratio and the VCO output frequency are given by these formulas: N=B·P+A ( B ⋅ P + A ) ⋅ F ref F vco = -----------------------------------------R where: Fvco: output frequency of VCO. P: modulus of dual modulus prescaler (16 or 19 selected through the digital interface). B: division ratio of the main counter. A: division ratio of the swallow counter. Fref: input reference frequency. R: division ratio of reference counter. N: division ratio of PLL For a correct work of the VCO divider, B must be strictly higher than A. A can take any value ranging from 0 to 31. The range of the N number can vary from 256 to 65551 (P=16) or from 361 to 77836 (P=19). Figure 16. VCO Divider Diagram VCOBUF- Prescaler 16/17 or 19/20 VCOBUF+ modulus To PFD 5 bit A counter 12 bit B counter 4.1.5 Phase frequency detector (PFD) The PFD takes inputs from the reference and the VCO dividers and produces an output proportional to the phase error. The PFD includes a delay gate that controls the width of the anti-backlash pulse. This pulse ensures that there is no dead zone in the PFD transfer function. Figure 17 is a simplified schematic of the PFD. 18/43 STW81102 Figure 17. PFD diagram VDD General description D FF Fref Up R Delay R D FF Down ABL Fref VDD 4.1.6 Lock detect This signal indicates that the difference between rising edges of both UP and DOWN PFD signals is found to be shorter than the fixed delay (roughly 5 ns). Lock Detect signal is high when the PLL is locked. When Power Down is activated, Lock Detect is let to high level (Lock Detect consumes current only during PLL transients). 4.1.7 Charge pump This block drives two matched current sources, Iup and Idown, which are controlled respectively by UP and DOWN PFD outputs. The nominal value of the output current is controlled by an external resistor (to be connected to the REXT input pin) and a selection among 8 by a 3 bit word. The minimum value of the output current is: IMIN = 2*VBG/REXT (VBG~1.17 V) Table 7. CPSEL2 0 0 0 0 1 1 1 1 Current value vs selection CPSEL1 0 0 1 1 0 0 1 1 CPSEL0 0 1 0 1 0 1 0 1 Current IMIN 2*IMIN 3*IMIN 4*IMIN 5*IMIN 6*IMIN 7*IMIN 8*IMIN Value for REXT=4.7 KΩ 0.5 mA 1.0 mA 1.5 mA 2.0 mA 2.5 mA 3.0 mA 3.5 mA 4.0 mA Note: The current is output on pin ICP. During the VCO auto calibration, ICP and VCTRL pins are forced to VDD/2 19/43 General description Figure 18. Loop filter connection VDD VCTRL STW81102 BUF Charge Pump ICP C3 R3 R1 C1 BUF Cal bit C2 4.1.8 Voltage controlled oscillators VCO Selection Within STW81102 two low-noise VCOs are integrated to cover a wide band from 3000MHz to 3620MHz and 4000MHz to 4650MHz (direct output), from 1500MHz to 1810MHz and 2000MHz to 2325MHz (selecting divider by 2), from 750MHz to 905MHz and 1000MHz to 1162.5MHz (selecting divider by 4). VCO A frequency range 3000MHz-3620MHz VCO B frequency range 4000MHz-4650MHz VCO Frequency Calibration Both VCOs can operate on 32 frequency ranges that are selected by adding or subtracting capacitors to the resonator. These frequency ranges are intended to cover the wide band of operation and compensate for process variation on the VCO center frequency. An automatic selection of the range is performed when the bit SERCAL rises from "0" to "1". The charge pump is inhibited and the pins ICP & VCTRL are at VDD/2 volts. Then the ranges are tested to select the one which with this VCO input voltage is the nearest to the desired output frequency (Fout = N*Fref/R). When this selection is achieved the signal ENDCALB (which means End of Calibration) falls to "0", then the charge pump is enabled again and SERCAL should be reset to "0" before the next channel step. The PLL has just to perform fine adjustment around VDD/2 on the loop filter to reach Fout, which enables a fast settle. Figure 19. VCO Sub-Bands Frequency Characteristics 20/43 STW81102 General description The SERCAL bit should be set to "1" at each division ratio change. It should be noted that in order to reset the autocalibrator State Machine after a power-up, and anyway before the first calibration, the INITCAL bit should be set to "1" and back to "0" (this operation is automatically performed by the Power On Reset circuitry). The calibration takes approximately 7 periods of the PFD Frequency. The maximum allowed fPFD to perform the calibration process is 1 MHz. Using an higher FPFD the following procedure should be adopted: 1. 2. Calibrate the VCO at the desired frequency with an fPFD less than 1 MHz Set the A, B and R dividers ratio for the desired fPFD VCO Voltage Amplitude Control The voltage swing of the VCOs can be adjusted over 4 levels by means of two dedicated programming bits (PLL_A1 and PLL_A0). Higher amplitudes provide best phase noise while lower ones save power. The following table gives the voltage level expected on the resonator nodes, the current consumption and the phase noise @1MHz. Table 8. VCO A performances vs. amplitude setting (Freq=3.3GHz) Differential voltage swing (Vp) 1.1 1.3 1.9 2.1 Current Consumption (mA) 16 18 27 30 PN @1MHz (dBc/Hz) -125 -126 -128.5 -129 PLL_A[1:0] 00 01 10 11 Table 9. VCO B performances vs. amplitude setting (Freq=4.3GHz) Differential voltage swing (Vp) 1.1 1.3 1.9 2.1 Current Consumption (mA) 11 14 20 22 PN @1MHz (dBc/Hz) -124 -125 -127.5 -128 PLL_A[1:0] 00 01 10 11 21/43 I2C bus interface STW81102 5 I2C bus interface The I2C bus interface is selected by hardware connection of the pin #21 (DBUS_SEL) to 0 V. Data transmission from microprocessor to the STW81102 takes place through the 2 wires (SDA and SCL) I2C-BUS interface. The STW81102 is always a slave device. The I2C-bus protocol defines any device that sends data on to the bus as a transmitter and any device that reads the data as receiver. The device that controls the data transfer is known as the Master and the others as the slave. The master will always initiate the transfer and will provide the serial clock for synchronization. 5.1 5.1.1 General features Data validity Data changes on the SDA line must only occur when the SCL is LOW. SDA transitions while the clock is HIGH are used to identify START or STOP condition. Figure 20. Data validity SDA SCL DATA LINE STABLE DATA VALID CHANGE DATA ALLOWED 5.1.2 START condition A Start condition is identified by a HIGH to LOW transition of the data bus SDA while the clock signal SCL is stable in the HIGH state. A Start condition must precede any command for data transfer. 5.1.3 STOP condition A LOW to HIGH transition of the data bus SDA identifies stop while the clock signal SCL is stable in the HIGH state. A STOP condition terminates communications between the STW81102 and the Bus Master. 22/43 STW81102 Figure 21. Start and Stop condition I2C bus interface SCL SDA START STOP 5.1.4 Byte format and acknowledge Every byte transferred on the SDA line must contain bits. Each byte must be followed by an acknowledge bit. The MSB is transferred first. An acknowledge bit is used to indicate a successful data transfer. The bus transmitter, either master or slave, will release the SDA bus after sending 8 bits of data. During the 9th clock pulse the receiver pulls the SDA low to acknowledge the receipt of 8 bits data. Figure 22. Byte format and acknowledge SCL 1 2 3 // 7 8 9 SDA START MSB // ACKNOWLEDGMENT FROM RECEIVER 5.1.5 Device addressing To start the communication between the Master and the STW81102, the master must initiate with a start condition. Following this, the master sends onto the SDA line 8 bits (MSB first) corresponding to the device select address and read or write mode. The first 7 MSB's are the device address identifier, corresponding to the I2C-Bus definition. For the STW81102 the address is set as "1100A2A1A0", 3bits programmable. The 8th bit (LSB) is the read or write operation bit (RW; set to 1 in read mode and to 0 in write mode). After a START condition the STW81102 identifies on the bus the device address and, if matched, it will acknowledge the identification on SDA bus during the 9th clock pulse. 5.1.6 Single-byte write mode Following a START condition the master sends a device select code with the RW bit set to 0. The STW81102 gives an acknowledge and waits for the internal sub-address (1 byte). This byte provides access to any of the internal registers. After the reception of the sub-address internal byte the STW81102 again responds with an acknowledge. A single-byte write to sub-address 00H will change the "FUNCTIONAL_MODE" register, so a single-byte write with sub-address 04H will change the "CONTROL" register and so on. 23/43 I2C bus interface Table 10. S STW81102 Single-byte write mode 0 ack sub-address byte ack DATA IN ack P 1100A2A1A0 5.1.7 Multi-byte write mode The multi-byte write mode can start from any internal address. The master sends the data bytes and each one is acknowledged. The master terminates the transfer by generating a STOP condition. The sub-address decides the starting byte. A multi-byte with sub-address 01H and 2 DATA_IN bytes will change the "B_COUNTER" and "A_COUNTER" registers (01H,02H), so a multi-byte with sub-address 00H and and 6 DATA_IN bytes will change all the STW81102 registers. Table 11. S Multi-byte write mode 0 ack sub-address byte ack DATA IN ack .... DATA IN ack P 1100A2A1A0 5.1.8 Current byte address read In the current byte address read mode, following a START condition, the master sends the device address with the rw bit set to 1 (No sub-address is needed as there is only 1 byte read register). The STW81102 acknowledges this and outputs the data byte. The master does not acknowledge the received byte, but terminates the transfer with a STOP condition. Table 12. S Current Byte Address Read 1100 A2 A1 A0 1 ack DATA OUT No ack P 5.2 Timing specification Figure 23. Data and clock SDA SCL tcwl tcs tch tcwh Table 13. Data and clock Parameter Data to clock set up time Data to clock hold time Clock pulse width high Clock pulse width low Minimum time (ns) 2 2 10 5 Tcs Tch Symbol Tcwh Tcwl 24/43 STW81102 Figure 24. Start and stop I2C bus interface Table 14. Start and stop Parameter Clock to data start time Data to clock down stop time Minimum time (ns) 2 2 Symbol Tstart Tstop Figure 25. Acknowledge SDA SCL 8 9 td1 td2 Table 15. Acknowledge Parameter Ack begin delay Ack end delay Minimum time (ns) 2 2 Td1 Td2 Symbol 25/43 I2C bus interface STW81102 5.3 I2C registers STW81102 has 6 write-only registers and 1 read-only register. The following table gives a short description of the write-only registers list. Table 16. Write-only registers list DEC CODE 0 1 2 3 4 5 DESCRIPTION FUNCTIONAL_MODE B_COUNTER A_COUNTER REF_DIVIDER CONTROL CALIBRATION HEX CODE 0x00 0x01 0x02 0x03 0x04 0x05 5.3.1 FUNCTIONAL_MODE MSB b7 PD6 b6 PD5 b5 PD4 b4 PD3 b3 PD2 b2 PD1 b1 PD0 LSB b0 B11 FUNCTIONAL_MODE register is used to select different functional mode for the STW81102 synthesizer according to the following table: Table 17. Different functional mode of the FUNCTIONAL_MODE register Description Power down mode Enable VCO A, output frequency divided by 2 Enable VCO B, output frequency divided by 2 Enable external VCO, output frequency divided by 2 Enable VCO A, output frequency divided by 4 Enable VCO B, output frequency divided by 4 Enable external VCO, output frequency divided by 4 Enable VCO A, direct output Enable VCO B, direct output Enable external VCO, direct output Decimal value 0 1 2 3 4 5 6 7 8 9 26/43 STW81102 I2C bus interface 5.3.2 B_COUNTER MSB b7 B10 b6 B9 b5 B8 b4 B7 b3 B6 b2 B5 b1 B4 LSB b0 B3 B[10:3]. Counter value (bit B11 in the previous register, bits B[2:0] in the next register) 5.3.3 A_COUNTER MSB b7 B2 b6 B1 b5 B0 b4 A4 b3 A3 b2 A2 b1 A1 LSB b0 A0 Bits B[2:0] for B Counter, A Counter value. 5.3.4 REF_DIVIDER MSB b7 R9 b6 R8 b5 R7 b4 R6 b3 R5 b2 R4 b1 R3 LSB b0 R2 Reference Clock divider ratio R[9:1] (bits R1, R0 in the next register). 5.3.5 CONTROL MSB b7 R1 b6 R0 b5 PLL_ A1 b4 PLL_ A0 b3 CP SEL2 b2 CP SEL1 b1 CP SEL0 LSB b0 PSC_ SEL The CONTROL register is used to set the Charge Pump current, the VCO output voltage amplitude and the Prescaler Modulus. PLL_A[1:0]: VCO amplitude CPSEL[2:0]: Charge Pump output current PSC_SEL: Prescaler Modulus select ('0' for P=16, '1' for P=19) The LO output frequency is programmed by setting the proper value for A,B and R according to the following formula: F REF_CLK F OUT = D R ⋅ ( B ⋅ P + A ) ⋅ --------------------------R 27/43 I2C bus interface STW81102 where DR equals { 1 0.5 0.25 for Direct Output for Output Divided by 2 for Output Divided by 4 and P is the selected Prescaler Modulus 5.3.6 CALIBRATION MSB b7 INIT CAL b6 SER CAL b5 SEL EXT CAL b4 CAL4 b3 CAL3 b2 CAL2 b1 CAL1 LSB b0 CAL0 This register controls VCO calibrator. INITCAL: SERCAL: resets the auto-calibrator State Machine (writing to "1" and back to "0") at "1" starts the VCO auto-calibration (should be reset to "0" at the end of calibration) test purpose only; must be set to '0' SELEXTCAL: test purpose only; must be set to '0' CAL[4:0]: 5.3.7 READ-ONLY register MSB b7 DEV_ID1 b6 DEV_ID0 b5 LOCK_ DET b4 INT CAL4 b3 INT CAL3 b2 INT CAL2 b1 INT CAL1 LSB b0 INT CAL0 This register is automatically addressed in the 'current byte address read mode'. DEV_ID[1:0]: device identifier bits; returns '00' LOCK_DET: INTCAL[4:0]: "1" when PLL is locked internal value of the VCO control word 5.3.8 Default configuration At Power On Reset the following configuration is automatically loaded: – – – – – – – FUNCTIONAL MODE = 1 (VCOA with divided by 2 output) A COUNTER = 8 B COUNTER = 562 R DIVIDER = 192 PLL_A[1:0] = [10] CP_SEL[2:0] = [111] PSC_MOD_SEL set to "0" (Modulus = 16) This is corresponding to an output frequency of 1800MHz and a PFD frequency of 400KHz using a 76.8MHz reference clock (calibration algorithm of the VCO is automatically started). 28/43 STW81102 I2C bus interface 5.4 VCO calibration procedure The calibration of the VCO center frequency is activated by a '0' to '1' transition of the SERCAL bit (CALIBRATION Register bit[6]). In order to program properly the device, ensuring the VCO calibration, the following procedure is required before every channel change: a) b) Reset the "CALIBRATION" Register using a single-byte write sequence (subaddress 05H) with all the bits set to '0' Program all the Registers using a multi-byte write sequence with the desired settings (Functional Mode, B and A counters, R counter, VCO amplitude, Charge Pump, Prescaler Modulus) and the SERCAL bit of the "CALIBRATION" Register (05H) set to '1' The maximum allowed PFD frequency (fPFD) to perform the calibration process is 1 MHz; if the desired fPFD is higher than 1MHz the following steps are needed: – – Perform all the steps of the calibration procedure programming the desired VCO frequency with a proper setting of R, B and A counter so that fPFD is ≤ 1MHz. Program the device with the proper setting for the desired VCO and PFD frequencies according to the above step b) only. 29/43 SPI digital interface STW81102 6 6.1 SPI digital interface General features The SPI digital interface is selected by hardware connection of the pin #21 (DBUS_SEL) to 3.3V. The STW81102 IC is programmed by means of a high-speed serial-to-parallel interface with write option only. The 3-wires bus can be clocked at a frequency as high as 100MHz to allow fast programming of the registers containing the data for RF IC configuration. The programming of the chip is done through serial words with whole length of 26 bits. The first 2 MSB represent the address of the registers. The others 24 LSB represent the value of the registers. Each Data bit is stored in the internal shift register on the rising edge of the CLOCK signal. On the rising edge of the LOAD signal the outputs of the selected register are sent to the device. Figure 26. SPI input and output bit order 30/43 STW81102 Table 18. MSB Address Data for Register (24 bits) SPI digital interface SPI data structure LSB A1 A0 D23 D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Table 19. Address decoder and outputs Outputs A0 DATABITS D23-D0 24 24 24 24 No Name Function Reference divider, VCO amplitude, VCO Calibration, Charge Pump current, Prescaler Modulus Functional modes, VCO dividers Reserved Reserved Address A1 0 0 1 1 0 1 0 1 0 1 2 3 ST1 ST2 ST3 ST4 6.2 Timing specification Figure 27. SPI Timing specification Table 20. Parameter tsetup thold tclk tload tclk_loadr tclk_loadf SPI Timing specification Description DATA to CLOCK setup time DATA to clock hold time CLOCK cycle period LOAD pulse width CLOCK to LOAD rising edge CLOCK to LOAD falling edge Min. 0.8 0.2 10 3 2 0.5 Typ. Max. Unit ns ns ns ns ns ns 31/43 SPI digital interface STW81102 6.3 Bits table Table 21. Bit [23] [22] [21] [20] [19] [18] [17] [16] [15] [14] [13] [12] [11] [10] [9] [8] [7] [6] [5] [4] [3] [2] [1] [0] Bits (Serial Interface Address = 00h; Register name = ST1) Name R9 R8 R7 R6 R5 REFERENCE CLOCK DIVIDER RATIO R4 R3 R2 R1 R0 PLL_A1 VCO Amplitude Control PLL_A0 CPSEL2 CPSEL1 CPSEL0 PSC_SEL INITCAL SERCAL SELEXTCAL CAL4 CAL3 CAL2 CAL1 CAL0 test purpose only; must be set to ‘0’ Prescaler Modulus select (‘0’ for P=16, ‘1’ for P=19) test purpose only; must be set to ‘0’ Enable VCO calibration (see Section 6.4) test purpose only; must be set to ‘0’ Charge Pump output current Control Description 32/43 STW81102 Table 22. Bit [23] [22] [21] [20] [19] [18] SPI digital interface Bits (Serial Interface Address = 01h; Register name = ST2) Name PD6 PD5 PD4 PD3 PD2 PD1 Description DEVICE FUNCTIONAL MODES 0. Power down 1. Enable VCO A, output frequency divided by 2 2. Enable VCO B, output frequency divided by 2 3. Enable external VCO, output frequency divided by 2 4. Enable VCO A, output frequency divided by 4 5. Enable VCO B, output frequency divided by 4 6. Enable external VCO, output frequency divided by 4 7. Enable VCO A, direct output 8. Enable VCO B, direct output 9. Enable external VCO, direct output [17] PD0 [16] [15] [14] [13] [12] [11] [10] [9] [8] [7] [6] [5] [4] [3] [2] [1] [0] B11 B10 B9 B8 B7 B6 B Counter Bits B5 B4 B3 B2 B1 B0 A4 A3 A2 A1 A0 A Counter Bits The LO output frequency is programmed by setting the proper value for A,B and R according to the following formula: F REF_CLK F OUT = D R ⋅ ( B ⋅ P + A ) ⋅ --------------------------R where DR equals { 1 0.5 0.25 for Direct Output for Output Divided by 2 for Output Divided by 4 and P is the selected Prescaler Modulus 33/43 SPI digital interface STW81102 6.3.1 Default configuration At Power On Reset the following configuration is automatically loaded: – – – – – – – FUNCTIONAL MODE = 1 (VCOA with divided by 2 output) A COUNTER = 8 B COUNTER = 562 R DIVIDER = 192 PLL_A[1:0] = [10] CP_SEL[2:0] = [111] PSC_MOD_SEL set to "0" (Modulus = 16) This is corresponding to an output frequency of 1800MHz and a PFD frequency of 400KHz using a 76.8MHz reference clock (calibration algorithm of the VCO is automatically started). 6.4 VCO calibration procedure The calibration of the VCO center frequency is activated by a '0' to '1' transition of the SERCAL bit (ST1 Register bit[6]). In order to program properly the device, ensuring the VCO calibration, the following procedure is required before every channel change: a) b) c) Program the ST1 Register with the desired settings (R counter, VCO amplitude, Charge Pump, Prescaler Modulus) and SERCAL bit set to '0' Program the ST2 Register with the desired settings (Functional mode, B and A counters) Program the ST1 Register with the desired settings (R counter, VCO amplitude, Charge Pump, Prescaler Modulus) and SERCAL bit set to '1' The maximum allowed PFD frequency (fPFD) to perform the calibration process is 1 MHz; if the desired fPFD is higher than 1MHz the following steps are needed: – – Perform all the steps of the calibration procedure programming the desired VCO frequency with a proper setting of R, B and A counter so that fPFD is ≤ 1MHz. Program the device with the proper setting for the desired VCO and PFD frequencies according to the above step a) and b) only. 34/43 STW81102 Application information 7 Application information The STW81102 features three different alternatively selectable bands: direct output (3.0 to 3.62GHz and 4.0 to 4.65GHz), divided by 2 (1.5 to 1.81GHz and 2.0 to 2.325GHz) and divided by 4 (750 to 905MHz and 1000 to 1162.5MHz). In order to achieve a suitable power level, a good matching network is needed to adapt the output stage to a 50Ω load. Moreover, since most of commercial RF components have single ended input and output terminations, a differential to single ended conversion could be required. Below different matching configurations for the three bands are suggested as a guideline for the design of own application board. The user can find in the Evaluation Kit the ADS Design for each matching configuration suggested in this section. The name of the corresponding ADS Design is reported in each figure. The ADS designs provide only a first indication of the output stage matching and they should be reworked according to the user choice for layout, board substrate, components and so on. The ADS designs of the Evaluation Boards are provided with a complete electromagnetic modelling (board, components, ...). 7.1 Direct Output If a differential to single conversion is not needed it is possible to match the output buffer of the STW81102 in the simple way shown in Figure 28. Figure 28. Differential/single ended output network in the 3.0 - 4.65GHz range (MATCH_LC_LUMP_4G_DIFF.dsn) V CC 100 Ohm 5.5nH 50 Ohm 10pF RFOUTP RF OUTN 100 Ohm 10pF 50 Ohm 5.5nH V CC Since most of discrete components for microwave applications are single ended, the user can easily use one of the two outputs and terminate the other one to 50Ω with a 3dB power loss. 35/43 Application information STW81102 Alternatively it is possible to combine the 2 outputs in different ways. A first topology for the direct output (3GHz to 4.65GHz) is suggested in Figure 29. It basically consists of a simple LC balun and a matching network to adapt the output to a 50Ω load. The two LC networks shift output signal phase of -90° and +90° thus combining the 2 outputs. This topology, designed for a center frequency of 4GHz, is intrinsically narrow band, since the LC balun is tuned at a single frequency. If the application requires a different sub-band, the LC combiner could be easily adjusted to be tuned at the frequency of interest. Figure 29. LC lumped balun and matching network (MATCH_LC_LUMP_4G.dsn) V CC 50 Ohm 1.9nH 0.8pF 1.9nH RF OUTP 0.8pF 2.5pF 1.9nH 50 Ohm RF OUTN 0.8pF 50 Ohm 1.9nH 0.8pF VCC The 1.9nH shunt inductor works as a DC feed for one of the open collector terminal as well as a matching element along with the other components. The 1.9nH series inductors are used to resonate the parasitic capacitance of the chip. For an optimum output matching it is recommended to use 0402 Murata or AVX capacitors and 0403 or 0604 HQ Coilcraft inductors. It is also advisable to use short interconnection paths to minimize losses and undesired impedance shift. An alternative topology, which allows for a more broadband matching and balanced to unbalanced conversion, is shown it Figure 30. Figure 30. Evaluation Board (EVB4G) matching network (MATCH_EVB4G.dsn) VCC 50 Ohm 5.5nH 12pF RFOUTP 2:1 12pF 1pF 12pF 4.7pF 1pF 1.2pF 1.2pF 50 Ohm RF OUTN 50 Ohm 5.5nH VCC For the differential to single conversion the 50 to 100Ω Johanson balun is recommended (3700BL15B100). 36/43 STW81102 Application information 7.2 Divided by 2 Output If the user's application does not require a balanced to unbalanced conversion, the output matching reduces to the simple circuit shown below (Figure 31). This solution can be easily used to provide one single ended output just terminating the other output at 50Ω with a 3dB power loss. Figure 31. Differential/single ended output network in the 1.5 - 2.325GHz range (MATCH_LC_LUMP_2G_DIFF.dsn) VCC 50 O hm 22nH 50 Ohm RFOUTP 10pF RFOUTN 50 O hm 10pF 50 Ohm 22nH VCC A first solution to combine the differential outputs is the lumped LC type balun tuned in the 2GHz band (Figure 32). Figure 32. LC lumped balun for divided by 2 output (MATCH_LC_LUMP_2G.dsn) V CC 50 Ohm 2.7nH 2pF 2.7nH RF OUTP 2pF 3pF 2.7nH 3nH 50 Ohm RF OUTN 2pF 50 Ohm 2.7nH 2pF VCC The same recommendation for the SMD components applies also for the divided by 2 output. Another topology suitable to combine the two outputs for the divided by 2 frequencies is represented in Figure 33. 37/43 Application information STW81102 Figure 33. Evaluation Board (EVB2G) matching network (MATCH_EVB2G.dsn) VCC 50 Ohm 5.5nH 22pF RFOUTP 2:1 22pF 22pF 1.9nH 50 Ohm 1.2pF RF OUTN 50 Ohm 5.5nH VCC For the differential to single conversion the 50 to 100Ω Johanson balun (1600BL15B100) is recommended. 7.3 Divided by 4 Output The same topology, components values and considerations of Figure 31, applies also for the divided by 4 output (MATCH_LC_LUMP_1G_DIFF.dsn). As for the previous sections, a solution to combine the differential outputs is the lumped LC type balun tuned in the 1GHz band (Figure 34). Figure 34. LC lumped balun for the divided by 4 output (MATCH_LC_LUMP_1G.dsn) VCC 25 Ohm 5.5nH 4pF 5.5nH RFOUTP 4pF 6pF 5.5nH 14nH 50 Ohm RFOUTN 4pF 25 Ohm 5.5nH 4pF VCC If the user prefers to use an RF balun it is possible to adopt the same topology depicted in Figure 33, just changing the balun and the matching components (Figure 35). The suggested balun for the 0.75 - 1.17GHz frequency range is the 1:1 Johanson 900BL15C050. 38/43 STW81102 Application information Figure 35. Evaluation Board (EVB1G) matching network (MATCH_EVB1G.dsn) VCC 25 Ohm 18nH 8.2pF RFOUTP 1:1 8.2pF 22pF 2.1nH 50 Ohm 0.5pF RF OUTN 25 Ohm 18nH VCC 7.4 Evaluation Kit Upon request an Evaluation Kit can be delivered. It includes: ● ● ● ● ● Evaluation Board GUI (Graphical User Interface) to program the device Measured S parameters of the RF output ADS2005 schematics providing guidelines for application board design STWPLLSim software for PLL loop filter design and noise simulation Three different Evaluation Kits are available, one optimized for 1GHz frequency range, one for 2GHz frequency range and the last one for 4GHz range. While ordering please specify the following order codes: Table 23. Order code of the evaluation kit Part Number STW81102-EVB1G STW81102-EVB2G STW81102-EVB4G Description 1GHz frequency range - Divider by 4 output optimized 2GHz frequency range - Divider by 2 output optimized 4GHz frequency range - Direct output optimized The three Evaluation Kits differ only for the output stage network and can be adapted from one frequency band variant to a different one replacing properly the macthing components and the balun. 39/43 Application diagram STW81102 8 Application diagram Figure 36. Application diagram From/to µ– controller 100 100 100 15p 15p 15p ADD0/LOAD SCL/CLK 1n 22p 10 µ SDA/DATA EXT_PD ADD2 ADD1 VDD1 VDD_DBUS I2C VDD_VCOA VDD_DIV2 DBUS_SEL VDD_BUFVCO SPI VDD1 VDD_OUTBUF EXTVCO_INP 1n OUTBUFP VDD2 22p 10 µ RF Out STW81102 EXTVCO_INN OUTBUFN VDD_PLL VDD_DIV4 VDD _CP REF_CLK LOCK_DET 1.8n TEST2 ref clk 51 VDD1 VDD1 1n 22p 10 µ VDD_ESD VCTRL ICP REXT 4.7K VDD1 2.2K 8.2K 68p 2.7n 1n 22p 10 µ loop filter 270p TEST1 VDD_VCOB to µ– controller Note: 1 2 3 See Application Information (Section 7) for further information on Output Matching topology. EXT_PD, ADD2, ADD1 (and ADD0 when I2C Bus is selected) can be hard wired directly on the board. Loop Filter values are for 200KHz frequency step. 40/43 STW81102 Package information 9 Package information In order to meet environmental requirements, ST offers these devices in ECOPACK® packages. These packages have a Lead-free second level interconnect. The category of second Level Interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: http://www.st.com. Figure 37. VFQFPN28 Mechanical Data & Package Dimensions REF. A A1 A2 A3 b D D1 D2 E E1 E2 e L P K ddd 0.350 2.950 2.950 4.850 0.180 4.850 mm MIN. 0.800 TYP. 0.900 0.020 0.650 0.200 0.250 5.000 4.750 3.100 5.000 4.750 3.100 0.500 0.550 0.750 0.60 14˚ 0.080 0.014 3.250 0.116 3.250 5.150 0.116 0.191 0.300 5.150 MAX. 1.000 0.050 1.000 MIN. 0.031 inch TYP. 0.035 MAX. 0.039 OUTLINE AND MECHANICAL DATA 0.0008 0.0019 0.025 0.0078 0.007 0.0098 0.012 0.191 0.197 0.187 0.122 0.197 0.187 0.122 0.020 0.022 0.029 0.0236 14˚ 0.003 0.128 0.128 0.203 0.203 0.039 Notes: 1) VFQFPN stands for Thermally Enhanced Very thin Fine pitch Quad Packages No lead. Very thin: A = 1.00 Max. 2) The pin #1 identifier must be existed on the top surface of the package by using indentation mark or other feature of package body. Exact shape and size of this feature is optional. VFQFPN-28 (5x5x1.0mm) Very Fine Quad Flat Package No lead 7655832 A 41/43 Revision history STW81102 10 Revision history Table 24. Date 06-Mar-2006 16-Jun-2006 Document revision history Revision 1 2 Initial release. Changed from preliminary data to maturity. Updated Section 2: Electrical specifications; Section 7: Application information and Section 8: Application diagram. Changes 42/43 STW81102 Please Read Carefully: Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. 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