STW8N90K5

STW8N90K5 N-channel 900 V, 0.60 Ω typ., 8 A MDmesh™ K5 Power MOSFET in a TO-247 package Datasheet - production data Features      3 2 1 TO-247 Order code VDS RDS(on) max. ID STW8N90K5 900 V 0.68 Ω 8A Industry’s lowest RDS(on) x area Industry’s best FoM (figure of merit) Ultra-low gate charge 100% avalanche tested Zener-protected Applications  Figure 1: Internal schematic diagram D(2) Switching applications Description This very high voltage N-channel Power MOSFET is designed using MDmesh™ K5 technology based on an innovative proprietary vertical structure. The result is a dramatic reduction in on-resistance and ultra-low gate charge for applications requiring superior power density and high efficiency. G(1) S(3) AM15572v1_no_tab Table 1: Device summary Order code Marking Package Packing STW8N90K5 8N90K5 TO-247 Tube November 2016 DocID030092 Rev 1 This is information on a product in full production. 1/12 www.st.com Contents STW8N90K5 Contents 1 Electrical ratings ............................................................................. 3 2 Electrical characteristics ................................................................ 4 2.1 Electrical characteristics (curves) ...................................................... 6 3 Test circuits ..................................................................................... 8 4 Package information ....................................................................... 9 4.1 5 2/12 TO-247 package information ............................................................. 9 Revision history ............................................................................ 11 DocID030092 Rev 1 STW8N90K5 1 Electrical ratings Electrical ratings Table 2: Absolute maximum ratings Symbol Parameter Value Unit VGS Gate-source voltage ±30 V ID(1) Drain current (continuous) at TC = 25 °C 8 A ID(1) Drain current (continuous) at TC = 100 °C 5 A ID(2) Drain current pulsed 32 A W PTOT Total dissipation at TC = 25 °C 130 dv/dt (3) Peak diode recovery voltage slope 4.5 dv/dt (4) MOSFET dv/dt ruggedness 50 TJ Operating junction temperature range Tstg Storage temperature range V/ns -55 to 150 °C Value Unit 0.96 °C/W 50 °C/W Value Unit Notes: (1)Limited (2)Pulse (3)I SD (4)V by maximum junction temperature. width limited by safe operating area ≤ 8 A, di/dt ≤ 100 A/μs; VDS peak ≤ V(BR)DSS DS ≤ 720 V Table 3: Thermal data Symbol Parameter Rthj-case Thermal resistance junction-case Rthj-amb Thermal resistance junction-ambient Table 4: Avalanche characteristics Symbol Parameter IAR Avalanche current, repetitive or not repetitive (pulse width limited by TJ max) 2.7 A EAS Single pulse avalanche energy (starting TJ = 25 °C, ID = IAR, VDD = 50 V) 250 mJ DocID030092 Rev 1 3/12 Electrical characteristics 2 STW8N90K5 Electrical characteristics TC = 25 °C unless otherwise specified Table 5: On/off-state Symbol Parameter V(BR)DSS Drain-source breakdown voltage Test conditions Min. VGS = 0 V, ID = 1 mA 900 Typ. Max. Unit V VGS = 0 V, VDS = 900 V 1 µA IDSS Zero gate voltage drain current VGS = 0 V, VDS = 900 V, TC = 125 °C(1) 50 µA IGSS Gate body leakage current VDS = 0 V, VGS = ±20 V ±10 µA VGS(th) Gate threshold voltage VDS = VGS, ID = 100 µA 4 5 V RDS(on) Static drain-source on-resistance VGS = 10 V, ID = 4 A 0.60 0.68 Ω Min. Typ. Max. Unit - 426 - pF - 41 - pF - 1.2 - pF - 75 - pF - 28 - pF 3 Notes: (1)Defined by design, not subject to production test. Table 6: Dynamic Symbol Ciss Parameter Test conditions Input capacitance VDS = 100 V, f = 1 MHz, VGS = 0 V Coss Output capacitance Crss Reverse transfer capacitance Co(tr)(1) Equivalent capacitance time related Co(er)(2) Equivalent capacitance energy related VDS = 0 to 720 V, VGS = 0 V Rg Intrinsic gate resistance f = 1 MHz , ID= 0 A - 7 - Ω Qg Total gate charge - 11 - nC Qgs Gate-source charge - 3.5 - nC Qgd Gate-drain charge VDD = 720 V, ID = 8 A, VGS= 10 V (see Figure 15: "Test circuit for gate charge behavior") - 4.8 - nC Notes: (1)Time related is defined as a constant equivalent capacitance giving the same charging time as Coss when V DS increases from 0 to 80% VDSS (2)Energy related is defined as a constant equivalent capacitance giving the same stored energy as Coss when VDS increases from 0 to 80% VDSS 4/12 DocID030092 Rev 1 STW8N90K5 Electrical characteristics Table 7: Switching times Symbol Parameter td(on) Turn-on delay time tr Rise time td(off) Turn-off delay time tf Fall time Test conditions Min. Typ. Max. Unit VDD= 450 V, ID = 4 A, RG = 4.7 Ω, VGS = 10 V (see Figure 14: "Test circuit for resistive load switching times" and Figure 19: "Switching time waveform") - 14.7 - ns - 13.2 - ns - 36.4 - ns - 13.5 - ns Min. Typ. Max. Unit Table 8: Source-drain diode Symbol Parameter Test conditions ISD Source-drain current - 8 A ISDM(1) Source-drain current (pulsed) - 32 A VSD(2) Forward on voltage ISD = 8 A, VGS = 0 V - 1.5 V ISD = 8 A, di/dt = 100 A/µs, VDD = 60 V (see Figure 16: "Test circuit for inductive load switching and diode recovery times") - 371 ns - 4.27 µC - 23 A ISD = 8 A, di/dt = 100 A/µs, VDD = 60 V, Tj = 150 °C (see Figure 16: "Test circuit for inductive load switching and diode recovery times") - 582 ns - 5.73 µC - 19.7 A trr Reverse recovery time Qrr Reverse recovery charge IRRM Reverse recovery current trr Reverse recovery time Qrr Reverse recovery charge IRRM Reverse recovery current Notes: (1)Pulse width limited by safe operating area (2)Pulsed: pulse duration = 300 µs, duty cycle 1.5% Table 9: Gate-source Zener diode Symbol V (BR)GSO Parameter Test conditions Gate-source breakdown voltage IGS= ± 1mA, ID= 0A Min Typ. Max Unit 30 - - V The built-in back-to-back Zener diodes are specifically designed to enhance the ESD performance of the device. The Zener voltage facilitates efficient and cost-effective device integrity protection,thus eliminating the need for additional external componentry. DocID030092 Rev 1 5/12 Electrical characteristics 2.1 STW8N90K5 Electrical characteristics (curves) Figure 2: Safe operating area Figure 3: Thermal impedance CG20930 K δ = 0.5 δ = 0.2 δ = 0.1 10-1 Z Zthth == kk R Rthj-C thj-C δδ == ttp // Ƭ Ƭ p δ = 0.05 δ = 0.02 δ = 0.01 tp SINGLE PULSE ƬƬ -2 10 10-5 10-4 10-3 10-2 10-1 tp(s) Figure 4: Output characteristics Figure 5: Transfer characteristics Figure 6: Gate charge vs gate-source voltage Figure 7: Static drain-source on-resistance 6/12 DocID030092 Rev 1 STW8N90K5 Electrical characteristics Figure 8: Capacitance variations Figure 9: Normalized gate threshold voltage vs temperature Figure 10: Normalized on-resistance vs temperature Figure 11: Normalized V(BR)DSS vs temperature Figure 12: Source-drain diode forward characteristics Figure 13: Maximum avalanche energy vs starting TJ DocID030092 Rev 1 7/12 Test circuits 3 STW8N90K5 Test circuits Figure 14: Test circuit for resistive load switching times Figure 15: Test circuit for gate charge behavior VDD RL IG= CONST VGS + pulse width 2200 μF 100 Ω D.U.T. 2.7 kΩ VG 47 kΩ 1 kΩ AM01469v10 8/12 Figure 16: Test circuit for inductive load switching and diode recovery times Figure 17: Unclamped inductive load test circuit Figure 18: Unclamped inductive waveform Figure 19: Switching time waveform DocID030092 Rev 1 STW8N90K5 4 Package information Package information In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK ® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. 4.1 TO-247 package information Figure 20: TO-247 package outline DocID030092 Rev 1 9/12 Package information STW8N90K5 Table 10: TO-247 package mechanical data mm Dim. Min. Max. A 4.85 5.15 A1 2.20 2.60 b 1.0 1.40 b1 2.0 2.40 b2 3.0 3.40 c 0.40 0.80 D 19.85 20.15 E 15.45 15.75 e 5.30 L 14.20 14.80 L1 3.70 4.30 L2 10/12 Typ. 5.45 5.60 18.50 ØP 3.55 ØR 4.50 S 5.30 DocID030092 Rev 1 3.65 5.50 5.50 5.70 STW8N90K5 5 Revision history Revision history Table 11: Document revision history Date Revision 28-Nov-2016 1 Changes First release DocID030092 Rev 1 11/12 STW8N90K5 IMPORTANT NOTICE – PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement. Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers’ products. No license, express or implied, to any intellectual property right is granted by ST herein. Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners. Information in this document supersedes and replaces information previously supplied in any prior versions of this document. © 2016 STMicroelectronics – All rights reserved 12/12 DocID030092 Rev 1