STW9N150

STW9N150 N-channel 1500V - 2.2Ω - 8A - TO-247 Very high voltage PowerMESH™ Power MOSFET TARGET SPECIFICATION General features Type STW9N150 ■ ■ ■ ■ ■ ■ VDSS 1500V RDS(on) < 2.7Ω ID 8A Pw 350W 100% avalanche tested Avalanche ruggedness Gate charge minimized Very low intrinsic capacitances High speed switching Very low on-resistance TO-247 Description Using the well consolidated high voltage MESH OVERLAY™ process, STMicroelectronics has designed an advanced family of Power MOSFETs with outstanding performances. The strengthened layout coupled with the Company’s proprietary edge termination structure, gives the lowest RDS(on) per area, unrivalled gate charge and switching characteristics. Internal schematic diagram Applications ■ Switching application Order code Part number STW9N150 Marking W9N150V Package TO-247 Packaging Tube May 2007 Rev 1 1/9 www.st.com 9 This is preliminary information on a new product foreseen to be developed. Details are subject to change without notice. Electrical ratings STW9N150 1 Electrical ratings Table 1. Symbol VDS VGS ID ID IDM (1) Absolute maximum ratings Parameter Drain-source voltage (VGS = 0) Gate- source voltage Drain current (continuous) at TC = 25°C Drain current (continuous) at TC = 100°C Drain current (pulsed) Total dissipation at TC = 25°C Derating factor Value 1500 ± 30 8 5 32 350 0.37 -55 to 150 Unit V V A A A W W/°C °C PTOT Tj Tstg Operating junction temperature Storage temperature 1. Pulse width limited by safe operating area Table 2. Symbol Thermal data Parameter Value 0.36 62.5 Unit °C/W °C/W Rthj-case Thermal resistance junction-case max Rthj-amb Thermal resistance junction-ambient max Table 3. Symbol IAR EAS Avalanche characteristics Parameter Avalanche current, repetitive or not-repetitive (pulse width limited by Tj max) Single pulse avalanche energy (starting Tj = 25°C, ID = IAR, VDD = 50V) Max value Tbd Tbd Unit A mJ 2/9 STW9N150 Electrical characteristics 2 Electrical characteristics (Tcase =25°C unless otherwise specified) Table 4. Symbol V(BR)DSS IDSS IGSS VGS(th) RDS(on On /off states Parameter Drain-source breakdown voltage Test conditions ID = 1mA, VGS = 0 Min. 1500 10 500 ± 100 3 4 2.2 5 2.7 Typ. Max. Unit V µA µA nA V Ω VDS = Max rating Zero gate voltage drain current (VGS = 0) VDS = Max rating, TC=125°C Gate-body leakage current (VDS = 0) VGS = ± 30V Gate threshold voltage VDS = VGS, ID = 250µA Static drain-source on resistance VGS = 10V, ID = 1.3A Table 5. Symbol gfs (1) Ciss Coss Crss Dynamic Parameter Forward transconductance Input capacitance Output capacitance Reverse transfer capacitance Gate input resistance Total gate charge Gate-source charge Gate-drain charge Test conditions VDS = 30V, ID = 2A Min. Typ. Tbd 3600 280 35 Max. Unit S pF pF pF VDS = 25 V, f = 1 MHz, VGS = 0 Rg Qg Qgs Qgd f=1MHz Gate DC Bias=0 Test signal level=20mV open drain VDD = 600V, ID = 2.5A, VGS = 10V (see Figure 2) 2 90 Tbd Tbd Ω nC nC nC 1. Pulsed: Pulse duration = 300 µs, duty cycle 1.5% 3/9 Electrical characteristics STW9N150 Table 6. Symbol td(on) tr td(off) tf Switching times Parameter Turn-on delay time Rise time Turn-off-delay time Fall time Test conditions VDD = 750V, ID = 2A, RG = 4.7Ω, VGS = 10V (see Figure 1) Min. Typ. Tbd Tbd Tbd Tbd Max Unit ns ns ns ns Table 7. Symbol ISD ISDM (1) Source drain diode Parameter Source-drain current Source-drain current (pulsed) Forward on voltage Reverse recovery time Reverse recovery charge Reverse recovery current Reverse recovery time Reverse recovery charge Reverse recovery current ISD = 4A, VGS = 0 ISD = 4A, di/dt = 100A/µs VDD= 45V Tj = 25°C (see Figure 3) ISD = 4A, di/dt = 100A/µs VDD= 45V Tj = 150°C (see Figure 3) Tbd Tbd Tbd Tbd Tbd Tbd Test conditions Min. Typ. Max Unit 8 32 Tbd A A V ns µC A ns µC A VSD (2) trr Qrr IRRM trr Qrr IRRM 1. Pulse width limited by safe operating area 2. Pulsed: pulse duration = 300µs, duty cycle 1.5% 4/9 STW9N150 Test circuits 3 Figure 1. Test circuits Switching times test circuit for resistive load Figure 2. Gate charge test circuit Figure 3. Test circuit for inductive load Figure 4. switching and diode recovery times Unclamped Inductive load test circuit Figure 5. Unclamped inductive waveform Figure 6. Switching time waveform 5/9 Package mechanical data STW9N150 4 Package mechanical data In order to meet environmental requirements, ST offers these devices in ECOPACK® packages. These packages have a Lead-free second level interconnect. The category of second level interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com 6/9 STW9N150 Package mechanical data TO-247 MECHANICAL DATA mm. MIN. 4.85 2.20 1.0 2.0 3.0 0.40 19.85 15.45 5.45 14.20 3.70 18.50 3.55 4.50 5.50 3.65 5.50 0.140 0.177 0.216 14.80 4.30 0.560 0.14 0.728 0.143 0.216 TYP MAX. 5.15 2.60 1.40 2.40 3.40 0.80 20.15 15.75 MIN. 0.19 0.086 0.039 0.079 0.118 0.015 0.781 0.608 0.214 0.582 0.17 inch TYP. MAX. 0.20 0.102 0.055 0.094 0.134 0.03 0.793 0.620 DIM. A A1 b b1 b2 c D E e L L1 L2 øP øR S 7/9 Revision history STW9N150 5 Revision history Table 8. Date 24-May-2007 Revision history Revision 1 First release Changes 8/9 STW9N150 Please Read Carefully: Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale. Purchasers are solely responsible for the choice, selection and use of the ST products and services described herein, and ST assumes no liability whatsoever relating to the choice, selection or use of the ST products and services described herein. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. 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