STWA40N95K5

STWA40N95K5 N-channel 950 V, 0.110 Ω typ., 38 A MDmesh™ K5 Power MOSFET in a TO-247 long leads package Datasheet - production data Features Order code VDS RDS(on) max ID PTOT STWA40N95K5 950 V 0.130 Ω 38 A 450 W      Industry’s lowest RDS(on) x area Industry’s best figure of merit (FoM) Ultra low gate charge 100% avalanche tested Zener-protected Applications Figure 1: Internal schematic diagram  Switching applications Description D(2, TAB) This very high voltage N-channel Power MOSFET is designed using MDmesh™ K5 technology based on an innovative proprietary vertical structure. The result is a dramatic reduction in on-resistance and ultra-low gate charge for applications requiring superior power density and high efficiency. G(1) S(3) AM01476v1 Table 1: Device summary Order code Marking Package Packaging STWA40N95K5 40N95K5 TO-247 Tube August 2015 DocID028207 Rev 1 This is information on a product in full production. 1/13 www.st.com Contents STWA40N95K5 Contents 1 Electrical ratings ............................................................................. 3 2 Electrical characteristics ................................................................ 4 2.1 Electrical characteristics (curves) ...................................................... 6 3 Test circuits ..................................................................................... 9 4 Package mechanical data ............................................................. 10 4.1 5 2/13 TO-247 long leads package information ......................................... 10 Revision history ............................................................................ 12 DocID028207 Rev 1 STWA40N95K5 1 Electrical ratings Electrical ratings Table 2: Absolute maximum ratings Symbol VGS Parameter Unit ± 30 V ID Drain current (continuous) at TC = 25 °C 38 A ID Drain current (continuous) at TC = 100 °C 24 A Drain current (pulsed) 152 A Total dissipation at TC = 25 °C 450 W IAR Max current during repetitive or single pulse avalanche 13 A EAS Single pulse avalanche energy (starting TJ = 25 °C, ID= 13 A, VDD= 50 V) 700 mJ Peak diode recovery voltage slope 4.5 V/ns MOSFET dv/dt ruggedness 50 V/ns -55 to 150 °C IDM Gate- source voltage Value (1) PTOT dv/dt (2) dv/dt (3) Tj Tstg Operating junction temperature Storage temperature Notes: (1)Pulse (2)I SD (3)V width limited by safe operating area. ≤ 19 A, di/dt ≤ 100 A/µs, VDS(peak) ≤ V(BR)DSS. DS ≤ 760 V Table 3: Thermal data Symbol Parameter Value Unit Rthj-case Thermal resistance junction-case max 0.28 °C/W Rthj-amb Thermal resistance junction-amb max 50 °C/W DocID028207 Rev 1 3/13 Electrical characteristics 2 STWA40N95K5 Electrical characteristics (Tcase =25 °C unless otherwise specified) Table 4: On /off states Symbol V(BR)DSS Parameter Test conditions Drain-source breakdown voltage VGS = 0, ID = 1 mA Min. Typ. Max. 950 Unit V VGS = 0, VDS = 950 V 1 µA VGS = 0, VDS = 950 V, TC=125 °C 50 µA Gate-body leakage current VDS=0, VGS = ± 20 V ±10 µA VGS(th) Gate threshold voltage VDS = VGS, ID = 100 µA 4 5 V RDS(on) Static drain-source onresistance VGS = 10 V, ID = 19 A 0.110 0.130 Ω Min. Typ. Max. Unit - 3300 - pF - 250 - pF - 2 - pF - 398 - pF - 142 - pF 5 - Ω IDSS Zero gate voltage drain current IGSS 3 Table 5: Dynamic Symbol Parameter Ciss Input capacitance Coss Output capacitance Crss Reverse transfer capacitance Co(tr)(1) Test conditions VGS=0, VDS =100 V, f=1 MHz Equivalent capacitance time related VGS = 0, VDS = 0 to 760 V Co(er)(2) Equivalent capacitance energy related RG Intrinsic gate resistance f = 1 MHz, ID=0 - VDD = 760 V, ID = 38 A VGS =10 V (see Figure 16: "Gate charge test circuit") - 93 - nC - 18.7 - nC - 63.4 - nC Qg Total gate charge Qgs Gate-source charge Qgd Gate-drain charge Notes: (1)Time related is defined as a constant equivalent capacitance giving the same charging time as C oss when VDS increases from 0 to 80% VDSS (2)energy related is defined as a constant equivalent capacitance giving the same stored energy as C oss when VDS increases from 0 to 80% VDSS Table 6: Switching times Symbol td(on) tr td(off) tf 4/13 Parameter Turn-on delay time Rise time Turn-off-delay time Fall time Test conditions VDD = 475 V, ID = 19 A, RG = 4.7 Ω, VGS = 10 V (see Figure 15: "Switching times test circuit for resistive load") DocID028207 Rev 1 Min. Typ. Max Unit - 33.5 - ns - 51 - ns - 91.5 - ns - 10 - ns STWA40N95K5 Electrical characteristics Table 7: Source drain diode Symbol Parameter Test conditions Min. Typ. Max Unit ISD Source-drain current - 38 A ISDM (1) Source-drain current (pulsed) - 152 A VSD (2) Forward on voltage ISD = 38 A, VGS = 0 - 1.5 V trr Reverse recovery time - 706 ns Qrr Reverse recovery charge - 22 µC IRRM Reverse recovery current ISD = 38 A, di/dt = 100 A/µs VDD= 60 V (see Figure 18: "Unclamped inductive load test circuit") - 62 A ISD = 38 A, di/dt = 100 A/µs VDD= 60 V TJ = 150 °C (see Figure 18: "Unclamped inductive load test circuit") - 886 ns - 28.2 µC - 64 A trr Reverse recovery time Qrr Reverse recovery charge IRRM Reverse recovery current Notes: (1)Pulse width limited by safe operating area. (2)Pulsed: pulse duration = 300 µs, duty cycle 1.5% Table 8: Gate-source Zener diode Symbol V(BR)GSO Parameter Gate-source breakdown voltage Test conditions IGS = ± 1mA, ID=0 Min Typ. Max. Unit 30 - - V The built-in back-to-back Zener diodes have specifically been designed to enhance the device's ESD capability. In this respect the Zener voltage is appropriate to achieve an efficient and cost-effective intervention to protect the device's integrity. These integrated Zener diodes thus avoid the usage of external components. DocID028207 Rev 1 5/13 Electrical characteristics 2.1 6/13 STWA40N95K5 Electrical characteristics (curves) Figure 2: Safe operating area Figure 3: Thermal impedance Figure 4: Output characteristics Figure 5: Transfer characteristics Figure 6: Gate charge vs gate-source voltage Figure 7: Static drain-source on-resistance DocID028207 Rev 1 STWA40N95K5 Electrical characteristics Figure 8: Capacitance variations Figure 9: Normalized gate threshold voltage vs temperature Figure 10: Normalized on-resistance Figure 11: Normalized V(BR)DSS vs temperature GIPD121120141039FSR R DS(on) (norm) 1.12 2.6 V GS= 10V ID= 1m A 2.2 1.08 1.8 1.04 1.4 1.00 1 0.96 0.6 0.92 0.2 -50 GIPD121120141041FSR V (BR)DSS (norm) 0 50 100 T j(°C) Figure 12: Output capacitance stored energy DocID028207 Rev 1 0.88 -50 0 50 100 T j(°C) Figure 13: Source-drain diode forward characteristics 7/13 Electrical characteristics STWA40N95K5 Figure 14: Maximum avalanche energy vs T J GIPD141120141040FSR E AS (mJ) 600 400 200 0 -50 8/13 Single pulse ID= 13 A V DD= 50V 0 50 DocID028207 Rev 1 100 T j(°C) STWA40N95K5 3 Test circuits Test circuits Figure 15: Switching times test circuit for resistive load Figure 16: Gate charge test circuit Figure 17: Test circuit for inductive load switching and diode recovery times Figure 18: Unclamped inductive load test circuit Figure 19: Unclamped inductive waveform Figure 20: Switching time waveform DocID028207 Rev 1 9/13 Package mechanical data 4 STWA40N95K5 Package mechanical data In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK ® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. 4.1 TO-247 long leads package information Figure 21: TO-247 long leads package outline 10/13 DocID028207 Rev 1 STWA40N95K5 Package mechanical data Table 9: TO-247 long leads package mechanical data mm. Dim. Min. Typ. Max. A 4.90 5.00 5.10 A1 2.31 2.41 2.51 A2 1.90 2.00 2.10 b 1.16 1.26 b2 3.25 b3 2.25 c 0.59 0.66 D 20.90 21.00 21.10 E 15.70 15.80 15.90 E2 4.90 5.00 5.10 E3 2.40 2.50 2.60 e 5.34 5.44 5.54 L 19.80 19.92 20.10 P 3.50 3.60 Q 5.60 S 6.05 L1 4.30 DocID028207 Rev 1 3.70 6.00 6.15 6.25 11/13 Revision history 5 STWA40N95K5 Revision history Table 10: Document revision history 12/13 Date Revision 05-Aug-2015 1 DocID028207 Rev 1 Changes First release. STWA40N95K5 IMPORTANT NOTICE – PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement. Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers’ products. No license, express or implied, to any intellectual property right is granted by ST herein. Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners. Information in this document supersedes and replaces information previously supplied in any prior versions of this document. © 2015 STMicroelectronics – All rights reserved DocID028207 Rev 1 13/13