STWA75N60M6

STWA75N60M6 Datasheet N-channel 600 V, 32 mΩ typ., 72 A, MDmesh™ M6 Power MOSFET in a TO‑247 long leads package Features D(2, TAB) Order code VDS RDS(on) max. ID STWA75N60M6 600 V 36 mΩ 72 A • • Reduced switching losses Lower RDS(on) per area vs previous generation • • • Low gate input resistance 100% avalanche tested Zener-protected Applications • • • G(1) S(3) AM01475V1 Switching applications LLC converters Boost PFC converters Description The new MDmesh™ M6 technology incorporates the most recent advancements to the well-known and consolidated MDmesh family of SJ MOSFETs. STMicroelectronics builds on the previous generation of MDmesh devices through its new M6 technology, which combines excellent RDS(on) per area improvement with one of the most effective switching behaviors available, as well as a user-friendly experience for maximum end-application efficiency. Product status link STWA75N60M6 Product summary Order code STWA75N60M6 Marking 75N60M6 Package TO-247 long leads Packing Tube DS12418 - Rev 2 - November 2018 For further information contact your local STMicroelectronics sales office. www.st.com STWA75N60M6 Electrical ratings 1 Electrical ratings Table 1. Absolute maximum ratings Symbol Value Unit Gate-source voltage ±25 V Drain current (continuous) at TC = 25 °C 72 A Drain current (continuous) at TC = 100 °C 45 A IDM(1) Drain current (pulsed) 288 A PTOT Total power dissipation at TC = 25 °C 446 W dv/dt(2) Peak diode recovery voltage slope 15 dv/dt(3) MOSFET dv/dt ruggedness 100 Tstg Storage temperature range VGS ID TJ Parameter Operating junction temperature range V/ns -55 to 150 °C Value Unit 0.28 °C/W 50 °C/W Value Unit 1. Pulse width is limited by safe operating area. 2. ISD ≤ 72 A, di/dt = 400 A/µs, VDS(peak) < V(BR)DSS, VDD = 400 V 3. VDS ≤ 480 V Table 2. Thermal data Symbol Parameter Rthj-case Thermal resistance junction-case Rthj-amb Thermal resistance junction-ambient Table 3. Avalanche characteristics Symbol DS12418 - Rev 2 Parameter IAR Avalanche current, repetitive or not repetitive (pulse width limited by TJmax) 11 A EAS Single pulse avalanche energy (starting TJ = 25 °C, ID = IAR, VDD = 50 V) 1.4 J page 2/13 STWA75N60M6 Electrical characteristics 2 Electrical characteristics (TC = 25 °C unless otherwise specified) Table 4. On /off-states Symbol V(BR)DSS Parameter Test conditions Drain-source breakdown voltage VGS(th) RDS(on) TC = 125 VDS = 0 V, VGS = ±25 V Gate threshold voltage VDS = VGS, ID = 250 µA Static drain-source 1 100 µA ±5 µA 4 4.75 V 32 36 mΩ Min. Typ. Max. Unit - 4850 - pF - 380 - pF - 3.5 - pF 3.25 VGS = 10 V, ID = 36 A on-resistance Unit V °C(1) Gate-body leakage current Max. 600 VGS = 0 V, VDS = 600 V, drain current IGSS Typ. VGS = 0 V, VDS= 600 V Zero-gate voltage IDSS VGS = 0 V, ID = 1 mA Min. 1. Defined by design, not subject to production test. Table 5. Dynamic Symbol Parameter Ciss Input capacitance Coss Output capacitance Crss Test conditions VGS = 0 V, VDS = 100 V, f = 1 MHz Reverse transfer capacitance (1) Equivalent output capacitance VGS = 0 V, VDS = 0 to 480 V - 851 - pF RG Intrinsic gate resistance f = 1 MHz open drain - 1.5 - Ω Qg Total gate charge VDD = 480 V, ID = 72 A, - 106 - nC Gate-source charge VGS = 0 to 10 V - 32 - nC Gate-drain charge (see Figure 14. Test circuit for gate charge behavior) - 45 - nC Coss eq. Qgs Qgd 1. Coss eq. is defined as the constant equivalent capacitance giving the same charging time as Coss when VDS increases from 0 to 80% VDSS. Table 6. Switching times Symbol td (on) tr td(off) tf DS12418 - Rev 2 Parameter Test conditions Min. Typ. Max. Unit Turn-on delay time VDD = 300 V, ID = 36 A, - 35 - ns Rise time RG = 4.7 Ω, VGS = 10 V - 38 - ns Turn-off delay time (see Figure 13. Test circuit for resistive load switching times and Figure 18. Switching time waveform) - 90 - ns - 12 - ns Fall time page 3/13 STWA75N60M6 Electrical characteristics Table 7. Source-drain diode Symbol ISD ISDM (1) (2) Parameter Test conditions Min. Typ. Max. Unit Source-drain current - 72 A Source-drain current (pulsed) - 288 A 1.6 V Forward on voltage VGS = 0 V, ISD = 72 A - trr Reverse recovery time ISD = 72 A, di/dt = 100 A/µs, - 367 ns Qrr Reverse recovery charge - 6.4 µC IRRM Reverse recovery current VDD = 60 V (see Figure 15. Test circuit for inductive load switching and diode recovery times) - 35 A trr Reverse recovery time ISD = 72 A, di/dt = 100 A/µs, - 552 ns Qrr Reverse recovery charge VDD = 60 V, TJ = 150 °C - 13.7 µC Reverse recovery current (see Figure 15. Test circuit for inductive load switching and diode recovery times) - 49.6 A VSD IRRM 1. Pulse width is limited by safe operating area. 2. Pulse test: pulse duration = 300 µs, duty cycle 1.5%. DS12418 - Rev 2 page 4/13 STWA75N60M6 Electrical characteristics (curves) 2.1 Electrical characteristics (curves) Figure 2. Thermal impedance Figure 1. Safe operating area ID (A) GADG211120181126SOA d=0.5 tp=1 μs Operation in this area is limited by RDS(on) 10 2 0.2 tp =10 µs 0.1 tp =100 µs 10 1 10 AM09125v1 K tp =1 ms 0.05 10 -1 0.02 0.01 Single pulse, TC = 25 °C, TJ ≤ 150 °C, VGS = 10 V Zth =k *Rthj-c d=t p /t tp =10 ms Single pulse 0 tp t -2 10 -1 10 -1 10 0 10 1 VDS (V) 10 2 10 -4 10 10 -3 10 -2 10 -1 t p (s) Figure 3. Output characteristics Figure 4. Transfer characteristics Figure 5. Gate charge vs gate-source voltage Figure 6. Static drain-source on-resistance VDS (V) GADG211120181125QVG VGS (V) VDD = 480 V, ID = 72 A 600 12 Qg 500 400 10 VDS 8 Qgd Qgs 300 6 200 4 100 2 0 0 DS12418 - Rev 2 20 40 60 80 100 120 0 Qg (nC) page 5/13 STWA75N60M6 Electrical characteristics (curves) Figure 7. Normalized on-resistance vs temperature RDS(on) (norm.) Figure 8. Normalized V(BR)DSS vs temperature V(BR)DSS (norm.) GADG051220171032RON 2.5 GADG051220171032BDV 1.10 2.0 1.05 VGS = 10 V 1.5 1.00 1.0 0.95 0.5 0.90 0 -75 -25 25 75 125 Tj (°C) 0.85 -75 -25 25 75 125 Tj (°C) Figure 10. Normalized gate threshold voltage vs temperature Figure 9. Capacitance variations C (pF) ID = 1 mA GADG051220171033CVR VGS(th) (norm.) 10 4 GADG051220171030VTH 1.1 CISS 1.0 10 3 COSS f = 1 MHz 10 2 0.9 ID = 250 µA 0.8 CRSS 10 1 0.7 10 0 10 -1 10 0 10 1 VDS (V) 10 2 Figure 11. Output capacitance stored energy EOSS (µJ) GADG051220171034EOS 0.6 -75 -25 25 75 Tj (°C) Figure 12. Source-drain diode forward characteristics VSD (V) GADG051220171033SDF 1.1 50 125 Tj = -50 °C 1.0 40 Tj = 25 °C 0.9 30 0.8 20 0.7 10 0 0 DS12418 - Rev 2 Tj = 150 °C 0.6 100 200 300 400 500 600 VDS (V) 0.5 0 10 20 30 40 50 60 70 ISD (A) page 6/13 STWA75N60M6 Test circuits 3 Test circuits Figure 13. Test circuit for resistive load switching times Figure 14. Test circuit for gate charge behavior VDD RL RL 2200 + μF 3.3 μF VDD VD RG VGS IG= CONST VGS + pulse width D.U.T. 2.7 kΩ 2200 μF pulse width D.U.T. 100 Ω VG 47 kΩ 1 kΩ AM01469v10 AM01468v1 Figure 15. Test circuit for inductive load switching and diode recovery times D G A D.U.T. S 25 Ω A L A VD 100 µH fast diode B B B 3.3 µF D G + Figure 16. Unclamped inductive load test circuit RG 1000 + µF 2200 + µF VDD 3.3 µF VDD ID D.U.T. S D.U.T. Vi _ pulse width AM01471v1 AM01470v1 Figure 18. Switching time waveform Figure 17. Unclamped inductive waveform ton V(BR)DSS td(on) toff td(off) tr tf VD 90% 90% IDM VDD 10% 0 ID VDD AM01472v1 VGS 0 VDS 10% 90% 10% AM01473v1 DS12418 - Rev 2 page 7/13 STWA75N60M6 Package information 4 Package information In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. DS12418 - Rev 2 page 8/13 STWA75N60M6 TO-247 long leads package information 4.1 TO-247 long leads package information Figure 19. TO-247 long leads package outline 8463846_2_F DS12418 - Rev 2 page 9/13 STWA75N60M6 TO-247 long leads package information Table 8. TO-247 long leads package mechanical data Dim. mm Min. Typ. Max. A 4.90 5.00 5.10 A1 2.31 2.41 2.51 A2 1.90 2.00 2.10 b 1.16 1.26 b2 3.25 b3 2.25 c 0.59 0.66 D 20.90 21.00 21.10 E 15.70 15.80 15.90 E2 4.90 5.00 5.10 E3 2.40 2.50 2.60 e 5.34 5.44 5.54 L 19.80 19.92 20.10 L1 DS12418 - Rev 2 4.30 P 3.50 Q 5.60 S 6.05 3.60 3.70 6.00 6.15 6.25 page 10/13 STWA75N60M6 Revision history Table 9. Document revision history Date Version 11-Dec-2017 1 Changes Initial version Removed maturity status indication from cover page. The document status is production data. 30-Nov-2018 2 Updated Table 1. Absolute maximum ratings and Table 5. Dynamic. Updated Figure 5. Gate charge vs gate-source voltage and Figure 14. Test circuit for gate charge behavior. Minor text changes DS12418 - Rev 2 page 11/13 STWA75N60M6 Contents Contents 1 Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2 2 Electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2.1 Electrical characteristics (curves) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3 Test circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 4 Package information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 4.1 TO-247 long leads package information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 DS12418 - Rev 2 page 12/13 STWA75N60M6 IMPORTANT NOTICE – PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement. Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers’ products. No license, express or implied, to any intellectual property right is granted by ST herein. Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners. Information in this document supersedes and replaces information previously supplied in any prior versions of this document. © 2018 STMicroelectronics – All rights reserved DS12418 - Rev 2 page 13/13