STWLC03
Dual mode Qi/PMA wireless power receiver
Datasheet - production data
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Flip Chip 77 bumps (3.12x4.73 mm)
Applications
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Description
Features
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Cellular phones
Power banks
Navigation systems
Tablets
Medical and healthcare instrumentation
1 W to 12 W output power
Qi 1.1 and PMA wireless standard
communication protocols
Integrated high efficiency synchronous
rectifier
800 kHz programmable step-down converter
with input current and input voltage
regulation loops
Step-down converter efficiency up to 90%
Simplified Li-Ion/Polymer charger function
32-bit, 16 MHz embedded microcontroller
with 16 kB ROM and 2 kB RAM memory
2 kB NVM for customization
Integrated driver for external supply switch
Precise voltage and current measurements
for received power calculation
I2C interface
Configurable GPIO output
Rx coil NTC protection
Thermal protection
Low power dissipative rectifier overvoltage
clamp
The STWLC03 is an integrated wireless power
receiver solution suitable for portable
applications. The STWLC03 is able to operate
with Qi 1.1 or PMA communication protocol.
Thanks to the integrated low impedance
synchronous rectifier and DC-DC step-down
converter, the STWLC03 achieves high
efficiency, low power dissipation and output
power beyond 5 W. Digital control and precise
analog control loops ensure stable operation. I2C
interface allows many parameters to be
customized in the device and this configuration
can be stored in the embedded NVM.
The STWLC03 can deliver the output power in
two modes: as a power supply with configured
output voltage or as a simple CC/CV battery
charger with configurable charging current.
The STWLC03 can detect an external (wired)
power supply connection and drive an external
power switch.
Table 1: Device summary
Order code
Description
Package
Packing
STWLC03JR
12 W output
Flip Chip 77 bumps (3.12x4.73 mm)
Tape and reel
March 2017
DocID029451 Rev 2
This is information on a product in full production.
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www.st.com
Contents
STWLC03
Contents
1
Introduction ..................................................................................... 6
2
Pin configuration ............................................................................. 7
3
Maximum ratings ........................................................................... 10
4
5
Electrical characteristics .............................................................. 12
Device description......................................................................... 17
5.1
Using the STWLC03 as a power supply .......................................... 17
5.2
Using the STWLC03 as a battery charger ....................................... 17
5.3
Wireless standard auto-detection .................................................... 18
5.4
Qi operation and flow chart ............................................................. 19
5.4.1
6
7
5.5
PMA operation ................................................................................ 21
5.6
External power supply ..................................................................... 22
5.7
The device interface ........................................................................ 24
I2C register description ................................................................. 25
6.1
ADC measured values .................................................................... 31
6.2
Service registers ............................................................................. 33
Non-volatile memory ..................................................................... 35
7.1
8
8.1
Application schematic and recommended external components..... 45
8.2
External passive component selection ............................................ 49
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8.2.1
Input resonant circuit component selection (L1, C1, C2) ................. 49
8.2.2
Voltage clamp resistor selection (RCL1, RCL2) ............................... 49
8.2.3
Load modulation capacitors selection (CM1, CM2) ......................... 49
8.2.4
Feedback resistor divider components selection (RFB1, RFB2) ..... 49
8.2.5
Rx NTC circuit component selection (RNTC, R1) ............................ 49
8.2.6
Soft-start capacitor selection (C10) .................................................. 50
8.2.7
External supply transistor selection .................................................. 50
Reference PCB layout ..................................................................... 51
Package information ..................................................................... 53
9.1
10
NVM sector maps............................................................................ 35
Application information ................................................................ 45
8.3
9
Received power calibration (FOD feature) ....................................... 21
Flip Chip 77 bumps (3.12x4.73 mm) package information .............. 53
Revision history ............................................................................ 55
DocID029451 Rev 2
STWLC03
List of tables
List of tables
Table 1: Device summary ........................................................................................................................... 1
Table 2: Pin description .............................................................................................................................. 7
Table 3: Absolute maximum ratings ......................................................................................................... 10
Table 4: Thermal data ............................................................................................................................... 11
Table 5: Electrical characteristics ............................................................................................................. 12
Table 6: Recommended VRECT and VRMIN values for various VOUT .................................................. 17
Table 7: EPT reasons in Qi ....................................................................................................................... 20
Table 8: EOC reasons in PMA .................................................................................................................. 22
Table 9: User register map ....................................................................................................................... 25
Table 10: Control register ......................................................................................................................... 25
Table 11: Target rectified voltage register (register address 02h) ............................................................ 26
Table 12: Input voltage threshold for output power limitation register (register address 03h) ................. 26
Table 13: Input current limit register (register address 05h) ..................................................................... 26
Table 14: Overload threshold register (register address 06h) ..................................................................26
Table 15: Step-down output voltage register (register address 07h) ....................................................... 27
Table 16: Step-down converter feedback voltages .................................................................................. 27
Table 17: Buck current limit register ......................................................................................................... 27
Table 18: Chip overtemperature threshold register (register address 09h).............................................. 27
Table 19: Interrupt mask L register (register address 0Ah) ...................................................................... 27
Table 20: Interrupt mask H register ( register address 0Bh) .................................................................... 28
Table 21: Interrupt status L register ( register address 0Ch) .................................................................... 28
Table 22: Interrupt status H register ......................................................................................................... 29
Table 23: Interrupt latch L register ............................................................................................................ 29
Table 24: Interrupt latch H register ........................................................................................................... 29
Table 25: Operation mode detection status register ................................................................................. 30
Table 26: Operation mode detection control register (register address 11h) ........................................... 30
Table 27: Qi charge status register (register address 12h) ...................................................................... 31
Table 28: Charger status register (register address 13h) ......................................................................... 31
Table 29: Charger control register ............................................................................................................ 31
Table 30: ADC measured value register map .......................................................................................... 31
Table 31: Rectified voltage (VRECT)........................................................................................................ 32
Table 32: Rectified output current (IRECT) .............................................................................................. 32
Table 33: RX coil NTC voltage ................................................................................................................. 32
Table 34: VOUT voltage ........................................................................................................................... 32
Table 35: VDROP voltage ........................................................................................................................ 33
Table 36: Chip temperature ...................................................................................................................... 33
Table 37: Ground voltage ......................................................................................................................... 33
Table 38: RX_POWER ............................................................................................................................. 33
Table 39: Service register map ................................................................................................................. 34
Table 40: NVM control .............................................................................................................................. 34
Table 41: I2C registers corresponding to bytes in NVM sector ................................................................ 34
Table 42: Non-volatile memory sector map .............................................................................................. 35
Table 43: Map of NVM sector 04 .............................................................................................................. 35
Table 44: Byte 0 ........................................................................................................................................ 36
Table 45: Byte 1 ........................................................................................................................................ 36
Table 46: Byte 2 ........................................................................................................................................ 36
Table 47: Byte 3 ........................................................................................................................................ 36
Table 48: Byte 4 ........................................................................................................................................ 37
Table 49: Map of NVM sector 05 .............................................................................................................. 37
Table 50: Map of NVM sector 07 .............................................................................................................. 38
Table 51: Map of NVM sector 08 .............................................................................................................. 39
Table 52: Map of NVM sector 10 .............................................................................................................. 40
Table 53: Map of NVM sector 13 .............................................................................................................. 41
DocID029451 Rev 2
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List of tables
STWLC03
Table 54: Byte 0 Qi_EPT_threshold [7:0] ................................................................................................. 41
Table 55: Byte 1, Qi_EPT_Time [7:0] ....................................................................................................... 41
Table 56: Byte 2, Qi charger enable ......................................................................................................... 42
Table 57: Qi target voltage ....................................................................................................................... 42
Table 58: Byte 3, Q1_Precharge_Battery_overvoltage ............................................................................42
Table 59: Byte 4, Q1_Precharge and Fastcharge .................................................................................... 42
Table 60: Byte 8, PMA_EOC_theshold [7:0] ............................................................................................ 43
Table 61: Byte 9, PMA_EOC_Time [7:0] .................................................................................................. 43
Table 62: Byte 10, PMA_Target_Voltage [2:0] ......................................................................................... 43
Table 63: PMA target voltage vs charging voltage ................................................................................... 44
Table 64: Byte 11 ...................................................................................................................................... 44
Table 65: Byte 12 ...................................................................................................................................... 44
Table 66: STWLC03 recommended external components....................................................................... 46
Table 67: Flip Chip 77 bumps (3.12x4.73 mm) package mechanical data .............................................. 54
Table 68: Document revision history ........................................................................................................ 55
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DocID029451 Rev 2
STWLC03
List of figures
List of figures
Figure 1: Simplified block diagram .............................................................................................................. 6
Figure 2: Pin configuration Flip Chip 77 bumps (3.12x4.73 mm) ............................................................... 7
Figure 3: Typical step-down converter efficiency ..................................................................................... 17
Figure 4: Typical charging profile .............................................................................................................. 18
Figure 5: Wireless standard detection flowchart ....................................................................................... 19
Figure 6: Qi simplified flow diagram .......................................................................................................... 20
Figure 7: PMA simplified flow diagram ..................................................................................................... 21
Figure 8: External power supply situation ................................................................................................. 23
Figure 9: External power supply situation 1 .............................................................................................. 23
Figure 10: STWLC03 application schematic ............................................................................................ 45
Figure 11: STWLC03 charger configuration ............................................................................................. 46
Figure 12: VIO and digital interface in standalone application schematic ................................................ 48
Figure 13: VIO and digital interface in platform application schematic ..................................................... 48
Figure 14: Top overlay .............................................................................................................................. 51
Figure 15: Top layer .................................................................................................................................. 51
Figure 16: Mid layer 1 ............................................................................................................................... 51
Figure 17: Mid layer 2 ............................................................................................................................... 51
Figure 18: Bottom layer............................................................................................................................. 52
Figure 19: Flip Chip 77 bumps (3.12x4.73 mm) package outline ............................................................. 53
Figure 20: Flip Chip 77 bumps (3.12x4.73 mm) recommended footprint ................................................. 54
DocID029451 Rev 2
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Introduction
1
STWLC03
Introduction
The STWLC03 is a dual mode Qi/PMA wireless power receiver. It works as a voltage
source with regulated output voltage, typically 5 V. It can be reconfigured into a simple
battery charger mode (CC/CV) to charge directly Li-Ion or Li-Pol batteries. The STWLC03
can operate autonomously or can be controlled through I2C by the host system.
Figure 1: Simplified block diagram
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DocID029451 Rev 2
Pin configuration
STWLC03
2
Pin configuration
Figure 2: Pin configuration Flip Chip 77 bumps (3.12x4.73 mm)
Table 2: Pin description
Pin name
Pin position
Description
AC1
F6, F7, G7
RX coil circuit terminal connection
AC2
E9, E10, E11
RX coil circuit terminal connection
MOD1
G6
Load modulation capacitor 1 connection
MOD2
F11
Load modulation capacitor 2 connection
CLMP1
G5
Clamping capacitor/resistor 1 connection
CLMP2
F9
Clamping capacitor/resistor 2 connection
RMOD
E7
Modulation current sink connection, internally connected to
VRECT
RMOD1
G11
VRECT
F10, G10
BOOT1
G8
Bootstrap capacitor connection for the rectifier
BOOT2
E8
Bootstrap capacitor connection for the rectifier
BOOT
G9
Bootstrap capacitor connection for the step-down converter
CLAMP
F8
Low power clamp connection
VSUP
A8, B8, B7
VSUPS
A7, C6
Load modulation external resistor connection.
RM resistor is not necessary for most applications
Synchronous rectifier output
Power supply input for the step-down converter
Sensing terminal of the external current sensing resistor
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Pin configuration
STWLC03
Pin name
Pin position
Description
RESL
A6
Sensing terminal of the external current sensing resistor
VOUT
D5
Step-down output voltage
VFB
A5
Step-down feedback input
FBGND
B6
Ground connection of the resistor feedback divider for stepdown converter
LX
A11, B11, B10
NTCRX
A3
Step-down converter coil connection
Comparator input for RX coil temperature sensing
NTC thermistor has to be placed close to RX coil
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VA
A4
LDO1 output to filtering capacitor. ADC supply and sensitive
analog circuitries are connected to this LDO; any external
circuit cannot be connected to this node
VCORE
F2
LDO2 output to filtering capacitor. The microcontroller core
and logic supply. VCORE voltage can be used as a reference
voltage for the RX coil NTC divider
V5V
A9, B9
VIO
G1
VIO power supply for the digital interface. It can be connected
to VCORE or provided externally
SCL
D1
I2C clock input
SDA
D4
I2C data
GPIO0
D6
General purpose push-pull I/O pin. This function depends on
firmware configuration
GPIO1
E5
General purpose push-pull I/O pin. This function depends on
firmware configuration
GPIO2
E4
General purpose push-pull I/O pin. This function depends on
firmware configuration
GPIO3
E1
Open drain output pin only. This function depends on firmware
configuration
RESET
D2
Chip reset input, active low
INT
C3
Open drain interrupt output to the host platform
RPGND
D8, D9, D10, D11
Rectifier power ground
BPGND
C8, C9, C10, C11
Step-down converter power ground
GND
G2, F3
Digital ground
AGND
B4, C4, B5, C5
Analog ground
VEXT
A10
Detection of the external power supply voltage – adapter/USB
voltage. 30 V spike tolerant
SWDRV
D7
External P-channel switch control for connecting adapter/USB
voltage to VOUT
USBOK
C2
Digital input for the USBOK signal from platforms
COMP
C7
Step-down converter soft-start capacitor connection
GND
G4, F4
Reserved. Connect to ground
VCORE
A1
Reserved. Connect to VCORE
LDO3 output to filtering capacitor
DocID029451 Rev 2
Pin configuration
STWLC03
Pin name
Pin position
Description
N/C
G3
GND
B1, E2, E6, F1
Reserved. Connect to ground
N/C
B2, B3, D3, E3
Reserved. Do not connect
GND
C1
N/C
A2, F5
Reserved. Do not connect
Reserved. Connect to ground
Reserved. Do not connect
DocID029451 Rev 2
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Maximum ratings
3
STWLC03
Maximum ratings
Table 3: Absolute maximum ratings
Pin
Value
Unit
AC1, AC2
Input AC voltage
-0.3 to 20
V
MOD1, MOD2
Modulation transistor voltage
-0.3 to 20
V
CLMP1, CLMP2
Clamp transistor voltage
-0.3 to 20
V
BOOT1, BOOT2
Voltage on bootstraps
AC1, AC2 -0.3;
AC1, AC2 + 6
V
BOOT
Voltage on bootstrap
VRECT-0.3;
VRECT + 6
V
VRECT
Rectified voltage
-0.3 to 20
V
VRESL, VSUPS
Current sensing resistor connection voltage
-0.3 to 20
V
VRESL-VSUPS
Voltage on the current sensing resistor
-0.3 to 2
V
VSUP
Input voltage of the buck converter
-0.3 to 20
V
LX
Buck converter switching node voltage
-0.3 to 20
V
RMOD, RMOD1
Resistive modulation current source and
transistor voltage
-0.3 to 20
V
FBGND
Internal feedback transistor VDS voltage
-0.3 to 20
V
VOUT
Output voltage range
-0.3 to 20
V
VFB
Buck converter feedback voltage
-0.3 to 3
V
VEXT, SWDRW
Detection pin for the external voltage and driver
output for the external transistor
-0.3 to 30
V
NTCRX
RX coil NTC voltage
-0.3 to 2.3
V
VA, VCORE
LDO1,2 voltages
-0.3 to 2.3
V
V5V
LDO 3 voltage
-0.3 to 6
V
VIO
VIO voltage
-0.3 to 6
V
SCL, SDA, USBOK,
INT, RESET
Digital interface voltage
-0.3 to VIO+0.3
V
GPIO0, GPIO1,
GPIO2, GPIO3
General purpose I/O voltage
-0.3 to VIO+0.3
V
TSTG
Storage temperature range
-40 to 150
°C
TOP
TJ
ESD
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Parameter
-40 to +85
°C
Maximum junction temperature
Operating ambient temperature range
+125
°C
Machine model
±100
V
Charged device model
±500
V
Human body model
±2000
V
DocID029451 Rev 2
Maximum ratings
STWLC03
Absolute maximum ratings are those values beyond which damage to the device
may occur. Functional operation under these conditions is not implied.
Table 4: Thermal data
Package
Flip Chip 77 (3.12x4.73 mm)
Symbol
RTHJA
Parameter
Junction-to-ambient thermal
resistance(1)
Value
Unit
35
°C/W
Notes:
(1)This
parameter corresponds to the PCB board, 4-layer with 1 inch2 of cooling area.
DocID029451 Rev 2
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Electrical characteristics
4
STWLC03
Electrical characteristics
-30 °C < TA < 85 °C; typical values are at T A = 25 °C, unless otherwise specified.
Table 5: Electrical characteristics
Symbol
Parameter
Test conditions
Min.
Typ.
Max.
Unit
General section
VIN
AC input voltage
VUVLO
Undervoltage
lockout threshold
TIMEOUTRESET
Reset time-out for
shutdown mode
Peak-to-peak
voltage between
AC1- AC2 over
the period
32
VSUP rising
VSUP falling
3.6
3.3
3.8
3.5
V
V
1
ms
RESET=0 (active
low) duration>1
ms, measured at
VEXT
10
μA
RESET=0 (active
low) duration>1
ms, measured at
VRECT
2
IRESET
Current
consumption in
the RESET
condition
RESET=0 (active
low), duration
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