STWLC38JRM

STWLC38 Datasheet Qi-compliant dual mode wireless power receiver for up to 15W applications Features • • • • • • • • • Product status link STWLC38 Product summary Order code STWLC38JRM Package WLCSP40 Packing Tape and Reel • • • • • • • • Up to 15 W output power Up to 5W output power in Tx mode Qi 1.3 inductive wireless standard communication protocol compliant High efficiency (98% typical) synchronous rectifier operating up to 800 kHz Low drop-out linear regulator with output current limit and input voltage control loop Adaptive Rectifier Configuration (ARC) Mode for enhanced spatial freedom 4 V to 12 V programmable output voltage Above 85% overall system efficiency 32-bit, 64 MHz ARM Cortex M0+ core with 32kB RRAM,16 kB SRAM,64kB ROM 10-bit A/D Converter Configurable GPIOs I2C Slave interface Multi-level ASK modulator, Enhanced FSK demodulator Output Over-Voltage clamping protection Accurate voltage/current measurement for Foreign Object Detection (FOD) On-chip thermal management and protections Flip chip 40 bumps (2.12mm x 3.32mm) Applications • • • • Smartphones Wearable/Hearables TWS Asset tracking devices Medical and healthcare equipment Description The STWLC38 is an integrated Wireless Power Receiver suitable for wearable/ hearable and smart phone applications and can supply up to 15 W of output power. The chip has been designed to support Qi 1.3 specifications for inductive communication protocol, 5W Baseline Power Profile and 15W Extended Power Profile. STWLC38 shows excellent efficiency performance thanks to the integrated low-loss synchronous rectifier and the low drop-out linear regulator: both elements are dynamically managed by the digital core to minimize the overall power dissipation over a wide range of output load conditions. Through the I2C interface the user can access and modify different configuration parameters, tailoring the operation of the device to the needs of custom applications. The configuration parameters can be saved in the embedded Resistive RAM (RRAM) and automatically retrieved at power-up. STWLC38 is also capable of operating in Tx mode to transmit power to charge other devices. The device can provide power up to 5W Output power in this mode. The STWLC38 is housed in a Chip-Scale Package to fit real-estate sensitive solutions in wearable devices. DS14078 - Rev 1 - September 2022 further information contact your local STMicroelectronics sales office. DownloadedFor from Arrow.com. www.st.com STWLC38 Introduction 1 Introduction STWLC38 is a Wireless Power Receiver that rectifies the AC voltage developed across the receiving coil and provides a regulated DC voltage at the output. The 32-bit core MCU is the supervisor of the whole device and manages all the functional blocks to • • • • establish and maintain communication with the transmitter, ensure adherence to Qi standard specifications (wherever required), optimize the efficiency by properly adjusting the operating point guarantee reliability by monitoring and protecting both the load and the device itself. In order to execute the above mentioned (and many others) tasks, the MCU core relies on a resident firmware stored in ROM . In addition, some configuration parameters (e.g. output voltage, FOD tuning parameters, etc.) can be saved in the internal few times programmable Resistive RAM (RRAM) and retrieved at power-up, allowing the STWLC38 to operate as a fully autonomous stand-alone chip. For applications in which the host system directly monitors or controls the power transfer, the I2C interface provides access to the internal registers of the STWLC38. The device is also equipped with three programmable general-purpose I/O pins (GPIOs) to implement specific functions (e.g. driving status LEDs, enabling the output on request, informing the host system about faulty conditions, etc.). Figure below shows the block diagram of the device with simplified interconnections among the functional blocks. The synchronous rectifier converts the AC voltage from the receiving coil into a DC voltage at the VRECT pin. The four switches of the rectifier (that is basically an H-bridge) are controlled by the digital core in order to minimize both conduction and switching losses as a function of the output voltage and current, both monitored by two channels of the ADC. Two bootstrap capacitors are externally connected to the BOOT1-BOOT2 pins to correctly drive the high-side switches of the rectifier. The output of the rectifier, filtered by an external capacitor, is also the input rail for the main LDO linear regulator and for the auxiliary linear regulators in charge of deriving the 1.1 V and 2.5 V supply voltages. The digital core has full control of the main LDO linear regulator in order to manage the output voltage, the output current and the drop-out voltage. Of course the minimization of the drop-out voltage requires a closed loop regulation of the voltage at the VRECT pin, i.e. a feedback information that is sent to the transmitter (via ASK modulation) which, in turn, adjusts the delivered power by acting on the supply voltage, the switching frequency or the switching duty-cycle (or a combination of the three) of its own power stage, depending on the adopted technique. This regulation loop involving the transmitter is an essential part of the wireless power transmission and is extensively described in Qi specifications. STWLC38 is also capable to function as a transmitter to provide power up to 5W. DS14078 - Rev 1 Downloaded from Arrow.com. page 2/63 STWLC38 Block diagram 2 Block diagram Figure 1. Simplified block diagram DS14078 - Rev 1 Downloaded from Arrow.com. page 3/63 STWLC38 Device pin out 3 Device pin out Figure 2. Pin assignment (through top view) A1 VSSP B1 AC2 C1 AC2 D1 VRECT E1 A2 VSSP B2 AC2 C2 AC2 D2 E3 F2 H1 COMB1 D3 E2 F1 G1 C3 BOOT2 VRECT VOUT COMA1 B3 BOOT1 VRECT VOUT NTC A3 IEXT VS G2 COMA2 H2 COMB2 NC F3 GPIO0 G3 GPIO1 H3 GPIO2 A4 A5 VSSP VSSP B4 B5 AC1 AC1 C4 C5 AC1 AC1 D4 VRECT E4 D5 VRECT E5 VAA VSSA F4 F5 VDD VSSD G4 G5 ENB SDA H4 H5 INTB SCL Table 1. Pin description DS14078 - Rev 1 Downloaded from Arrow.com. Pin name Pin location VSSA E5 Analog ground. Power return for the main LDO and the analog circuitry. VSSD F5 Digital ground. Reference for digital input and output signals. VSSP A1, A2, A4, A5 Power ground. Power return for the synchronous rectifier. AC1 B4, B5, C4, C5 AC power input: input of the synchronous rectifier. Connect to RX series resonant circuit. AC2 B1, B2, C1, C2 AC power input: input of the synchronous rectifier. Connect to RX series resonant circuit. BOOT1 B3 Synchronous rectifier bootstrap capacitor connection: a 47 nF (typ.) ceramic capacitor is connected between this pin and AC1. BOOT2 C3 Synchronous rectifier bootstrap capacitor connection: a 47 nF (typ.) ceramic capacitor is connected between this pin and AC2. COMA1 G1 COMA2 G2 Pin function Modulation switches connection: capacitors between COMA1 and AC1 pin and between COMA2 and AC2 pin are used to implement ASK modulation. page 4/63 STWLC38 Device pin out DS14078 - Rev 1 Downloaded from Arrow.com. Pin name Pin location Pin function COMB1 H1 COMB2 H2 VRECT D1, D2, D3,D4, D5 VS F2 ASK de-modulation input; NTC F1 Coil temperature-sensing input: this pin is connected to the center tap of a resistor divider having an NTC in the low-side position. If this function is not used, the pin must be pulled-up to VAA through a 10 kΩ resistor to prevent triggering the coil over-temperature protection. If not used as temperature-sensing pin, it can be used as ADCIN2 sampling input pin VOUT E1,E2 NC E3 Not connected (To be left floating) VDD F4 1.1 V LDO output and supply rail for the digital core, the ADC, and the analog circuitry. Connect a 1 μF filtering capacitor between this pin and ground. VAA E4 2.5 V LDO output and supply rail for the auxiliary circuitry. Connect a 4.7 μF filtering capacitor between this pin and ground. ENB G4 Chip-enable input. If set high, the device is disabled. This pin is eventually used by the host controller to control the power transfer process. Connect to ground if not used. IEXT A3 Internal pull-down switch for active (dissipative) over-voltage clamper: a resistor with adequate power dissipation capability must be connected between this pin and VRECT to damp excessive voltage developing at the output of the rectifier. SCL H5 I2C bus, clock line input. A pull-up resistor to the supply rail of the host controller is required to ensure correct digital levels. SDA G5 I2C bus, data line I/O. A pull-up resistor to the supply rail of the host controller is required to ensure correct digital levels. GPIO0 F3 GPIO1 G3 GPIO2 H3 INTB H4 Auxiliary modulation switches connection: capacitors between COMB1 and AC1 and between COMB2 and AC2 are used to implement additional ASK modulation. These pins are optionally used, in conjunction with COMA1 and COMA2 pins, to modify the ASK modulation index in specific operating conditions. Synchronous rectifier output and input for the main LDO linear regulator. A suitable capacitor between these pins and VSSA ensures residual AC ripple filtering and energy storage for proper load-transient response. Main LDO linear regulator output voltage. Connect a suitable filtering capacitor between these pins and VSSA to ensure stable operation and proper load transient response in all operating conditions. Programmable general-purpose I/Os: the function of these pins depends on the configuration of the device. Interrupt output (active low). Programmable open-drain output used to generate an interrupt on specific events for the host controller. page 5/63 STWLC38 Electrical and thermal specifications 4 Electrical and thermal specifications 4.1 Absolute maximum ratings Stresses beyond those listed in Table 2 may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other condition above those indicated in Table 2 is not implied. Exposure to absolute maximum rated conditions for extended periods may affect device reliability. Table 2. Absolute maximum ratings Parameter Pin(s) Min. Max. AC1, AC2, COMA1, COMA2, COMB1 and COMB2 respect to ground (VSSA, VSSD and VSSP pins) -0.9 20 -0.3 2.75 BOOT1 and BOOT2 respect to ground (VSSA, VSSD and VSSP pins) -0.3 22.5 VRECT, VOUT and IEXT respect to ground (VSSA, VSSD and VSSP pins) -0.9 20 VDD respect to ground (VSSA, VSSD, and VSSP pins) -0.3 1.21 VAA, VS, and NTC respect to ground (VSSA, VSSD, and VSSP pins) -0.3 2.75 GPIO0, GPIO1, GPIO2, INTB, ENB, SDA and SCL respect to ground (VSSA, VSSD, and VSSP pins) -0.3 3.6 Relative voltage between any ground pin (VSSA, VSSD, VSSP) -0.3 0.3 BOOT1 to AC1 BOOT2 to AC2 Pin voltage range RMS pin current 2 COMA1, COMA2, COMB1, COMB2, IEXT 0.5 A 2000 JEDEC JS001-2012 V CDM ESD susceptibility All pins 500 JEDEC JS002-2012 Latch-Up EIA/JESD78E 4.2 V AC1, AC2, VRECT, VOUT HBM ESD susceptibility Unit -200 200 mA Thermal characteristics Table 3. Thermal characteristics Symbol Parameter TA,OP(1) Operating ambient temperature -40 85 TJ,OP Operating junction temperature 0 125 RϴJA(2) Junction to ambient thermal resistance TSHDN Thermal shutdown threshold 125 TSHDN,HYST Thermal shutdown hysteresis 10 Conditions 2s2p Min. Typ. 48 Max. Unit °C °C/W °C 1. TA,OP -40°C to +85°C, limits over the operating range guaranteed by design and characterization, if not otherwise specified. 2. Device mounted on a standard JESD51-5 test board DS14078 - Rev 1 Downloaded from Arrow.com. page 6/63 STWLC38 Electrical characteristics 4.3 Electrical characteristics 0 °C < TA < 85 °C; VVRECT = 5 V to 10 V. Typical values are at TJ = 25 °C, if not otherwise specified. Table 4. Electrical characteristics Symbol Parameter Test Conditions Min. Typ. VRECT Under-Voltage Lock-Out upper (turn-on) threshold VRECT pin voltage, rising edge 2.5 VRECT Under-Voltage Lock-Out lower (turn-off) threshold VRECT pin voltage, falling edge 2.3 VVRECT,MAX VRECT maximum operating supply voltage Voltage on VRECT pin IVOUT,Q VOUT current consumption in shutdown mode ENB High for more than 1 ms, supply voltage (5 V) applied to VOUT 500 ENB low, supply voltage applied to VRECT 5 ENB low, supply voltage applied to VOUT 5 Max. Unit Supply section VVRECT,UVLO IVRECT,OP IVOUT,OP Operating current consumption (not considering the programmed dummyload current) V HOVP setting V μA mA 1.1V supply voltage LDO linear regulator LDO1 output voltage VDD IVDD = 5 mA LDO1 under-voltage lock-out upper threshold 1.05 1.10 1.15 V 0.85 0.9 0.95 V 2.4 2.5 2.6 V 2.0 2.1 2.2 V 20 mA 2.5V supply voltage LDO linear regulator LDO2 output voltage V AA IVAA,EXT IVAA =10 mA LDO2 under-voltage lock-out upper threshold Maximum current allowed for external load Synchronous rectifier Synchronous rectifier switches onresistance low resistance mode (dynamically selected) 50 RDSON,COMMx COMAx-COMBx modulation switches on-resistance VVRECT = 5 V 0.5 ICOMxx,MAX COMAx-COMBx modulation switches current capability RMS value 0.25 RDSON,ACx mΩ ASK modulator 1 Ω A Main LDO linear regulator VOUT_SET=5V Output voltage VOUT Line regulation VOUT Load regulation 4.95 5.0 5.05 V VOUT_SET=12V 0x00B2=49 IVOUT=0.1A VOUT DS14078 - Rev 1 Downloaded from Arrow.com. 0x00B2 = 2D I VOUT=0.1A IVOUT = 0.1 A, VOUT = 5 V, 5.1 V < VVRECT< 12 V VVRECT = 5.5 V, VOUT = 5 V, 1 mA < IVOUT < 1A 11.95 12 12.05 30 50 mV 50 70 mV page 7/63 STWLC38 Electrical characteristics Symbol Parameter VOUT_STEP Programmable step size VDROP Linear regulator drop-out voltage IOUT_CL Linear regulator over current protection Test Conditions Min. IOUT = 1 A Typ. Max. Unit 25 mV 80 mV 1.75 A Thermal protection (external NTC) VNTC,OTP External over-temperature NTC pin upper threshold 0.55 0.59 0.65 V External over-temperature NTC pin hysteresis 50 125 150 mV 1 2 μA INTC,BIAS NTC pin bias current VNTC = 1.5 V Hard OVP (AC1-AC2 short to VSSP) upper threshold HOVP threshold Hard-OVP step size HOVP threshold step size Over-Voltage Protection VVRECT,OVPH SOVP threshold VVRECT,OVPS Soft OVP (IEXT clamping) upper threshold 12 18 9 16 SOVP threshold step size 0.2 Hysteresis 1 IIEXT,MAX IEXT clamping switch current capability Non-repetitive 100 ms rectangular pulse RIEXT,ON IEXT switch on-resistance IIEXT = 250 mA V 2.0 1 V 0.3 A 2 Ω Digital signals VIL Low level input voltage VIH High level input voltage VOH GPIOx high level output voltage Output high, ISOURCE = 2mA 1.4 IOH GPIOx pin current capability Output high 3 VOL Low level output voltage Output low, ISINK=3mA DS14078 - Rev 1 Downloaded from Arrow.com. 0.54 1.26 V mA 0.4 V page 8/63 STWLC38 Recommended operating conditions 4.4 Recommended operating conditions Symbol Parameter Conditions Min. Typ. Max. Unit DC characteristics VVRECT,OP Operating VRECT supply voltage range VVRECT,BPP Operating VRECT supply voltage range in BPP mode 4.5 13 V VVOUT = 5 V, IVOUT = 0.5 A 5.1 5.2 8 AC characteristics 4.5 VACIN AC peak-to-peak voltage between AC1 and AC2 input pins IAC,MAX AC1 and AC2 pins maximum RMS current capability fAC AC synchronous rectifier input frequency range Sinusoidal waveform at AC1-AC2 terminals 100 14 V 1.25 A 800 kHz Typical characteristics Measurements performed at room temperature (25°C) using evaluation boards STEVAL-WBC86 TX (MP-A11a) and STEVAL-WLC38RX (8uH Coil). Figure 3. System efficiency and Thermal Performance 5V,1A 4.6 Start up waveforms This section shows typical waveforms measured on AC1,AC2,VRECT,VOUT pins during receiver power up and ARC mode operation. Figure 4. STWLC38 Power Up and ARC mode waveforms DS14078 - Rev 1 Downloaded from Arrow.com. page 9/63 STWLC38 Device description 5 Device description 5.1 Chip-Enable Pin When Chip-enable pin is set to HIGH , the device is in reset mode. Both rectifier low-side switches are turned-on while high-side switches are turned-off. After releasing the enable pin, STWLC38 can resume normal operational mode. 5.2 Synchronous rectifier The synchronous rectifier of the STWLC38 is a key block in charge of converting the AC input power from the receiving coil into a DC supply rail for the following linear regulator. In principle it consists of four N-channel MOSFETs arranged in an H-bridge, conveniently driven by a control block that monitors the voltage at the AC1 and AC2 pins to optimize the commutations and to charge the external bootstrap capacitors for the high-side switches. Different driving schemes are possible for the switches of the rectifier and the MCU core dynamically selects the optimal one to maximize the overall efficiency as a function of the operating point. When designing the filtering capacitor at the output of the synchronous rectifier, it must be taken into account that it has to minimize the AC residual ripple and to provide energy storage to sustain load transients, without impacting on the ASK communication with the transmitter. 5.3 ASK and FSK communication Robust and reliable in-band ASK modulation is critical to the operation of any Qi compliant devices. STWLC38 has dedicated hardware on top of the firmware algorithm to improve the performance of the in-band communication. STWLC38 allows for two sets of modulation capacitors, namely COMA1/2 and COMB1/2. These 2 sets of ASK communication capacitors can be used in parallel or individually according to the load condition of the device. This allows for high level of flexibility to cater for a wide range of wireless transmitters. STWLC38 comes with an advanced FSK demodulation filter which is able to remove any glitches present in the rectifier input. The filter comes with a programmable masking pulse which is controlled by the firmware. This allows the firmware to adaptively control the filter to cater to different rectifier modes thereby ensuring robust FSK demodulation across the operating range. 5.4 ARC (Adaptive Rectifier Configuration) Mode ARC (Adaptive Rectifier Configuration) mode improves the ping up and power transfer spatial freedom of the system in both X and Y direction. Without any change in hardware or optimization of the coil, the ping up distance is enhanced by up to 50% in all directions by enabling ARC mode. This transforms the whole surface of the Tx to a usable area. Further enhancement is possible by customization of the coil. Coil parameter tolerance requirements are widely relaxed due to ARC mode ping up feature. This is critical to wearables and hearables application where coils are of smaller and thinner dimensions, and it is relatively costlier to keep coil parameters within tight tolerances. 5.5 Protections Over-voltage protection The STWLC38 integrates different Over-Voltage Protection circuits to protect itself, the load connected to its output rail and the external components from damage due to overheating and/or exceeding AMR condition. Under normal operating conditions the voltage at the output of the synchronous rectifier is slightly higher than the output one thanks to the communication with the transmitter. DS14078 - Rev 1 Downloaded from Arrow.com. page 10/63 STWLC38 GPIOx and INTB pins A sudden change in the coupling factor between transmitting and receiving coils, for example due to abrupt reciprocal repositioning of the coils, easily leads to unpredictable voltage peaks at the AC input terminals: the TX-RX regulation loop is not fast enough to prevent such an event and additional precautions must be taken. There are 3 over voltage protections, which are POVP, SOVP and HOVP. • • • POVP (Ping Over Voltage Protection) During power-up when VAA and VDD are lower than UVLO threshold, POVP is triggered when VRECT > 14V, both rectifier low-side switches are turned-on while high-side switches are turned-off. POVP is released when VRECT < 11V. SOVP (Soft over voltage protection) When VRECT > VOUT + SOVP threshold, IEXT switch will be turned-on. SOVP threshold is programmable and can be set by PC GUI tool. SOVP is released when VRECT < SOVP threshold - 1V. HOVP (Hard Over voltage Protection) When VRECT > HOVP threshold, both rectifier low-side switches are turned on while high-side switches are turned-off. HOVP threshold is set by internal register. HOVP is released when VRECT < VOUT + SOVP release threshold, which is SOVP threshold - 1V. Over-temperature protection The STWLC38 is equipped with over-temperature detection circuits based on different sources: • • • Internal temperature sensor external NTC temperature sensor TSHUT (hardware) Over temperature protection(Software) The signals coming from the internal temperature sensors are conditioned and routed to the ADC. The temperature can be monitored in dedicated register. When the temperature exceeds set threshold level , it can turn off Main Voltage regulator (VOUT) , EPT can be sent to TX to stop power transfer. The external sensor (NTC), typically placed very close to the coil to detect the over temperature of the coil , low-sided NTC of a resistor divider whose center tap is connected to the NTC pin(analog input), while the high-side resistor is connected to the VAA pin. The temperature threshold is programmable by GUI. If this function is not used, the pin must be pulled-up to VAA through a 10 kΩ resistor to prevent triggering the coil over-temperature protection. TSHUT comparator monitor die temperature and turns off Main voltage regulator (VOUT) when temperature exceed set threshold level. The temperature threshold is programmable by GUI from 105 °C to 135 °C with 10 °C step (10 °C hysteresis). When TSHUT is triggered both rectifier low-side switches are turned on while high-side switches are turned-off. Over current Protection The current limit is programmable (1.25A, 1.5A, 1.75A, 1.93A) , when output current exceed the set current limit , it can turn off Main Voltage regulator (VOUT) , EPT can be sent to TX to stop power transfer. 5.6 GPIOx and INTB pins The GPIO0 through GPIO2 pins are programmable general-purpose I/O pins whose functions can be assigned in NVM memory. These pins can be configured both as inputs and outputs (either push-pull or open-drain) according to the selected function. The INTB (GPIO3) pin is an interrupt output line that can be associated to any internal interrupt condition and used to inform the host system about specific events. The INTB pin is programmed as open-drain type. 5.7 RRAM (Resistive Random Access Memory) STWLC38 has a 32kB RRAM which allows for multiple erase/re-write cycles. This provides flexibility for custom firmware needed for various applications like proprietary protocols or field firmware upgrades. RRAM also offers design in flexibility during preproduction optimization. RRAM programming can be done in standalone mode, applying 5V (USB-VBUS 5V) to VOUT pin. Using USB-I2C interface to PC GUI tool. DS14078 - Rev 1 Downloaded from Arrow.com. page 11/63 STWLC38 TX Mode 6 TX Mode STWLC38 can be configured to Tx mode, it is capable of delivering output power up to 5W (coil dependent). Input Voltage The device can support wide range of input voltage of 5V up to 12V. The power is applied to VOUT pin (VIN), which is the same VOUT pin when in Receiver Mode Tx Inverter The power transmitter uses a Full Bridge inverter, four N-channel MOSFETs arranged in an H-bridge. The inverter converts the DC input into AC waveform that drives resonant circuit, which consists of Primary coil plus series capacitor. The power transmitted to the coil is regulated by varying the switching frequency of the bridge. A higher the operating frequency (example 200kHZ) for lower transmitted power, while a lower operating frequency (example 110kHZ) for higher transmitted power. ASK Demodulation Using ASK (Amplitude Shift Keying) modulation, the power receiver regularly sends Control error Packets to tune operating point to match Load requirements. Tx receives this modulated signal from AC1 input, the coil signal is conditioned using discrete filter circuit as shown below and fed into VS pin for demodulation. Figure 5. ASK Demodulator Circuit DS14078 - Rev 1 Downloaded from Arrow.com. page 12/63 STWLC38 Wireless power interface 7 Wireless power interface The blocks that refer to the wireless power interface are the synchronous rectifier, the main LDO linear regulator and the ASK modulator, as well as the digital core as supervisor. The power transfer from the transmitter to the receiver is established as a result of a procedure which consists of several distinct stages. The power transfer begins after the transmitter has properly detected a valid receiver and a specific communication has been established between the two parts. Power transfer phases The flow-chart in Figure 6 reports the whole process of power transfer in Baseline Power Profile (BPP up to 1A@5V) Figure 6. Power transfer phases for Baseline Power Profile Apply Power Signal No Response / Abort Digital Ping Ping Extended Digital Ping Selection No Power Transfer Contract / Unexpected Packet / Transmission Error / Timeout Identification & Configuration Power Transfer Contract established Power Transfer Contract Violation / Unexpected Packet / Timeout Power Transfer Power Transfer Complete BPP power transfer phases • Digital ping: this phase is an interrogation session based on a more energetic AC burst during which the potential receiver is expected to reply through amplitude shift-keying (ASK) modulation, the receiver device sends Signal strength packet. • Identification & configuration: this phase is aiming to identify the receiver and to gather information about its power transfer capability. The transmitter generates a so-called “Power Transfer Contract” tailoring some parameters that will characterize the following power transfer phase. Power transfer: this is the final step, where the transmitter initially increases and subsequently modulates the transmitted power in response to the control (feedback) data from the receiver. • The flow-chart in below shows the whole process leading to a power transfer in Extended Power Profile (EPP) up to 1.25A@12V Figure 7. Power transfer phases for Extended Power Profile EPP power transfer phases Without entering the details of the different phases, the basic sequence of events taking place when a receiver is properly placed on the transmitting coil are summarized as: DS14078 - Rev 1 Downloaded from Arrow.com. page 13/63 STWLC38 Wireless power interface • • • • Digital ping: this phase is an interrogation session based on a more energetic AC burst during which the potential receiver is expected to reply through amplitude shift-keying (ASK) modulation, the receiver device sends Signal strength packet. Identification & configuration: this phase is aiming to identify the receiver and to gather information about its power transfer capability. The transmitter generates a so-called “Power Transfer Contract” tailoring some parameters that will characterize the following power transfer phase. Negotiation: in this phase the Power Receiver negotiates with the Power Transmitter to fine tune the Power Transfer Contract. Power transfer: this is the final step, where the transmitter initially increases and subsequently modulates the transmitted power in response to the control (feedback) data from the receiver STWLC38 goes autonomously through Selection, Ping, Identification & Configuration phases, entering Power Transfer phase if no error occurs. During the Power Transfer phase, the device sends Received-Power and Control-Error packets periodically as feedback information for the transmitter. If a critical event like over-voltage, over-current or over-temperature occurs, the STWLC38 automatically sends the End-Power-Transfer packet. When the Power Transfer is up and running, the End-Power-Transfer packet (with any response value) or any custom packet (e.g. Proprietary packet or Charge-Status packet) can be sent to the transmitter simply through commands via I2C interface. Sending a custom packet may result in a reply (either a data packet or a pattern response from the transmitter) or no reply at all: if a response is received, the content is captured and stored in specific I2C registers. Important notes: • • • • DS14078 - Rev 1 Downloaded from Arrow.com. Changing the output voltage must respect the overall system design (selected coil, transmitter type, etc.). Output load transient response strongly depends on a correct design of the output capacitors. Severe load transients may lead to temporary output voltage collapse due to the overall TX-RX response time. A minimal output load significantly helps in increasing the signal-to-noise ratio during digital ping and is advisable to ensure interoperability with all transmitters. For this purpose, the STWLC38 allows the user to set a dummy load (reservoir current) which is dynamically managed to fade-out when an output load is applied. The initial load at power-up should not exceed 2.5 W, smoothly ramping-up to full power subsequently. page 14/63 STWLC38 I2C interface 8 I2C interface The STWLC38 can operate fully independently, i.e. without being interfaced with a host system. In applications in which the STWLC38 has to be a part of peripherals managed by the host system, the two SDA and SCL pins could be connected to the existing I²C bus. The device works as an I²C slave and supports standard (100 kbps) fast (400 kbps) data transfer modes. The STWLC38 has been assigned 0x61 7-bit hardware address. The pins are up to 3.3 V tolerant and the pull-up resistors should be selected as a trade-off between communication speed (lower resistors lead to faster edges) and data integrity (the input logic levels have to be guaranteed to preserve communication reliability). When the bus is idle, both SDA and SCL lines are pulled HIGH. Data Validity The data on the SDA line must be stable during the high period of the clock. The high and low states of the SDA line can only change when the SCL clock signal is low. Start and Stop Conditions Both the SDA and the SCL lines remain high when the I2C bus is not busy. A START condition is a high-to-low transition of the SDA line when SCL is HIGH, while the STOP condition is a low-to-high transition of the SDA line when SCL is HIGH. A STOP condition must be sent before each START condition. Figure 8. Start and Stop Condition on the I2C Bus Byte format Every byte transferred over the SDA line must contain 8 bits. Each byte received by the STWLC38 generally is followed by an acknowledge (ACK) bit. The MSB is transferred first. One data bit is transferred during each clock pulse. The data on the SDA line must remain stable during the high state of each SCL clock pulse. The device generates the ACK pulse (by pulling-down the SDA line during the acknowledge clock pulse) to confirm the correct device address or received data bytes. Interface protocol The interface protocol consists of • • • • • • Start condition (START) 7-bit device address (0x61) + R/W bit (read = 1 / write = 0) Register pointer, high-byte Register pointer, low-byte Data sequence: N x (data byte + ACK) Stop condition (STOP) The register pointer (or address) byte defines the destination register to which the read or write operation applies. When the read or write operation is finished, the register pointer is automatically incremented. Writing to a single register Writing to a single register begins with a START condition followed by device address 0xC2 (7-bit device address plus R/W bit cleared), two bytes of the register pointer and the data byte to be written in the destination register. Each transmitted byte is acknowledged by the STWLC38 through an ACK pulse. DS14078 - Rev 1 Downloaded from Arrow.com. page 15/63 STWLC38 I2C interface Figure 9. Writing to single register byte Writing to multiple registers (page write) The STWLC38 supports writing to multiple registers with auto-incremental addressing. When data is written into a register, the register pointer is automatically incremented, therefore transferring data to a set of subsequent registers (also know as page write) is a straightforward operation. Figure 10. Writing multiple register bytes Reading from a single register Reading from a single register begins with a START condition followed by the device address byte 0xC2 (7-bit device address plus R/W bit cleared) and two bytes of register pointer, then a re-START condition is generated and the device address 0xC3 (7-bit device address plus R/W bit asserted) is sent, followed by data reading. ACK pulse is generated by the STWLC38 at the end of each byte, but not for data bytes retrieved from the register. A STOP condition is finally generated to terminate the operation. Figure 11. Reading single register byte DS14078 - Rev 1 Downloaded from Arrow.com. page 16/63 STWLC38 I2C interface Reading from multiple registers (page reading) Similarly to multiple (page) writing, reading from subsequent registers relies on an auto-increment of the register: the master can extend data reading to the following registers by generating and an ACK pulse at the end of each byte. Data reading starts immediately and the stream is terminated by a NMAK pulse at the end of the last data byte, followed by a STOP condition. Figure 12. Reading multiple bytes DS14078 - Rev 1 Downloaded from Arrow.com. page 17/63 STWLC38 I2C register map 9 I2C register map The STWLC38 can be monitored and controlled by accessing the internal registers via I2C interface. The following registers map reports the accessible addresses. Addresses not shown in the map and blank bits have to be considered reserved and not altered as well. These CFG parameters are accessible using the GUI tool, a new memh file needs to be generated after customized changes and to be Programmed in to NVM. Table 5. Register abbreviations Register type Description R/W can read and write the bits R can read only W can write only CFG For customizing Configuration, accessible through GUI only. Table 6. Chip information Address Register name R/W Default Description 0x0000 Chip ID [Byte 0] R 0x26 Chip ID [7..0] 0x0001 Chip ID [Byte 1] R 0x00 Chip ID [15..8] 0x0002 Chip revision R 0x03 Chip revision [7..0] 0x0003 Customer ID R 0x00 Customer ID [7..0] 0x0004 ROM ID [Byte 0] R 0x61 ROM ID [7..0] 0x0005 ROM ID[Byte 1] R 0x00 ROM ID [15..8] 0x0006 NVM Patch ID[Byte 0] R - NVM patch ID [7..0] 0x0007 NVM Patch ID[Byte 1] R - NVM patch ID [15..8] 0x0008 RAM patch ID[Byte 0] R - RAM patch ID [7..0] 0x0009 RAM patch ID[Byte 1] R - RAM patch ID [15..8] 0x000A Configuration ID[Byte 0] R - Configuration ID [7..0] 0x000B Configuration ID[Byte 1] R - Configuration ID [15..8] 0x000C Production ID[Byte 0] R 0x07 PE ID [7..0] 0x000D Production ID[Byte 1] R 0x00 PE ID [15..8] 0x000E Operation mode R 0x02 0x1: Standalone (debug) mode 0x2: Qi RX mode 0x3: Qi TX mode 0x0010 ..0x001F Device ID[Bytes 0 ..15] R - Device ID Bytes 0 ...15 Table 7. System information DS14078 - Rev 1 Downloaded from Arrow.com. Address Register name R/W Default 0x0020 System command[Byte 0] RW - Description Bit 0: Switch to TX command Write 1 to switch to Qi TX mode page 18/63 STWLC38 I2C register map Address Register name R/W Default 0x0020 System command[Byte 0] - - R - Description Bit 1..7 Reserved Bit 0: Core hard fault error 0: No hard fault error detected 1: Hard fault error detected Bit 1: HW WDT trigger latch R 0x002C - 0: HW WDT not triggered 1: HW WDT triggered System error information [Byte 0] Bit 2: NVM IP error R - 0: No NVM IP error detected 1: NVM IP error detected Bit 3: Reserved R - Bit 4: NVM Boot error Bit 5..7 : Reserved Bit [1..0] NVM PE error 0: No error R - 1: Section header error 2: Section CRC failed 3: Reserved Bit [3..2] NVM Configuration error 0: No error R - 1: Section header error 2: Section CRC failed 3: Reserved 0x002D System error [Byte 1] Bit [5..4] NVM Patch error 0: No error R - 1: Section header error 2: Section CRC failed 3: Reserved Bits [7..6] NVM Production Information error 0: No error R - 1: Section header error 2: Section CRC failed 3: Reserved R 0x002E System error[Byte 2] R - Reserved 0x002F System error[Byte 3] R - Reserved Table 8. Communication Address 0x00D8 0x00D9 0x00DA DS14078 - Rev 1 Downloaded from Arrow.com. Register name R/W Default RX DTS SEND LEN Byte 0,1 RW - RX DTS SEND RQ Byte2 RW - Description DTS ADS number of data bytes in stream Byte 0 [7..0] Byte 1 [7..0] Send ADC request Byte 2 Bits [4..0] page 19/63 STWLC38 I2C register map Address Register name R/W Default Description Bits[5..7] Reserved 0x00DC RX DTS RCV LEN Byte 0 ,1 RW - 0x00DE DTS RCV RQ[Byte 3] R - 0x0090 RX SEND DTS R 0x0200 ..0 x27F DTS SEND RW - 0x0280 ..0 x2FF DTS RECV R - 0x00DD DTS ADS number of bytes in stream received Byte 0 [7..0] Byte 1 [7..0] Received ADC request Bits [4..0] Bits[5..7] Reserved Bit 5 : Start sending DTS transaction , DTS send register specify the data to be send Total number of bytes can be sent 128. First 11Bytes shown in GUI Total number of bytes can be received 128. First 11Bytes shown in GUI Table 9. Commands Address Register name R/W Default 0x0020 Command RW - Description SWITCH TO TX Bit 0: Switch to TX command Write 1 to switch to Qi TX mode Table 10. Mode monitor Address 0x0092 0x0093 0x0094 0x0095 0x0096 0x0097 0x0098 0xx099 0x009A 0x009B 0x009C 0x009D 0x00A4 Register name R/W Default VRECT [Byte 0..1] R - VOUT[Byte 0..1] R - ICUR[Byte 0..1] R - TMEAS[Byte 0..1] R - OP FREQ[Byte 0..1] R - NTC [Byte 0 ..1] R - RX VOLT DIFF [Byte 0..1] - 0x00A5 0x00A6 0x00A7 0x00A8 0x00A9 DS14078 - Rev 1 Downloaded from Arrow.com. Description Rectifier voltage in mV [7..0] [15..8] Main LDO Voltage output in mV [7..0] Main LDO Voltage output in mV [15..8] Output current in mA [7..0] [15..8] Chip temperature in deg C [7..0] [15..8] Operating frequency in kHz [7..0] [15..8] NTC temperature measurement [7..0] [15..8] Control Error: Rx voltage difference target and measured VRECT in mV [7..0] [15..8] POWER RX[Byte 0..1] SIG STREN[Byte0..1] R - R - RX received power in mW [7..0] [15..8] Signal strength measured in Rx [7..0] [15..8] POWER TX CFG Power transferred to RX RX NEG STATE CFG Qi Power transfer Indicates BPP or EPP power transfer page 20/63 STWLC38 I2C register map Address Register name R/W Default Description 0x012A TX DUTY R TX POWER RPP CFG Last value sent in Received Power Packet TX RECENT CEP CFG Last CEP value received from RX TX operating duty cycle [7..0] Table 11. GPIO Address Register name R/W Default Description 0x30 GPIO0 Func RW - Please refer to GPIO configuration description. 0x31 GPIO1 Func RW - Please refer to GPIO configuration description. 0x32 GPIO2 Func RW - Please refer to GPIO configuration description. 0x33 GPIO3 Func RW Interrupt pin - INTB GPIO configuration - alternate functions • • • • • • • • • • • • • • • 0x00: GPIO configured as Input , FLOATING (Default) 0x01: GPIO configured as Input , Pull up resistor to internal 1.8V. 0x02: GPIO configured as Input ,Pull down resistor to Internal Ground. 0x03:GPIO configured as Interrupt pin , Open Drain output. 0x04:GPIO configured as Interrupt pin , Push pull output. 0x05:Initialization complete, FW ready (Active High). 0x06: Input to turn-off Main LDO block (Active High). 0x07:Input to Disable ASK communication (Active High). 0x0B: Input to Disable RX_POWEROUT after Negotiation- Push pull (Active High). 0x0C: Input to Disable RX_POWEROUT after Negotiation- Push pull (Active Low). 0x0D:Input to Disable RX_POWEROUT after Negotiation- Open Drain. 0x29: GPIO configured as Output , Open Drain (Active Low). 0x2A:GPIO configured as Output , Open Drain (Active High). 0x2B: GPIO configured as Output , Push pull (Active Low). 0x2C:GPIO configured as Output , Push pull (Active High). Receiver mode (Rx) registers Table 12. RX interrupts enable Address Register name R/W Default Description Bit 0:RX OVTP EN RW - over temperature protection enable 0: disable 1: enable Bit 1: RX OCP EN 0x0080 RX Interrupt Enable[Byte 0] RW - over current protection enable 0: disable 1: enable Bit 2:RX OVP EN RW - over voltage protection enable 0: disable 1: enable DS14078 - Rev 1 Downloaded from Arrow.com. page 21/63 STWLC38 I2C register map Address Register name R/W Default Description Bit 3: RX SYS ERROR EN RW - system error enable 0: disable 1: enable RW - Bit4:Reserved Bit5: RX MSG RCVD EN RW 0x0080 - RX Interrupt Enable[Byte 0] message received from TX enable 0: disable 1: enable Bit6: RX OUTPUT ON EN RW - output on interrupt enable 0: disable 1: enable Bit7: RX OUTPUT OFF EN RW - Output off interrupt enable 0: disable 1: enable Bit0: RX SENT PACKET EN RW - Packet sent interrupt enable 0: disable 1: enable Bit1:RX SENT PKT TO EN RW - Packet sending timeout interrupt enable 0: disable 1: enable Bit2:RX SIG STR EN 0x0081 RX Interrupt Enable[Byte 1] RW - Signal Strength sent interrupt enable 0: disable 1: enable Bit3:RX VRECT RDY EN RW - VRECT ready interrupt enable 0: disable 1: enable Bit4:RX UVLO EN RW - under voltage protection interrupt enable 0: disable 1: enable Bit5,6,7: RESERVED Bit0:RX DTS SEND SUCCESS EN RW 0x0082 RX Interrupt Enable[Byte 2] DTS sending data stream successfully interrupt enable 0: disable 1: enable RW DS14078 - Rev 1 Downloaded from Arrow.com. - - Bit1: RX DTS SEND TO END EN DTS stopped sending due to timeout error interrupt enable page 22/63 STWLC38 I2C register map Address Register name R/W Default Description 0: disable 1: enable Bit2 : RX DTS SEND RESET END EN RW - DTS stopped due to reset interrupt enable 0: disable 1: enable RW - Bit3: RESERVED Bit4:RX DTS RCVD SUCCESS EN RW 0x0082 - RX Interrupt Enable[Byte 2] DTS received data stream successful interrupt enable 0: disable 1: enable Bit 5:RX DTS RCVD TO END EN RW - DTS stopped receiving due to timeout error interrupt enable 0: disable 1: enable Bit6:RX DTS RCVD RESET END EN DTS stopped receiving due to reset interrupt enable 0: disable 1: enable 0x0083 RX Interrupt Enable[Byte 3] - - Bit 7: Reserved - - Reserved Table 13. RX interrupt Clear Address Register name R/W Default R - Description Bit 0:RX OVTP CLR Over temperature protection clear 1: clear Bit 1:RX OCP CLR R - Over current protection clear 1: clear Bit 2:RX OVP CLR R 0x0084 - Over voltage protection clear 1: clear RX interrupt Clear[Byte 0] Bit 3:RX SYS ERROR CLR R - system error clear 1: clear R - R - Bit 4: Reserved Bit5:RX MSG RCVD CLR message received from TX clear 1: clear R DS14078 - Rev 1 Downloaded from Arrow.com. - Bit6:RX OUTPUT ON CLR Output on interrupt clear page 23/63 STWLC38 I2C register map Address Register name R/W Default Description 1: clear 0x0084 RX interrupt Clear[Byte 0] Bit7: RX OUTPUT OFF CLR R - Output off interrupt clear 1: clear Bit0:RX SENT PACKET CLR R - Packet sent interrupt clear 1: clear Bit1:RX SENT PKT TO CLR R - Packet sending timeout interrupt clear 1: clear Bit2:RX SIG STR CLR 0x0085 RX interrupt Clear[Byte 1] R - Signal Strength sent interrupt clear 1: clear Bit3:RX VRECT RDY CLR R - VRECT ready interrupt clear 1: clear Bit4: RX UVLO CLR R -- under voltage protection interrupt clear 1: clear R - Bit5,6,7: RESERVED Bit0:RX DTS SEND SUCCESS CLR R - DTS sending data stream successfully interrupt clear 1: clear Bit1:RX DTS SEND TO END CLR R - DTS stopped sending due to timeout error interrupt clear 1: clear Bit2:RX DTS SEND RESET END CLR R - DTS stopped due to reset interrupt clear 1: clear 0x0086 RX interrupt Clear[Byte 2] R - R - Bit3: RESERVED Bit4: RX DTS RCVD SUCCESS CLR DTS received data stream successful interrupt clear 1: clear Bit5:RX DTS RCVD TO END CLR R - DTS stopped receiving due to timeout error interrupt clear 1: clear Bit6:RX DTS RCVD RESET END CLR R - DTS stopped sending due to reset interrupt clear 1: clear 0x0087 DS14078 - Rev 1 Downloaded from Arrow.com. RX interrupt Clear[Byte 3] - - Bit7: Reserved - - Reserved page 24/63 STWLC38 I2C register map Table 14. RX interrupt latch Address 0x0088 0x0089 0x008A 0x008B DS14078 - Rev 1 Downloaded from Arrow.com. Register name RX interrupt latch[Byte 0] RX interrupt latch[Byte 1] RX interrupt latch[Byte 2] RX interrupt latch[Byte 3] R/W Default Description R - R - R - R - R - R - R - R - R - R - R - R - R - R - R - R - R - R - R - R - R - - - Bit 7 : Reserved - - Reserved Bit 0:RX OVTP LTCH over temperature protection latch Bit 1: RX OCP LTCH over current protection latch Bit 2: RX OVP LTCH over voltage protection latch Bit 3:RX SYS ERROR LTCH system error latch Bit4: Reserved Bit5:RX MSG RCVD LTCH message received from TX latch Bit6:RX OUTPUT ON LTCH Output on interrupt latch Bit7: RX OUTPUT OFF LTCH Output off interrupt latch Bit0:RX SENT PACKET LTCH Packet sent interrupt latch Bit1:RX SENT PKT TO LTCH Packet sending timeout interrupt latch Bit2:RX SIG STR LTCH Signal Strength sent interrupt latch Bit3:RX VRECT RDY LTCH VRECT ready interrupt latch Bit4:RX UVLO LTCH under voltage protection interrupt latch Bit5,6,7: RESERVED Bit0:RX DTS SEND SUCCESS LTCH DTS sending data stream successfully interrupt latch Bit1:RX DTS SEND TO END LTCH DTS stopped sending due to timeout error interrupt latch Bit2:RX DTS SEND RESET END LTCH DTS stopped due to reset interrupt latch Bit3: RESERVED Bit4:RX DTS RCVD SUCCESS LTCH DTS received data stream successful interrupt latch Bit 5:RX DTS RCVD TO END LTCH DTS stopped receiving due to timeout error interrupt latch Bit6:RX DTS RCVD RESET END LTCH DTS stopped sending due to reset interrupt latch page 25/63 STWLC38 I2C register map Table 15. RX interrupt status Address 0x008C Register name RX interrupt status[Byte 0] R/W Default R - R - R - R - R - R - R - R - R - Description Bit 0: RX OVTP STAT over temperature protection status Bit 1:RX OCP STAT over current protection status Bit 2:RX OVP STAT over voltage protection status Bit 3:RX SYS ERROR STAT system error status Bit4:Reserved Bit5:RX MSG RCVD STAT message received from TX status Bit6:RX OUTPUT ON STAT Output on interrupt status Bit7:RX OUTPUT OFF STAT Output off interrupt status Bit0: RX SENT PACKET STAT Packet sent interrupt status Bit1:RX SENT PKT TO STAT R 0x008D RX interrupt status[Byte 1] Packet sending timeout interrupt status R - R - R - R 0x008E 0x008F DS14078 - Rev 1 Downloaded from Arrow.com. RX interrupt status[Byte 3] Signal Strength sent interrupt status Bit3:RX VRECT RDY STAT VRECT ready interrupt status Bit4: RX UVLO STAT under voltage protection interrupt status Bit5,6,7: RESERVED R - R - R - RX interrupt status[Byte 2] Bit2:RX SIG STR STAT Bit0:RX DTS SEND SUCCESS STAT DTS sending data stream successfully interrupt status Bit1:RX DTS SEND TO END STAT DTS stopped sending due to timeout error interrupt status Bit2:RX DTS SEND RESET END STAT DTS stopped due to reset interrupt status Bit3: RESERVED Bit4:RX DTS RCVD SUCCESS STAT R - R - R - - - Bit7: Reserved - - Reserved DTS received data stream successful interrupt status Bit 5:RX DTS RCVD TO END STAT DTS stopped receiving due to timeout error interrupt status Bit6:RX DTS RCVD RESET END STAT DTS stopped sending due to reset interrupt status page 26/63 STWLC38 I2C register map Table 16. RX commands Register address Register name R/W Default Description - RX EPT MSG - EPT reason to be included when sending EPT packet 0x0 : EPT/nul - use if none of the other codes is appropriate. 0x1: EPT/cc charge complete; use to indicate that the battery is full. 0x2: EPT/if internal fault; use if an internal logic error has been encountered. 0x3: EPT/ot over temperature, use if (e.g.) the battery temperature exceeds a limit. 0x4: EPT/ov 0x00CF RW over voltage; use if a voltage exceeds a limit. 0x5: EPT/oc over current; use if the current exceeds a limit. 0x6: EPT/bf battery failure: use if the battery cannot be charged. - RX command 0x8:EPT/nr no response: use if the target operating point cannot be reached. 0xA:EPT/an aborted negotiation: use if a suitable Power Transfer Contract cannot be negotiated. 0xB: EPT/rst restart; use to restart the power transfer Bit0: RX VOUT ON RW - Turn on the VOUT. If both VOUT_ON and VOUT_OFF are set to 1, this command is ignored and both requests are cleared. Bit1: RX VOUT OFF 0x0090 RW - Turn off the VOUT. If both VOUT_ON and VOUT_OFF are set to 1, this command is ignored and both requests are cleared. RW - - - Bit4:RX SEND EPT Send End of Power Packet to TX Bits [3,5,6,7] Reserve Table 17. RX Configuration Address Register name R/W Default Description Bits [7..0] RX VOUT_SET Low 0x00B1 RX BPP VOUT SET[Byte 0] RW - Bits [7..6] lower 2 bits of VOUT set 00 : 0mV 01:25mV DS14078 - Rev 1 Downloaded from Arrow.com. page 27/63 STWLC38 I2C register map Address Register name R/W Default Description 10:50mV 11 : 75mV Bits [5..0] Reserved Bits [7..0] RX VOUT_SET High 0x00B2 RX BPP VOUT SET[Byte 1] RW - Program VOUT output voltage 0.5V to 13.2V, step size 0.1V, step0 --> 0.5V 1 --> 0.6V..5 --> 1.0V.. 15 --> 2.0V.. 45 --> 5.0V.. 73 --> 12V Bits [7..0] RX VOUT_SET Low Bits [7..6] lower 2 bits of VOUT set 00 : 0mV RX EPP VOUT SET[Byte 0] CFG - 01:25mV 10:50mV 11 : 75mV Bits [5..0] Reserved Bits [7..0] RX VOUT_SET High RX EPP VOUT SET[Byte 1] CFG - Program VOUT output voltage 0.5V to 13.2V, step size 0.1V , step0 --> 0.5V 1 --> 0.6V..5 --> 1.0V.. 15 --> 2.0V.. 45 --> 5.0V.. 73 --> 12V Bit[7..5]:RX ILOAD BALAST ILOAD ballast mode current RX Dummy LOAD configuration CFG - 00:8mA 01:16mA 10:24mA 11:32mA Bit[7..0]:RX ARC THRES ARC mode auto off VRECT threshold RX ARC Mode configuration CFG 0x3C steps of 10mV Default : 0x3C --> 6V Maximum : 0x82 --> 13V RX VOUT configuration[Byte1] CFG - Bit 7:RX IVL EN Enable Input voltage loop Bit [4..0]:RX IVL THRES RX VOUT configuration[Byte2] CFG - IVL threshold setting u = 0 .. 15 steps 3V +u * 0.5 RX VOUT configuration[Byte1] CFG - Bit 4:RX UVLO EN VRECT UVLO detection enable Bit [3..0]:RX UVLO THRES RX VOUT configuration[Byte1] CFG - VRECT UVLO Threshold setting u = 0 .. 15 steps 3.5V + u*0.5 Bit0:RX VOUT AUTO EN DS14078 - Rev 1 Downloaded from Arrow.com. RX VOUT configuration CFG - Allow VOUT turn on when no feature is blocking it. If disabled, VOUT must be enabled manually by I2C command RX VOUT configuration CFG - Bit[7..0]:RX VRECT RDY THRES page 28/63 STWLC38 I2C register map Address Register name R/W Default Description VRECT must be higher by this value. Otherwise VOUT cannot be enabled Example : VOUT SET = 5V ; 0x00B2 = 2D ; 0x00B1 [7..6] = 00 VOUT SET = 5.075V ; 0x00B2 = 2D; 0x00B1[7..6] = 11 Table 18. RX LDO configuration Address Register name R/W Default Description 0x00C8 RX LDO DROP 0 RW - Bits[7..0] LDO target voltage drop at 0mA IOUT. Specified in 16mV units. Set point 0 0x00C9 RX LDO DROP 1 RW - Bits[7..0] LDO target voltage drop at ldo_cur_thres1 IOUT. Specified in 16mV units. Set point 1 0x00CA RX LDO DROP 2 RW - Bits [7..0] LDO target voltage drop at ldo_cur_thres2 IOUT. Specified in 16mV units. set point 2 0x00CB RX LDO DROP 3 RW - Bits [7..0] LDO target voltage drop at ldo_cur_thres3 IOUT. Specified in 16mV units. set point 3 0x00CC RX LDO CUR TH1 RW - Bits [7..0] LDO voltage drop IOUT current threshold 1. Specified in 8mA units. 0x00CD RX LDO CUR TH2 RW - Bits [7..0] LDO voltage drop IOUT current threshold 2. Specified in 8mA units. 0x00CE RX LDO CUR TH3 RW - Bits [7..0] LDO voltage drop IOUT current threshold 3. Specified in 8mA units. Table 19. RX BPP FOD configuration Address DS14078 - Rev 1 Downloaded from Arrow.com. Register name R/W Default Description RX BPP FOD CUR THR1 CFG - Bits [7..0] FOD current threshold 1, in units of 10mA. RX BPP FOD CUR THR2 CFG - Bits [7..0] FOD current threshold 2, in units of 10mA. RX BPP FOD CUR THR3 CFG - Bits [7..0] FOD current threshold 3, in units of 10mA. RX BPP FOD CUR THR4 CFG - Bits [7..0] FOD current threshold 4, in units of 10mA. RX BPP FOD CUR THR5 CFG - Bits [7..0] FOD current threshold 5, in units of 10mA. RX BPP FOD OFFSET 0 CFG - Bits [7..0] FOD offset at current 0, in units of 8mW. RX BPP FOD OFFSET 1 CFG - Bits [7..0] FOD offset at current 1, in units of 8mW. RX BPP FOD OFFSET 2 CFG - Bits [7..0] FOD offset at current 2, in units of 8mW. RX BPP FOD OFFSET 3 CFG - Bits [7..0] FOD offset at current 3, in units of 8mW. RX BPP FOD OFFSET 4 CFG - Bits [7..0] FOD offset at current 4, in units of 8mW. RX BPP FOD OFFSET 5 CFG - Bits [7..0] FOD offset at current 5, in units of 8mW. RX BPP FOD RSER CFG - Bits [7..0] Coil series resistance, in units of 4mOhm. page 29/63 STWLC38 I2C register map Table 20. RX EPP FOD configuration Address Register name R/W Default Description RX EPP FOD CUR THR1 CFG - Bits [7..0] EPP FOD current threshold 1, in units of 10mA. RX EPP FOD CUR THR2 CFG - Bits [7..0] EPP FOD current threshold 2, in units of 10mA. RX EPP FOD CUR THR3 CFG - Bits [7..0] EPP FOD current threshold 3, in units of 10mA. RX EPP FOD CUR THR4 CFG - Bits [7..0] EPP FOD current threshold 4, in units of 10mA. RX EPP FOD CUR THR5 CFG - Bits [7..0] EPP FOD current threshold 5, in units of 10mA. RX EPP FOD OFFSET 0 CFG - Bits [7..0] EPP FOD offset at current 0, in units of 8mW. RX EPP FOD OFFSET 1 CFG - Bits [7..0] EPP FOD offset at current 1, in units of 8mW. RX EPP FOD OFFSET 2 CFG - Bits [7..0] EPP FOD offset at current 2, in units of 8mW. RX EPP FOD OFFSET 3 CFG - Bits [7..0] EPP FOD offset at current 3, in units of 8mW. RX EPP FOD OFFSET 4 CFG - Bits [7..0] EPP FOD offset at current 4, in units of 8mW. RX EPP FOD OFFSET 5 CFG - Bits [7..0] EPP FOD offset at current 5, in units of 8mW. RX BPP FOD RSER CFG - Bits [7..0] Coil series resistance, in units of 4mOhm. Table 21. RX protections Address Register name R/W Default Description Bit 0: RX ADC OVTP EN PROT - Enable to compare chip temperature against VTMEAS threshold. AC1/2 will be shorted to ground. Bit1 : Reserved Bit2:RX ADC NTC EN PROT RX protections[Byte 0] CFG - Enable to compare NTC temperature against NTC threshold. If enabled, interrupt status and latch OVTP_INTR are updated on threshold reach. Bit3:RX TSHUT EN PROT - Enable to compare temperature against TSHUT threshold. AC1/2 will be shorted to ground - Bit4: Reserved Bits [5..7] Reserved Bit0: RX ADC OVP EN PROT - Enable to compare VRECT voltage against OVP threshold. If enabled, interrupt status and latch OVP_INTR are updated on threshold reach. Bit1: Reserved RX Protections [Byte 1] Bit 2:RX SOVP EN PROT Enable to compare VRECT against SOVP threshold. Bit [3..4] Reserved CFG Bit5:RX SCP EN PROT - Enable VOUT short detection. If enabled, interrupt status and latch OVP_SCP are updated on detection. Bit 6:RX UVLO EN PROT DS14078 - Rev 1 Downloaded from Arrow.com. - Under voltage protection. Enable to compare voltage against UVLO threshold. If enabled, interrupt status and latch UVLO_INTR are updated on threshold reach. - Bit7:Reserved page 30/63 STWLC38 I2C register map Address Register name R/W Default Description Bit0:RX ADC OCP EN PROT - RX Protections [Byte 2] CFG Enable to compare current against OCP threshold. If enabled, interrupt status and latch OCP_INTR are updated on threshold reach. Bit1:RX OCP EN PROT - Enable to compare VOUT current against current threshold. Interrupt status and latch OCP_INTR are updated on threshold reach. Bits[2..7] Reserved RX Protections [Byte 3] Reserved Bit0:RX ADC OVTP EPT - Send EPT when OVTP ADC threshold is reached. RX OVTP ADC EN PROT must be enabled for this to work. - Bit1: Reserved Bit2:RX ADC NTC EPT RX Protections (EPT) [Byte 0] CFG - Send EPT when NTC ADC threshold is reached. RX NTC ADC EN PROT must be enabled for this to work. Bit3:RX TSHUT EPT - Send EPT when TSHUT threshold is reached. RX TSHUT EN PROT must be enabled for this to work. Bits[4..7] Reserved RX ADC OVP EPT - Bit0 Send EPT when OVP ADC threshold is reached. RX OVP ADC EN PROT must be enabled for this to work. Bit 1 : Reserved Bit2: RX SOVP EPT Send EPT when SOVP threshold is reached. RX SOVP EN PROT must be enabled for this to work. Bit4: Reserved RX Protections (EPT) [Byte 1] CFG Bit4:RX SCP EPT - Send EPT when VOUT short is detected. RX SCP EN PROT must be enabled for this to work. Bit5:RX UVLO EPT - Send EPT when UVLO threshold is reached. RX UVLO EN PROT must be enabled for this to work. - Bit6: Reserved Bit7:RX HOVP EPT - Send EPT when HOVP threshold is reached. RX HOVP PROT must be enabled for this to work. Bit0:RX ADC OCP EPT RX Protections (EPT) [Byte 2] CFG Send EPT when OCP ADC threshold is reached. RX OCP ADC EN PROT must be enabled for this to work. Bit1:RX OC EPT - Send EPT when OCP threshold is reached. RX OCP EN PROT must be enabled for this to work. Bits[2..7] Reserved RX Protections (EPT) [Byte 3] DS14078 - Rev 1 Downloaded from Arrow.com. Reserved page 31/63 STWLC38 I2C register map Address Register name R/W Default CFG - Description Bit0:RX ADC OVTP VOUT OFF Turns VOUT OFF when OVTP ADC threshold is reached. RX OVTP ADC EN PROT must be enabled for this to work. Bit1: Reserved Bit2:RX ADC NTC VOUT OFF RX Protection (VOUT)[Byte 0] CFG - CFG - Turns VOUT OFF when TSHUT threshold is reached. RX TSHUT EN PROT must be enabled for this to work. CFG - Bit4:Reserved - - Bits[5..7] Reserved CFG - Turns VOUT OFF when NTC ADC threshold is reached. RX NTC ADC EN PROT must be enabled for this to work. Bit3:RX TSHUT VOUT OFF Bit0:RX ADC OVP VOUT OFF Turns VOUT OFF when OVP ADC threshold is reached. RX OVP ADC EN PROT must be enabled for this to work. Bit1 : Reserved Bit2:RX SOVP VOUT OFF CFG - Turns VOUT OFF when SOVP threshold is reached. RX SOVP EN PROT must be enabled for this to work. Bits3: Reserved RX Protection (VOUT)[Byte 1] Bit4:RX SCP VOUT OFF CFG - CFG - Turns VOUT OFF when UVLO threshold is reached. RX UVLO EN PROT must be enabled for this to work. - - Bit6: Reserved CFG - Turns VOUT OFF when VOUT short is detected. RX SCP EN PROT must be enabled for this to work. Bit5:RX UVLO VOUT OFF Bit7:RX HOVP VOUT OFF Turns VOUT OFF when HOVP threshold is reached. RX HOVP EN PROT must be enabled for this to work. Bit0:RX ADC OCP VOUT OFF RX Protection (VOUT)[Byte 2] CFG Turns VOUT OFF when OCP ADC threshold is reached. RX OCP ADC EN PROT must be enabled for this to work. Bit1:RX OCP VOUT OFF - Turns VOUT OFF when OCP threshold is reached. RX OCP EN PROT must be enabled for this to work. Bits [2..7] Reserved RX Protection (VOUT)[Byte 3] CFG - Bits [7..0] Reserved Table 22. RX Power transfer contract DS14078 - Rev 1 Downloaded from Arrow.com. Address Register name 0x00AA Rx Power Transfer Contract [Byte 0] 0x00AB Rx Power Transfer Contract [Byte 1] R/W Default Description Bits[7..0] Reserved Bit[5..0]:RX MAX POWER RW - Qi 1.3 Reference Power Field. This value should be 2x of power in watt. Qi spec max is 63/2 watt. page 32/63 STWLC38 I2C register map Address Register name R/W Default 0x00AB Rx Power Transfer Contract [Byte 1] Description RW - Bits[6..7] Reserved - Bits[3..0] Reserved Bit4:RX OB - Qi Power transfer contract. Out-of-band communications functionality. 1: supported Rx Power Transfer Contract [Byte 2] 0: not supported CFG - Bit5 :Reserved Bit6:RX AI - Qi Power transfer contract. Authentication functionality . 1: supported 0: not supported - Bit 7 Reserved Bit[2..0]:RX WIN OFFSET CFG - CFG - Rx Power Transfer Contract [Byte 3] Received Power window offset. Specified in units of 4ms. Keep default value (changing requires system level review). Bit[7..3]:RX WIN SIZE Received Power window size. Specified in units of 4ms. Keep default value (changing requires system level review). Bit0:RX DUP Qi Power transfer contract. Simultaneous incoming and outgoing data streams. CFG 1: supported 0: not supported Bit [3..1]:RX BUF SIZE Qi Power Transfer Contract. The size of the transport-layer buffer for receiving a data transport stream. The number of bytes in the buffer is equal to 16*2^n, with n the value contained in the Buffer Size field.\n Range 16 to 2048 bytes. CFG Bit[5..4]:RX FSK MOD DEPTH Rx Power Transfer Contract [Byte 4] Qi Power Transfer contract. FSK modulation depth. The value is 1/fmod - 1/fop in ns. Depends on configured fsk polarity. Stated as MINIMUM~MAXIMUM (for positive polarity)/MINIMUM~MAXIMUM (for negative polarity) CFG Bit6:RX POL CFG - Qi Power transfer contract. The requested FSK polarity is positive (ZERO) or negative (ONE). Bit7:RX NEG CFG - Qi Power transfer contract. The Extended Protocol is supported (ONE) or not supported (ZERO). If the Neg bit is set to ZERO, all bits of the AI, OB, Pol, and Depth fields shall be set to ZERO as well. Table 23. RX configuration Qi Address DS14078 - Rev 1 Downloaded from Arrow.com. Register name R/W Default RX configuration Qi CFG - Description Bit[7..0]:RX BPP FOD QF page 33/63 STWLC38 I2C register map Address Register name R/W Default Description Reference Quality factor which will be sent during negotiation in FOD/qf packet. Determination of this value is defined in Qi specification Bit[7..0]:RX BPP FOD RF Reference Resonance frequency which will be sent during negotiation in FOD/rf packet. Determination of this value is defined in Qi specification. CFG - CFG - CFG - - - CFG - Number of bytes in each DTS transaction. DTS ADT packet message length for outgoing stream. - - Bits[7..3] Reserved CFG - CFG - CFG - CFG - CFG - - - CFG - Bit[2..0]:RX CE DENOM Control error denominator. Value is set value +1 Bit[5..3]:RX CE NUM Control error numerator. Value is set value +1 Bits[7..6] : Reserved Bit[2..0]:RX DTS PKT LEN RX configuration Qi Bit[6..0]:RX CE MAX Maximal abs value of control error. 0 = no limitation. Bit6:RX RP24 REPLY RP24 request FSK reply Bit7:RX RP24 NACK LDO OFF Turn off LDO automatically when TX send NACK to RP24 Bit[2..0]:RX SS DENOM Signal strength denominator. Value is set value +1 Bit[5..3]:RX SS NUM Signal strength numerator. Value is set value +1 Bit [7..6] Reserved Bit[7..0]:RX SS MIN Minimal value of signal strength Table 24. RX ASK configuration Address Register name R/W Default Description Bit [7..0] RX ASK MOD IOUT THRES CFG 120mA Setting current threshold to switch ASK modulation capacitors Step size 8mA Bit[7..0] RX ASK MOD IOUT HYST Hysteresis for Current threshold to switch modulation capacitors configurations. The current must be lower than (threshold-hysteresis to switch from high current config to low current config. CFG Bit[7..0] RX ASK MOD VOUT THRES CFG 8V Setting voltage threshold to switch ASK modulation capacitors Step size 100mV DS14078 - Rev 1 Downloaded from Arrow.com. page 34/63 STWLC38 I2C register map Address Register name R/W Default Description Maximum : 0x0D : 13V Bit4:LC HV ASK MOD A1 CFG 1 CFG 1 Modulation capacitor used for under current higher voltage state of mod B - - Bits 0,1,2,3,6,7 : Reserved CFG 1 CFG 1 Modulation capacitor used for under current and voltage state of mod B - - Bits 0,1,2,3,6,7 : Reserved CFG 0 CFG 1 Modulation capacitor used for normal current and higher voltage state of mod B - - Bits 0,1,2,3,6,7 : Reserved CFG 0 CFG 1 Modulation capacitor used for normal current and under voltage state of mod B - - Bits 0,1,2,3,6,7 : Reserved ASK MOD Setting[Byte 0] Modulation capacitor used for under current higher voltage state of mod A Bit5:LC HV ASK MOD B1 Bit4:LC LV ASK MOD A1 ASK MOD Setting[Byte 1] Modulation capacitor used for under current and voltage state of mod A Bit5:LC LV ASK MOD B1 Bit4:NC HV ASK MOD A1 ASK MOD Setting[Byte 2] Modulation capacitor used for normal current and higher voltage state of mod A Bit5:NC HV ASK MOD B1 Bit4:NC LV ASK MOD A1 ASK MOD Setting[Byte 3] DS14078 - Rev 1 Downloaded from Arrow.com. Modulation capacitor used for normal current and under voltage state of mod A Bit5:NC LV ASK MOD B1 page 35/63 STWLC38 I2C register map The default settings are optimized for light and high load conditions. Table 25. RX Protection threshold Address Register name R/W Default Description RX OCP SEL Over current protection threshold 0x00 : 1.25A CFG 1.75A 0x01 : 1.5A 0x02 : 1.75A 0x03 : 1.93A RX THRES HOVP Bits [2..0] Hard Over voltage protection 0x00 : 6.0V CFG 16V 0x01 : 8.0V …... 0x06 : 16V 0x07:18V RX SOVP THRES Bits [6..3] Soft Over voltage protection CFG 4V RX Protection threshold 0x00 : VOUTSET +2.0V 0x01 :VOUTSET + 2.2V …... 0x0F : VOUTSET+ 5.0V CFG RX THRES NTC Bits [15..0] NTC ADC threshold setting CFG RX THRES OCP ADC Bits [15..0] Over current protection ADC threshold setting CFG RX THRES OVTP Bits [15..0] Over temperature protection ADC threshold setting CFG RX THRES VRECT Bits[15..0] VRECT Over voltage protection ADC threshold setting RX TSHUT SEL Bits [1..0] 0x00 : 105°C CFG 115°C 0x01 : 115°C 0x02 : 125°C 0x03 : 135°C Table 26. RX Qi chip ID Address Register name R/W Default RX 01 MFR ID H[Byte 1] RW - RX 02 MFR ID L [Byte 0] RW - RW - RW - RX 04 BDID HL [Byte 2] RW - Basic device ID, byte 2. RX 05 BDID LH [Byte 3] RW - Basic device ID, byte 3. RX 06 BDID LL [Byte 4] RW - Basic device ID, byte 4. RX 07 XID HHH [Byte 1] RW - Extended device ID, byte 1. RX 03 BDID HH [Byte 1] DS14078 - Rev 1 Downloaded from Arrow.com. Description Bit[15..8] Manufacturer ID high byte in ID packet Bit[7..0] Manufacturer ID low byte in ID packet Bit[6..0] Basic device ID, byte 1.(only 7bit available). Bit7: XID EN Enables extended id. page 36/63 STWLC38 I2C register map Address Register name R/W Default Description RX 08 XID HHL[Byte 2] RW - Extended device ID, byte 2. RX 09 XID HLH [Byte3] RW - Extended device ID, byte 3. RX 10 XID HLL [Byte 4] RW - Extended device ID, byte 4. RX 11 XID LHH [Byte5] RW - Extended device ID, byte 5. RX 12 XID LHL [Byte 6] RW - Extended device ID, byte 6. RX 13 XID LLH [Byte 7] RW - Extended device ID, byte 7. RX 14 XID LLL [Byte 8] RW - Extended device ID, byte 8. Transmitter mode (TX) registers Table 27. TX Commands Address Register name R/W Default RW - Description Bit0: TX EN Enable the TX. Write 1 to start Ping 0x0110 TX command [Byte 0] Bit1: TX DIS RW Disable the TX. - Write 1 to stop the inverter and cut the power to Rx 0x0111 TX command [Byte 1] - Reserved Table 28. TX Interrupt enable Address Register name R/W Default Description Bit 0:TX OVTP EN RW - over temperature protection enable 0: disable 1: enable Bit 1:TX OCP EN RW - over current protection enable 0: disable 1: enable 0x0108 Bit 2: TX OVP EN TX Interrupt enable[Byte 0] RW - over voltage protection enable 0: disable 1: enable Bit 3: TX SYS ERR EN RW - system error enable 0: disable 1: enable RW DS14078 - Rev 1 Downloaded from Arrow.com. - Bit4: TX RP PKT RCVD EN RP packet received interrupt enable page 37/63 STWLC38 I2C register map Address Register name R/W Default Description 0: disable 1: enable Bit5:TX CE PKT RCVD EN RW - CE packet received interrupt enable 0: disable 1: enable 0x0108 Bit6:TX SEND PKT SUC EN TX Interrupt enable[Byte 0] RW - Packet sent interrupt enable 0: disable 1: enable Bit7: TX EXT MON EN RW - Ext TX Detect interrupt enable 0: disable 1: enable Bit0:TX CEP TO EN RW - CEP Timeout interrupt enable 0: disable 1: enable Bit1:TX RPP TO EN RW - RPP Timeout interrupt enable 0: disable 1: enable Bit2: TX EPT EN RW - AC powered down interrupt enable 0: disable 1: enable Bit3:TX START PING EN RW 0x0109 - TX Interrupt enable[Byte 1] Ping started interrupt enable 0: disable 1: enable Bit4:TX SS PKT RCVD EN RW - SS ID packet received interrupt enable 0: disable 1: enable Bit5:TX ID PKT RCVD EN RW - ID packet received interrupt enable 0: disable 1: enable Bit6: TX CFG PKT RCVD EN RW - Configuration packet received interrupt 0: disable 1: enable RW DS14078 - Rev 1 Downloaded from Arrow.com. - Bit7:TX PP PKT RCVD EN PP packet received interrupt enable page 38/63 STWLC38 I2C register map Address Register name R/W 0x0109 TX Interrupt enable[Byte 1] Default Description 0: disable 1: enable Bit0:TX BRIDGE MD EN RW - Bridge mode (half/full) changed interrupt. 0: disable 1: enable Bit1:TX FOD DET EN RW 0x010A - TX Interrupt enable[Byte 2] TX FOD detect interrupt enable 0: disable 1: enable Bit2: TX PTC UPDATE EN RW - The power transfer contract is successfully updated after negotiation/renegotiation 0: disable 1: enable 0x010B TX Interrupt enable[Byte 3] - - Bits [3..7] Reserved - - Reserved Table 29. TX Interrupt clear Address Register name R/W Default Description Bit 0: TX OVTP CLR R - over temperature protection clear 1: clear Bit 1:TX OCP CLR R - over current protection clear 1: clear Bit 2: TX OVP CLR R - over voltage protection clear 1: clear Bit 3:TX SYS ERR CLR R 0x0104 - system error clear 1: clear TX Interrupt clear[Byte 0] Bit4:TX RP PKT RCVD CLR R - RP packet received interrupt clear 1: clear Bit5:TX CE PKT RCVD CLR R - CE packet received interrupt clear 1: clear Bit6: TX SCLRD PKT SUC CLR R - Packet sent interrupt clear 1: clear R DS14078 - Rev 1 Downloaded from Arrow.com. - Bit7: TX EXT MON CLR Ext TX Detect interrupt clear page 39/63 STWLC38 I2C register map Address Register name 0x0104 TX Interrupt clear[Byte 0] R/W Default Description 1: clear Bit0:TX CEP TO CLR R - CEP Timeout interrupt clear 1: clear Bit1:TX RPP TO CLR R - RPP Timeout interrupt clear 1: clear Bit2:TX EPT CLR R - AC powered down interrupt clear 1: clear Bit3:TX START PING CLR R 0x0105 - Ping started interrupt clear 1: clear TX Interrupt clear[Byte 1] Bit4:TX SS PKT RCVD CLR R - SS ID packet received interrupt clear 1: clear Bit5: TX ID PKT RCVD CLR R - ID packet received interrupt clear 1: clear Bit6:TX CFG PKT RCVD CLR R - Configuration packet received interrupt clear 1: clear Bit7: TX PP PKT RCVD CLR R - PP packet received interrupt clear 1: clear Bit0:TX BRIDGE MD CLR R - Bridge mode (half/full) changed interrupt clear 1: clear Bit1:TX FOD DET CLR R 0x0106 - TX Interrupt clear[Byte 2] TX FOD detect interrupt clear 1: clear Bit2: TX PTC UPDATE CLR R - The power transfer contract is successfully updated after negotiation/renegotiation clear 1: clear 0x0107 TX Interrupt clear[Byte 3] - - Bits [3..7] Reserved - - Reserved Table 30. TX interrupt latch Address Register name R/W Default TX interrupt latch[Byte 0] R - Description Bit 0:TX OVTP LTCH 0x0100 over temperature protection latch 1: latch DS14078 - Rev 1 Downloaded from Arrow.com. page 40/63 STWLC38 I2C register map Address Register name R/W Default R - Description Bit 1: TX OCP LTCH over current protection latch 1: latch Bit 2:TX OVP LTCH R - over voltage protection latch 1: latch Bit 3:TX SYS ERR LTCH R - system error latch 1: latch Bit4:TX RP PKT RCVD LTCH 0x0100 TX interrupt latch[Byte 0] R - RP packet received interrupt latch 1: latch Bit5:TX CE PKT RCVD LTCH R - CE packet received interrupt latch 1: latch Bit6:TX SLTCHD PKT SUC LTCH R - Packet sent interrupt latch 1: latch Bit7:TX EXT MON LTCH R - Ext TX Detect interrupt latch 1: latch Bit0:TX CEP TO LTCH R - CEP Timeout interrupt latch 1: latch Bit1: TX RPP TO LTCH R - RPP Timeout interrupt latch 1: latch Bit2:TX EPT LTCH R - AC powered down interrupt latch 1: latch Bit3:TX START PING LTCH 0x0101 TX interrupt latch[Byte 1] R -- Ping started interrupt latch 1: latch Bit4:TX SS PKT RCVD LTCH R - SS ID packet received interrupt latch 1: latch Bit5:TX ID PKT RCVD LTCH R - ID packet received interrupt latch 1: latch Bit6:TX CFG PKT RCVD LTCH R - Configuration packet received interrupt latch 1: latch R DS14078 - Rev 1 Downloaded from Arrow.com. - Bit7: TX PP PKT RCVD LTCH page 41/63 STWLC38 I2C register map Address Register name 0x0101 TX interrupt latch[Byte 1] R/W Default Description PP packet received interrupt latch 1: latch 0x0102 Bit0:TX BRIDGE MD LTCH R - R - R - The power transfer contract is successfully updated after negotiation/renegotiation latch - - Bits [3..7] Reserved - - Reserved TX interrupt latch[Byte 2] Bridge mode (half/full) changed interrupt latch Bit1:TX FOD DET LTCH TX FOD detect interrupt latch Bit2: TX PTC UPDATE LTCH 0x0103 TX interrupt latch[Byte 3] Table 31. TX Interrupt status Address 0x010C 0x010D DS14078 - Rev 1 Downloaded from Arrow.com. Register name R/W Default R - R - R - R - R - R - R - R - R - R - R - R - R - R - TX Interrupt status[Byte 0] TX Interrupt status[Byte 1] Description Bit 0:TX OVTP STAT over temperature protection status Bit 1:TX OCP STAT over current protection status Bit 2: TX OVP STAT over voltage protection status Bit 3:TX SYS ERR STAT system error status Bit4:TX RP PKT RCVD STAT RP packet received interrupt status Bit5:TX CE PKT RCVD STAT CE packet received interrupt status Bit6: TX SEND PKT SUC STAT Packet sent interrupt status Bit7:TX EXT MON STAT Ext TX Detect interrupt status Bit0: TX CEP TO STAT CEP Timeout interrupt status Bit1:TX RPP TO STAT RPP Timeout interrupt status Bit2: TX EPT STAT AC powered down interrupt status Bit3:TX START PING STAT Ping started interrupt status Bit4:TX SS PKT RCVD STAT SS ID packet received interrupt status Bit5:TX ID PKT RCVD STAT page 42/63 STWLC38 I2C register map Address Register name R/W Default Description ID packet received interrupt status 0x010D 0x010E TX Interrupt status[Byte 1] Bit6:TX CFG PKT RCVD STAT R - R - R - R - R - The power transfer contract is successfully updated after negotiation/renegotiation status - - Bits [3..7] Reserved - - Reserved TX Interrupt status[Byte 2] Configuration packet received interrupt status Bit7: TX PP PKT RCVD STAT PP packet received interrupt status Bit0:TX BRIDGE MD STAT Bridge mode (half/full) changed interrupt status Bit1:TX FOD DET STAT TX FOD detect interrupt status Bit2: TX PTC UPDATE STAT 0x010F TX Interrupt status[Byte 3] Table 32. TX configuration Address Register name R/W Default Description Bits [7…0] 0x0112 TX FREQ MAX[Byte 0..1] RW - 0x0113 Max frequency specified in units of 16Hz Bits [15…8] Max frequency specified in units of 16Hz Bits [7…0] 0x0114 Min frequency specified in units of 16Hz TX FREQ MIN[Byte 0..1] RW Bits [15…8] 0x0115 Min frequency specified in units of 16Hz Bits [7…0] 0x0116 Ping frequency specified in units of 16Hz TX FREQ PING[Byte 0..1] RW Bits [15…8] 0x0117 Ping frequency specified in units of 16Hz Bits [7…0] DS14078 - Rev 1 Downloaded from Arrow.com. 0x0118 TX DC MAX RW - 0x0119 TX DC MIN RW - 0x011A TX DC PING RW - 0x011B TX PING INTERVAL RW - 0x011C TX PING DURATION RW - 0x0120 TX PLOSS FOD THR RW - Max TX duty cycle %. Max value is 50. Must be >= TX_MIN_DC Bits [7…0] Min TX duty cycle %. Must be